Texas Instruments LM5171-Q1 User manual

User’s Guide
LM5171-Q1 EVM User Guide
ABSTRACT
The LM5171EVM-BIDIR Evaluation Module (EVM) is designed to showcase the LM5171-Q1 high performance
dual-channel bidirectional controller suitable for, but not limited to, the automotive 48-V to 12-V dual battery
system applications.
The EVM can be configured as a bidirectional power converter in the form of either a current source or voltage
source. The direction of power flow can be controlled either by an external command signal or by the on-board
jumper. Through the onboard interface headers, the EVM can be operated by a DSP, an FPGA, an MCU, or
other digital controllers. Two EVMs can be paralleled to make a 3 or 4 phases interleaved converter for higher
power. More EVMs can be paralleled for greater number of phases. Many convenient jumper headers are also
included for versatile configurations of the EVM.
Refer to the LM5171-Q1 Multiphase Bidirectional Current Controller Data Sheet (SNVSC75) for detailed
technical information of the LM5171-Q1 device.
CAUTION
!
Read the user's guide before use.
CAUTION
Hot surface! Contact can cause burns. Do not touch!
Table of Contents
1 Features and Electrical Performance................................................................................................................................... 3
2 Setup........................................................................................................................................................................................5
2.1 EVM Configurations........................................................................................................................................................... 5
2.2 Bench Setup.....................................................................................................................................................................13
2.3 Test Equipment................................................................................................................................................................ 13
2.4 Jumper Settings for Typical Operation Modes................................................................................................................. 13
3 Test Procedure...................................................................................................................................................................... 21
3.1 Buck Mode Power-Up and Power-Down Sequence........................................................................................................ 21
3.2 Boost Mode Power-Up and Power-Down Sequence....................................................................................................... 22
3.3 Bidirectional Operation Power-Up and Power-Down Sequence...................................................................................... 22
3.4 Operating the EVM With External MCU or Other Digital Circuit.......................................................................................22
4 Design Files...........................................................................................................................................................................23
4.1 Schematics.......................................................................................................................................................................23
4.2 Bill of Materials.................................................................................................................................................................26
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4.3 Board Layout....................................................................................................................................................................30
List of Figures
Figure 2-1. Simplified EVM Schematic........................................................................................................................................ 6
Figure 2-2. EVM Board Top View and Layout Partitions..............................................................................................................7
Figure 2-3. Bidirectional Converter Bench Setup...................................................................................................................... 13
Figure 2-4. Jumper Settings in Buck Mode with Voltage Regulation......................................................................................... 14
Figure 2-5. Jumper Settings in Boost Mode with Voltage Regulation........................................................................................16
Figure 2-6. Jumper Settings in Buck Mode with Current Regulation......................................................................................... 17
Figure 2-7. Jumper Settings in Boost Mode with Current Regulation........................................................................................18
Figure 2-8. Jumper Settings in 2-EVM Daisy-Chain for 3 or 4-Phase Operation...................................................................... 19
Figure 4-1. EVM Schematic Part 1: Over view.......................................................................................................................... 23
Figure 4-2. EVM Schematic Part 2: Bias Supplies.................................................................................................................... 23
Figure 4-3. EVM Schematic Part 3: Controller...........................................................................................................................24
Figure 4-4. EVM Schematic Part 4: Outer Voltage Loop........................................................................................................... 24
Figure 4-5. EVM Schematic Part 5: Protection.......................................................................................................................... 25
Figure 4-6. EVM Schematic Part 6: Power stage...................................................................................................................... 25
Figure 4-7. EVM Schematic Part 7: Interface Connectors and Configuration Headers.............................................................26
Figure 4-8. EVM Top Layer Silkscreen...................................................................................................................................... 30
Figure 4-9. EVM Top Layer Copper........................................................................................................................................... 31
Figure 4-10. EVM Middle Layer 1.............................................................................................................................................. 32
Figure 4-11. EVM Middle Layer 2.............................................................................................................................................. 33
Figure 4-12. EVM Middle Layer 3.............................................................................................................................................. 34
Figure 4-13. EVM Middle Layer 4.............................................................................................................................................. 35
Figure 4-14. EVM Middle Layer 5.............................................................................................................................................. 36
Figure 4-15. EVM Middle Layer 6.............................................................................................................................................. 37
Figure 4-16. EVM Bottom Layer Copper................................................................................................................................... 38
Figure 4-17. EVM Bottom Layer Silkscreen...............................................................................................................................39
List of Tables
Table 1-1. Electrical Performance................................................................................................................................................4
Table 2-1. Three-Pin Header Settings......................................................................................................................................... 8
Table 2-2. Two-Pin Header Settings............................................................................................................................................ 9
Table 2-3. J17 60-Pin Header Description(1) ............................................................................................................................. 11
Table 2-4. J18 60-Pin Header Description(1) .............................................................................................................................12
Table 4-1. Bill of Materials..........................................................................................................................................................26
Trademarks
All trademarks are the property of their respective owners.
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1 Features and Electrical Performance
The EVM supports the following features and performance capabilities:
• Input Operating Voltage Ranges
– The 48VDC-Port 6 V to 70 V, in the Buck Mode
– The 12VDC-Port 6 V to 48 V, in the Boost Mode
• Output Voltage Regulation (With the Onboard Outer Voltage Regulation Activated)
– 14.5-V Output Voltage at the 12VDC-Port, in the Buck Mode
– 50.5-V Output Voltage at the 48VDC-Port, in the Boost Mode
• Operating Current
– 60-Adc Maximum from or into the 12VDC-Port
– Typical 1% Current Regulation Accuracy
– Typical 1% Current Monitor Accuracy
• Switching Frequency:
– Standalone Fsw = 100 kHz
– Able to Synchronize to an External Clock from 80 kHz to 120 kHz.
• Maximum Efficiency: >97%
• OVP Threshold
– 75 V at the 48VDC-Port
– 24 V at the 12VDC-Port
• Other Convenient Features
– Optional Onboard SEPIC Converter Providing +10V Supply
– Onboard 5V Bias Voltages and 3.5V Voltage Reference.
– Onboard LM26LV Temperature Sensors Monitoring Local Temperatures of Power MOSFETs, With
Optional Over temperature Shutdown and LED Indicator.
– LED indicators of Buck and Boost Operating Modes.
– Optional Channel Current Shunt AC Filters for Accurate Digital Voltmeter (DVM) Reading.
– Onboard Two Stage RC Filter for PWM Input to ISET (J33).
– ISET Voltage Clamp Input (J43).
– Square Wave Input for Dithering (J14).
– I2C Interface for Monitoring and Diagnose. (J31)
The electrical performance of the EVM is show in Table 1-1. Figure 2-1 shows the simplified EVM schematic.
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Table 1-1. Electrical Performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
48VDC-Port Buck mode operation (DIR > 2 V) 6 48 70 V
12VDC-Port Boost mode operation (DIR < 1 V) 6 12 48 V
OUTPUT CHARACTERISTICS
Current delivery 12VDC-Port input or output current (dual-channel
enabled) 0 60 A
Current regulation accuracy 12VDC-Port current vs ISETA command voltage 1%
Channel current monitor
accuracy
When onboard IOUT1 and IOUT2 termination filter
activated 1%
48VDC-Port Boost mode operation (DIR < 1 V, onboard analog
output voltage loop closed) 50.5 V
12VDC-Port Buck mode operation (DIR > 2 V, onboard analog
output voltage loop closed) 14.5 V
SYSTEM CHARACTERISTICS
Switching frequency 100 kHz
External clock
synchronization 80 120 kHz
Full load efficiency 97%
Junction temperature, TJ–40 150 °C
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2 Setup
2.1 EVM Configurations
Figure 2-2 shows the EVM board top view and circuit layout partitions. The EVM has the following ports:
• 48VDC-Port: Connected to 48-V battery rail
• 12VDC-Port: Connected to 12-V battery rail
• J17 (60-Pin Header): Interfacing the external control commands or MCU
• J18 (60-Pin Header): Interfacing J17 of the secondary EVM in a 4-phase system consisting of two EVMs
• Channel Current Setting: Analog programming at J17-pin 11, and digital programming at J17-pin 13
• I2C interface for diagnosis and monitory functions at J45.
Table 2-1 through Table 2-4 list the functions of the EVM jumpers and headers. They offer flexible configurability
and programmability of the EVM for various use cases including but not limited to the following:
• A unidirectional or bidirectional voltage source
• A unidirectional or bidirectional current source
• Dynamic phase adding and shedding in a 4-phase system consisting of two EVMs
• Dynamic MOSFETs dead time adjustment
• Individual channel current monitoring or total current monitoring
• Synchronization to external clock
• External shutdown command through DT/nSD pin (J17-pin45)
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23
1 m 
2022 32 31
470 µF
PGND
12
1
HO1
HB1
LO1
CSA1
CSB1
VDD
VREF
19 VCC
26
45
27
DIR1
UVLO
EN1
10 EN2
39
AGND
40 SYNCI
11 DIR2
SYNCO
43 AGND 48
47
41
VSET
IPK
OPT
14
0.22 µF
PGND
1 m

1715 5 6
PGND
HO2
HB2 LO2 CSA2 CSB2
ENABLE
DIR
29COMP1
8COMP2
0.1 µF 3.65 k

VCC
VCC
1 nF
28
9
36
AGND
SS/DEM1
SS/DEM2
OVP
44CFG
33 nF
95.3 k

25 LDODRV
21
SW1
16
SW2
0.22 µF
46 DT/SD
PGND
+
HV-Port
-
+
LV-Port
-
100 µF
100 µF
PGND
470 µF
LM5171-Q1
CMMD AND
MONITOR
C2
C1 CHB1
QH1
QL2
CVCC
C8
CHB2
C10
CSS
CHF1
CCOMP1
QH2
QL2
RCS2
ROSC
ROVPT
RCFG
RCOMP1
DHB1
DHB2
18
PGND
PGND
CCOMP2
Lm1 RCS1
Lm2
2

RHB1
2

RHB2
15 k

RDT
2.2 µF
Qbias
Daux
AGND
SD
33 IMON1
4IMON2
10 k

10 nF
AGND
IMON2
CIMON2 RIMON2
37 SDA
38 SCL
SDA
SCL
10 k

10 nF
AGND
IMON1 CIMON1 RIMON1
0.1 µF
CVDD
0.1 µF
CVREF
0.1 µF
15 k

20 k

CVSET
100 pF
30.1 k

10 k

CIPK
0.1 µF
3.65 k

1 nF
CHF2
RCOMP2
42
OSC
41.2 k

35 FBHV
34 ERRHV
24
13
HV1
HV2
10

RHV
0.1 µF
CHV
PGND
33 nF
75 k

100 pF
CHHF
CHCOMP RHCOMP
RHFBT
RHFBB
30ISET1
2
FBLV
3
ERRLV
7ISET2
10 nF
49.9 k

100 pF
CLHF
CLCOMP
RLCOMP
RLFBT
ROVPB
1 k

4.02 k

ERRLV
AGND
ERRHV
RISETT
RISETB
4.42 k

AGND
RLFBB
26.7 k

2.1 k

AGND
49.9 k

1 k

23.2 k

AGND
PGND AGND
RIPKT RIPKB
RVSETT RVSETB
NC
1

1

RCSA1 RCSB1
CCS1
NC
1

1

RCSA2 RCSB2
CCS2
100p
CISET
4.7 µH
4.7 µH
AGND
Figure 2-1. Simplified EVM Schematic
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Figure 2-2. EVM Board Top View and Layout Partitions
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Table 2-1. Three-Pin Header Settings
HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
J1 UVLO
--(1) External UVLO command through J17
(1,2)(2) 48VDC-Port UVLO Control Y
(2,3)(3) 12VDC-Port UVLO Control
J6 OPT
-- External interleaving control through J17
(1,2) CH-2 240 degree delay from CH-1
(2,3) CH-2 180 degree delay from CH-1 Y
J13 SYNC -- Secondary EVM not sync to main EVM Y
(1,2) Secondary EVM sync to main EVM
(2,3) Secondary EVM sync to external clock
J26 OTEMP
-- Onboard Over temperature protection inactive Y
(1,2) Over temperature protection in hiccup mode
(2,3) Over temperature protection in latched shutdown
J28 DIR
-- External DIR control through J17
(1,2) Onboard DIR command for buck operation Y
(2,3) Onboard DIR command for boost operation
J29 EN1
-- External CH-1 enable control through J17
(1,2) Onboard CH-1 enable Y
(2,3) Onboard CH-1 inactive
J30 EN2
-- External CH-2 enable control through J17, overridden by
J24. Y
(1,2) Onboard CH-2 enable
(2,3) Onboard CH-2 inactive
J34 CFG
-- I2C address set to 0x0 is not selected
(1,2) I2C address set to 0x0, and select inductor current monitor Y
(2,3) I2C address set to 0x0, and select output current monitor
J35 CFG -- I2C address set to 0x1 is not selected Y
(1,2) I2C address set to 0x1, and select inductor current monitor
(2,3) I2C address set to 0x1, and select output current monitor
J36 ISET -- External ISET control through J17
(1,2) Onboard voltage loop Y
(2,3) External digital voltage loop
(1) – = All jumper pins open.
(2) (1,2) = Pins 1 and 2 closed.
(3) (2,3) = Pins 2 and 3 closed.
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Table 2-2. Two-Pin Header Settings
HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
J2 IMON1 C(1) IMON1 filter connected Y
O(2) IMON1 filter disconnected
J3 nSD C Shutdown
O External shutdown via J17 Y
J4 SS/DEM1 C CH-1 set to DEM Y
O CH-1 set to FPWM
J5 SS/DEM2 C CH-2 set to DEM Y
O CH-2 set to FPWM
J7 IMON2 C IMON2 filter connected Y
O IMON2 filter disconnected
J12 Dithering C dithering control allowed
O dithering control not allowed Y
J14 SQIN C Not allowed
O square wave input for dithering control Y
J15 SS/DEM1 & SS/
DEM2
C SS/DEM1 & SS/DEM2 are connected Y
O SS/DEM1 & SS/DEM2 are independent
J16 Main & Secondary
EVM IMON1
C Main EVM & Secondary EVM IMON1 signal merged
O Main EVM & Secondary EVM IMON1 signal not merged Y
J19 Main & Secondary
EVM 10V VCC
C Main EVM & Secondary EVM 10V VCC connected
O Main EVM & Secondary EVM 10V VCC not connected Y
J20 Main & Secondary
EVM SD_CMD
CMain EVM & Secondary EVM SD_CMD connected for
simultaneous shutdown
OMain EVM & Secondary EVM SD_CMD not connected for
independent shutdown Y
J21 IMON1 & IMON2 C Combined channel current monitors
O Independent dual-channel current monitor Y
J22 Main & Secondary
EVM UVLO
C Main EVM & Secondary EVM UVLO connected
O Main EVM & Secondary EVM UVLO not connected Y
J23 Main & Secondary
EVM EN1
C Main EVM & Secondary EVM EN1 connected
O Main EVM & Secondary EVM EN1 not connected Y
J24 EN1 & EN2 C Combined channel enable Y
O Independent dual-channel enable
J25 USB2ANY pullup for
SCL
C Pullup by USB2ANY board
O Pullup by external signal source through J17 Y
J32 OPT/
EN2_secondary
C 3- and 4-phase auto transition
O 3- and 4-phases auto transition inactive Y
J33 PWM input for ISET C Not allowed
O External PWM input for ISET Y
J37 buck/boost LED
indicator
C Having LED indicator Y
O No LED Indicator
J38 Onboard bias supply
output connection
C VCC supplied by onboard VCC. Y
O Onboard bias supply output disconnected from VCC.
J39 External VCC supply
input
C Not allowed
O External 10-12V input port for VCC Y
J40 Onboard bias supply
enable
C Onboard bias supply enabled Y
O Onboard bias supply inactive
J41 Onboard bias supply
input connection
CSepic input is energized by 48V-port Y
OSepic input is disconnected and not energized
J42 CC Control C CC control allowed
O CC control inactive Y
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Table 2-2. Two-Pin Header Settings (continued)
HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
J43 CC Control Input C Not allowed
O CC control input port Y
J44 USB2ANY pullup for
SDA
C Pullup by USB2ANY board
O Pullup by external signal source through J17 Y
(1) Jumper pins Closed.
(2) Jumper pins Open.
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Table 2-3. J17 60-Pin Header Description(1)
PIN SIGNAL I/O DESCRIPTION
1 V48SN O(2) 48V-port voltage sense during operation
3 V12SN O 12V-port voltage sense during operation
5 UVLO I(3) Main EVM enable (connect to the UVLO pin of the IC)
7 EN1 I CH-1 control (connect to the EN1 pin of the IC)
9 DIR I Direction command
11 ISETA I Analog command for ISET
13 ISETD I Digital PWM command for ISET
15 SYNCIN I Input of the external clock to be synchronized to
17 SYNCOUT O Clock output signal
19 OPT I Interleave angle setting
21 EN2 I CH-2 control (connect to the EN2 pin of the IC)
23 DEM O FPWM/DEM selection
25 +5V O Onboard 5V bias supply
27 IMON1 O CH-1 monitor
29 IMON2 O CH-2 current monitor
31 IMON1_S O Secondary EVM CH-1 monitor in 3 or 4 phases
33 IMON2_S O Secondary EVM CH-2 current monitor in 3 or 4 phases
35 AGND I/O Reference GND for control signals
37 PGND O Power ground of the DC-DC converter
39 SDA I SDA of I2C
41 SCL I SCL of I2C
43 +10 V I/O +10V bias supply
45 nSD I/O External shut down command input pin
47 ENABLE_S I Secondary EVM enable (connect to the UVLO pin of the secondary IC)
49 CH1_S I Secondary EVM CH-1 control (connect to the EN1 pin of the secondary IC)
51 CH2_S I Secondary EVM CH-2 control (connect to the EN2 pin of the secondary IC)
53 SYNCIN_S I Input of the external clock for the secondary EVM to be synchronized to
55 SYNCOUT_S O Secondary EVM clock output signal
57 nSD_S I/O Secondary EVM external shut down command input pin
59 KEY — No Connect
All even
number pins AGND I/O All signals’ return
(1) J17 is the interface connector to MCU, or external digital controller, or to J18 of the main EVM if the host EVM serves as a secondary
EVM in the multiphase configuration.
(2) I = input pin
(3) O = output pin
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Table 2-4. J18 60-Pin Header Description(1)
PIN SIGNAL I/O DESCRIPTION
1 V48_X — No Connect
3 V12_X — No Connect
5 ENABLE_S I(2) Secondary EVM enable (connect to the UVLO pin of the secondary IC)
7 CH1_S I Secondary EVM CH-1 control (connect to the EN1 pin of the IC)
9 DIR I Direction command
11 ISETA I Analog command for ISET
13 ISETD I Digital PWM command for ISET
15 SYNCIN_S I The external clock input for the secondary
17 SYNCOUT_S O(3) Secondary EVM clock output signal
19 OPT I Interleave angle setting
21 CH2_S I Secondary EVM CH-2 control (connect to the EN1 pin of the IC)
23 DEM_S I FPWM/DEM selection
25 +5 V I Onboard 5V bias supply
27 IMON1_S O Secondary EVM CH-1 monitor in 3 or 4 phases
29 IMON2_S O Secondary EVM CH-2 current monitor in 3 or 4 phases
31 IMON1_X — Not used
33 IMON2_X — Not used
35 AGND I/O Reference GND for control signals
37 PGND O Power ground of the DC-DC converter
39 SDA I SDA of I2C
41 SCL — SCL of I2C
43 +10 V I Onboard +10-V bias supply
45 nSD_S I/O Secondary EVM external shut down command input pin
47 UVLO_X — No Connect
49 CH1_X — No Connect
51 CH2_X — No Connect
53 SYNCIN_X — No Connect
55 SYNCOUT_X — No Connect
57 SD_X — No Connect
59 KEY — No Connect
All even
number pins AGND I/O All signals’ return
(1) J18 is the interface connector to the secondary EVM in the multiphase configuration if the host EVM serves as the main. All control
commands and control signals are sent through J18 to J17 of the secondary EVM.
(2) I = input pin
(3) O = output pin
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2.2 Bench Setup
For buck mode or boost mode operation, one Power Supply (PS) and one Electronic Load (E-Load) are enough
to perform the test as shown in Jumper Settings for Typical Operation Modes.
For bidirectional operation, Figure 2-3 shows the typical bench setup to operate the EVM in the bidirectional
power system environment. The combination of the E-Load and bench PS emulates a battery capable of both
sourcing and sinking current. A relatively Higher Voltage Power Supply (HV-PS) and E-Load (HV-E-Load) are
needed for the 48VDC-port, and a Lower Voltage Power Supply (LV-PS) and E-Load (LV-E-Load) are needed for
the 12VDC-port.
The user can externally provide the dashed line signals, or use the onboard jumpers to set these signals, when
operating the EVM.
PSE-Load
LM5171-Q1
Bi-Directional
Converter
V48 V12
RTN RTN
PS E-Load
+
–
+
–
UVLO EN1/2 DIR ISETA or ISETD+10V
Figure 2-3. Bidirectional Converter Bench Setup
To operate the EVM to full power, follow the guidelines below for initial setup:
• Set the LV-E-Load to Constant Current (CC) of 62 A
• Set the LV-PS voltage at 12 V, and the current limit at 63 A
• Set the HV-E-Load to CC of 14 A
• Set the HV-PS voltage at 48 V, and the current limit at 15 A
2.3 Test Equipment
Power Supplies: HV-PS needs to be capable of 80V/20A, and LV-PS 40V/80A. To operate 2 EVMs in 4 phase
configuration, double the capabilities of the HV-PS and LV-PS. Bench power supplies to generate UVLO, ISETA,
DIR, and EN1 and EN2 signals need to be capable of 5V/0.1A.
Electronic Loads: The HV-E-Load needs to be capable of 80V/20A, and LV-E-Load 40V/80A. To operate 2
EVMs in 4 phase configuration, double the capability of the E-Load.
Meters: Because most current meters are rated only to 10 A, shunts are recommended to measure the current
using a DVM.
Oscilloscope: An oscilloscope and 10x probes with at least 20-MHz bandwidth is required. Current probe
capable of 50 A is required to monitor the inductor current via a wire loop inserted to the non-switching side of
the inductor.
2.4 Jumper Settings for Typical Operation Modes
Refer to the following sections for EVM jumper settings for some typical operation modes.
•Buck Mode with Voltage Regulation
•Boost Mode with Voltage Regulation
•Buck Mode with Current Regulation
•Boost Mode with Current Regulation
•2-EVM Daisy-Chain for 3 or 4-Phase Operation
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The jumper connections are shown as small red rectangular box, which indicating the short of the enclosed two
pins of the jumper header.
2.4.1 Buck Mode with Voltage Regulation
Jumper Settings in Buck Mode with Voltage Regulation shows the jumper settings of buck mode with voltage
regulation. This is the default jumper setting of the EVM.
+
–
Source
6~70V
Load
CC 0~60A
Figure 2-4. Jumper Settings in Buck Mode with Voltage Regulation
The status of the EVM is as follows:
• UVLO: 48 V via J1
• Phase interleaving angle: 180° via J6
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• DIR: Buck mode via J28
• EN1: Enable via J29
• CFG: I2C address set to 0x0 & inductor current monitor via J34
• Voltage loop: Closed via J36
• IMON1: Filter connected via J2
• IMON2: Filter connected via J7
• SS/DEM1: DEM mode via J4
• SS/DEM1: DEM mode via J5
• SS/DEM2 connected to SS/DEM1 via J15
• EN2: Select EN2=EN1 via J24
• LED indicator: ON via J37
• VCC supply: Select onboard bias power via J38
• Onboard bias power: Enabled via J40
• Onboard bias power input: 48 V via J41
Note the load needs to be set to CC mode.
2.4.2 Boost Mode with Voltage Regulation
Jumper Settings in Boost Mode with Voltage Regulation shows the jumper settings of boost mode with voltage
regulation.
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Load
0~14A
+
–
Source
6~20V
Figure 2-5. Jumper Settings in Boost Mode with Voltage Regulation
Compared to Buck Mode with Voltage Regulation, J28-pin 2,3 is closed for boost mode. Also note the source
and load are exchanged from that of buck mode.
2.4.3 Buck Mode with Current Regulation
Figure 2-6 shows the jumper settings of buck mode with current regulation.
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+
–
Source
6~70V
+
–
Load
CV 0~20V
+
–
Precision Voltage Souce
1000mV ~ 2200mV
Figure 2-6. Jumper Settings in Buck Mode with Current Regulation
Compared to Buck Mode with Voltage Regulation, J36 is open and ISET is set from external precision voltage
source . Also note the load needs to be set to CV mode.
2.4.4 Boost Mode with Current Regulation
Figure 2-7 shows the jumper settings of boost mode with current regulation.
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+
–
+
–
Load
CV ~70V
+
–
Precision Voltage Souce
1000mV ~ 2200mV
Source
6~20V
Figure 2-7. Jumper Settings in Boost Mode with Current Regulation
Compared to Buck Mode with Current Regulation, J28-pin 2,3 is closed for boost mode. Also note the source
and load are exchanged from that of buck mode.
2.4.5 2-EVM Daisy-Chain for 3 or 4-Phase Operation
Figure 2-8 shows the jumper settings for 2-EVM Daisy-Chain.
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+
–
Source
6~70V
Load
CC 0~14A
+
–
Source
6~20V
Load
CC 0~60A
Main EVM
Secondary EVM
Figure 2-8. Jumper Settings in 2-EVM Daisy-Chain for 3 or 4-Phase Operation
Jumper Settings in 2-EVM Daisy-Chain for 3 or 4-Phase Operation described four-phase operating with 90°
interleaving. By connecting secondary EVM J30 pin 2,3 instead of pin 1,2, three-phase operating is obtained.
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J6 is open and J32 is closed in main EVM, thus interleaving angle changes automatically between 3 phase and
4 phase.
Note for bidirectional operation, the source and load needs to be set referring to Bench Setup.
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20 LM5171-Q1 EVM User Guide SNVU843 – APRIL 2023
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