Texas Instruments ADS64XX EVM User manual

ADS64XX EVM User's Guide
User's Guide
April 2007
SLAU196

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Contents
1 Overview .................................................................................................................... 51.1 ADS64XX EVM Quick-Start Procedure ....................................................................... 52 Circuit Description ...................................................................................................... 72.1 Schematic Diagram .............................................................................................. 72.2 ADC Circuit Function ............................................................................................ 72.3 Deserialization and the TSW1200 ............................................................................. 93 ADC Evaluation ......................................................................................................... 103.1 Hardware Selection ............................................................................................ 103.2 Coherent Input Frequency Selection ......................................................................... 114 Physical Description .................................................................................................. 134.1 PCB Layout ...................................................................................................... 134.2 Bill of Materials .................................................................................................. 194.3 PCB Schematics ................................................................................................ 21
Important Notices ............................................................................................................... 26
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List of Figures
1................................................................................................................................. 82................................................................................................................................. 83 ADS64XX EVM Setup ..................................................................................................... 124 Layer 1, Top Silkscreen ................................................................................................... 135 Layer 2, Top Side .......................................................................................................... 146 Layer 3, Gound Plane ..................................................................................................... 157 Layer 4, Power Plane ...................................................................................................... 168 Layer 5, Bottom Side ...................................................................................................... 179 Layer 6, Bottom Silkscreen ............................................................................................... 1810 Sheet 1 of 5 ................................................................................................................. 2111 Sheet 2 of 5 ................................................................................................................. 2212 Sheet 3 of 5 ................................................................................................................. 2313 Sheet 4 of 5 ................................................................................................................. 2414 Sheet 5 of 5 ................................................................................................................. 25
List of Tables
1 Three-Pin Jumper List ....................................................................................................... 52 Surface Mount Jumpers..................................................................................................... 93 ADS64XXEVM Bill of Materials ........................................................................................... 19
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1 Overview
1.1 ADS64XX EVM Quick-Start Procedure
User's GuideSLAU196 – April 2007
This user's guide gives a general overview of the evaluation module (EVM) and provides a generaldescription of the features and functions to be considered while using this module. This manual isapplicable to the ADS6445, ADS6444, ADS6443, ADS6425, ADS6424, and ADS6423, which collectivelyare referred to as ADS64XX. The ADS64XX EVM provides a platform for evaluating the quad-channelADS64XX 14- and 12-bit analog-to-digital converters (ADC) under various signal, reference, and supplyconditions. In certain instances, the user's guide may offer directions for only the 14-bit ADC family, whichis referred to as the ADS644X, or only the 12-bit ADC family, which is referred to as the ADS642X. Inaddition, this user's guide explains the procedure for hooking up the ADS64XX EVM to TI's high-speedLVDS deserializer, the TSW1200.
This document should be used in combination with the respective ADC datasheet.
Using the quick-start procedure, many users can begin evaluating the ADC in a minimal amount of time.The quick-start procedure includes details on how to set up the ADS64XX EVM used in conjunction withTI's high-speed LVDS deserializer. A complete listing of all EVM features follows in Section 2 . Thequick-start instructions are delineated as ADS64XX, which refers to instructions pertaining to the ADCEVM; or TSW1200, which refers to instructions pertaining to the high-speed LVDS deserializer.1. ADS64XX: Verify all jumper settings against the schematic jumper list in Table 1 :
Table 1. Three-Pin Jumper List
JUMPER FUNCTION ADS644X DEFAULT ADS642X DEFAULT
J16 Sets ADC coarse gain mode and ADC reference mode. Use 0-dB gain, internal 0-dB gain, internalsilkscreen for configuration. references referencesJ17
(1)
Sets ADC output mode to either 1-wire, 2-wire, SDR, or DDR. DDR, 2-wire DDR, 2-wireUse silkscreen for configuration.J18 Sets ADC output serialization to either 14X or 16X and sets 16X, rising edge 14X, rising edge
(2)
data formatting to rising edge or falling edge when the ADC isused in SDR mode. Use silkscreen for configuration.J19
(1)
This is an ADC reserved pin and should always be set to Divide by 1 Divide by 1divide by 1.J20
(1)
Selects the data output format as MSB- or LSB-first and MSB-first, 2s-complement MSB-first, 2s-complement2s-complement or offset-binary.(1)
The high-speed LVDS deserializer requires data in a certain output format. Changing these to values other than the defaultwould require a recompilation of the FPGA source code with the appropriate format decoding options and an update to theFPGA PROM with the compiled file. Changing the default values without loading in a new FPGA design results in improperoperation. By default, the PROM stores two FPGA files, one for 12-bit ADCs and one for 14-bit ADCs.(2)
The silkscreen on the EVM only refers to the modes of the ADS644X. When an ADS642X, or 12-bit ADC, is being evaluated,the silkscreen 14X refers to the 12X serialization mode and the silkscreen 16X refers to the 14X serialization mode.2. ADS64XX: Connect 3.3-V dc supplies to P1 and P3, with the returns to P2 and P4, respectively. Thegrounds can be shorted together.3. TSW1200: Connect 5 V dc to J15 and the return to J14.4. TSW1200: If evaluating the 12-bit ADC, or ADS642X, verify that jumper J11 is set to short pins 1–2,which configures the FPGA for deserialization of a 12-bit ADC serial data stream. On J11, short pins2–3 for evaluating an ADS644X EVM.5. Connect the two boards together by connecting J9 on the TSW1200 circuit board to J15 of theSamtec is a trademark of Samtec, Inc.Xilinx is a trademark of Xilinx, Inc.All other trademarks are the property of their respective owners.
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Overview
ADS64XX EVM.6. ADS64XX and TSW1200: Switch power supplies on.7. ADS64XX: Using a low-phase-noise, filtered frequency generator with 50- Ωsource output impedance,generate a 0-V offset, 1.5-Vrms sine-wave clock into J12. The frequency of the clock must be withinthe specification for the device speed grade. TI uses an Agilent 8644B with a crystal MCF filter as aclock source.8. TSW1200: Depress SW4 (FPGA reset). This resets the logic inside the FPGA and must be done everytime one changes the ADC clock frequency.9. ADS64XX: Using a low-phase-noise, filtered frequency generator with a 50- Ωsource outputimpedance, generate a 10-MHz, 0-V offset, –1-dBFS-amplitude sine-wave signal into either J10 (inputchannel A) or J11 (input channel B). This provides a transformer-coupled differential input signal to theADC. TI uses an Agilent 8644B with an LC filter as a signal source.10. TSW1200: The deserialized parallel output data can be probed using a logic analyzer on J5 for inputsto ADC channel A and on J4 for inputs to ADC channel B. On both output headers, the clock can befound on the respective output header on pin 2, and the LSB can be found on pin 6.
Note: Any time the clock frequency of the ADC changes during the ADC evaluation, one must resetthe FPGA deserializer by depressing SW4. This allows the deserializer to re-align the ADCdata capture to the new output clock frequency.
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2 Circuit Description
2.1 Schematic Diagram
2.2 ADC Circuit Function
2.2.1 ADC Operational Mode
2.2.2 ADC Power
2.2.3 ADC Analog Inputs
Circuit Description
The schematic diagram for the EVM is in Section 4.3 .
The following sections describe the function of individual circuits. Refer to the relevant data sheet fordevice operating characteristics.
By default, the ADC is configured to operate in parallel-mode operation, because the surface-mountjumper asserts a 3.3-V state to the ADC reset pin. Consequenty, the SW1 reset pushbutton must bepressed only when the device is configured into serial operational mode. Because the ADC is in paralleloperation mode, voltages are used to set the ADC modes. Users can use the EVM silkscreen to set theoperation modes.
Power is supplied to the EVM via banana jack sockets. Separate connections are provided for a 3.3-Vdigital buffer supply (P1) and 3.3-V analog supply (P3). In most cases, these can be shorted together forADC evaluation. When using the amplifier evaluation path, users must connect the positive rail to J21 andthe negative rail to J22. The voltages depend on the coupling method and connection to the ADC. If theADC VCM is not supplied to the amplifier and the amplifier is connected to the ADC in a dc-coupledfashion, users should set J21 to 4 V and J22 to –1 V. In ac-coupled configurations where the ADC VCMbiases the ADC inputs, users can connect J21 to 5 V and J22 to GND.
The EVM is configured to accept a single-ended input souce and convert it to an ac-coupled differentialsignal using a transformer. The inputs to the ADC must be dc-biased, which is accomplished by using theADC VCM output. The inputs are provided via SMA connectors J10 for ADC channel A, J11 for ADCchannel B, J13 for ADC channel C, and J14 for ADC channel D. ADC input channel C also includes theoption for ADC evaluation using an amplifier signal chain.
TI has tested this ADC with a variety of transformer brands, transorfmer configurations and terminations.For many applications, a single low-cost transformer can be used in the input signal chain to a very highdegree of performance. Customers should select a transformer configuration based on their ADC inputbandwidth frequency. To assist in this process, TI has swept the analog input frequency and plotted theresulting ADC SFDR performance with various transformers. Figure 1 and Figure 2 show the ADCperformance using the Mini-Circuits TC1-1T, Mini-Circuits TC4-1W, and Coilcraft WBC1-1TLB in one- andtwo-tranformer configurations, respectively. In both plots, the results were taken on an ADS6443, samplingat 80 MSPS and on the same input channel. The termination was changed according to the impedanceratio of the transfomer used.
Using SMA input J2, users can evaluate the ADC using a THS4509 amplifier, which converts asingle-ended input into a differential signal while providing 10 dB of signal gain. Users should enable theamplifier path by connecting JP6 1–2 and by shorting positions 1–2 on both surface-mount jumpers JP1and JP2. At low input frequencies, the ADC represents a high input impedance and R10, R19, and C45form a low-pass filter with a 3-db cutoff frequency of 70 MHz. Users should change these componentvalues depending on the bandwidth of the signal they are digitizing to band-limit the input noise into theADC. Using an excessively high cutoff frequency degrades the SNR of the system. Before users beginevaluation of the amplifier path, one most choose whether to dc-couple or ac-couple to the amplifier path.
In a dc-coupled system, users should replace C46 and C47 with 0- Ωresistors and remove R9 and R18.The ADC VCM should be used to set the CM input of the amplifier by making sure R84 is populated with a0- Ωresistor. Because the ADC has a common-mode voltage of 1.5 V, and because the THS4509 is not arail-to-rail amplifier, users should adjust VCC to 4 V and –VCC to –1 V, which can be done by applying therespective voltages to J21 and J22.
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45
50
55
60
65
70
75
80
85
90
95
100
f − Frequency − MHz
SFDR − Spurious−Free Dynamic Range − dBc
G001
9.97 30.13 50.13 69.59 89.75 130.13 230.53 301.13 401.13 501.13
Mini Circuits
TC4−1W
Mini Circuits
TC1−1T
Coilcraft
WBC1−1TLB
45
50
55
60
65
70
75
80
85
90
95
100
f − Frequency − MHz
SFDR − Spurious−Free Dynamic Range − dBc
G002
9.97 30.13 50.13 69.59 89.75 130.13 230.53 301.13 401.13 501.13
Mini Circuits
TC4−1W
Mini Circuits
TC1−1T
Coilcraft
WBC1−1TLB
Circuit Description
For an ac-coupled system, users should use the voltage divider R9 and R18 to set the common-modeinput of the amplifier, which should be set to the midpoint of the amplifier supply. C46 and C47 ac-couplethe system, and the ADC inputs can then be biased by the R14 and R15 combination. Another ac-coupledapproach, not supported on this EVM, would be to use a transformer at the outputs of the THS4509. Inthis case, the transformer would provide for ac-coupling, and one could bias the inputs of the ADC byfeeding the ADC VCM to the transformer center tap on the secondary.
It should be noted that the THS4509 used on this EVM is pinout-compatible with the THS4508, THS4511,THS4513, and THS4520. Users can easily interchange the amplifier on this EVM and should pick theappropriate amplifier based on commmon mode range, power supplies, and frequency of operation. TIapplication engineers can assist in the best selection of these amplifiers based on the user requirements.
SFDR vs Frequency Using a Single Transformer
Figure 1.
SFDR vs Frequency Using a Dual Transformer
Figure 2.
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2.2.4 ADC Clock Input
2.2.5 ADC Digital Outputs
2.2.6 Surface-Mount Jumper Selections
2.3 Deserialization and the TSW1200
Circuit Description
Users should connect a filtered, low-phase-noise clock input to J12. A transformer, T5, provides theconversion from a single-ended clock signal into a differential clock signal. When selecting the clock signallevel, users should account for the transformer having an impedance ratio of 4, with a voltage step-upof 2.
The ADS64XX ADC outputs serialized data, a bit clock (DCLK), and a frame clock (FCLK). These signalsare brought to a high-density Samtec™ connector, J15. Users have three options in processing the ADCdata.
1. Customers can use the mating logic analyzer breakout board and capture the ADC data using a logicanalyzer. Users would be required to perform a software deserialization of the digital data beforeconducting analysis. Contact the factory for a breakout board for your logic analyzer.2. Customers can create their own digital interface card which directly interfaces to the ADC. In this case,customers would design their mating digital interface board with the Samtec part numberQSH-060-01-F-D-A, which is the companion part number to the EVM connector.3. In most cases, customers can use a hardware deserialization solution such as the TSW1200. TheTSW1200 features a powerful Xilinx™ Virtex 4 that comes preloaded with both 12-bit and 14-bitdeserialization routines. In addition, customers can use the FPGA to develop their own deserializer anddigital prototypes. The digital output of the TSW1200 easily plugs into logic analyzers or TI's owndigital capture and analysis solution, the TSW1100.
The EVM features surface-mount jumpers in cases where either the signal integrity is important or thefunctions are not often used. Table 2 summarizes these options.
Table 2. Surface Mount Jumpers
ADC Reference Designator Default Selection Optional SelectionSignal
RESET J7 2–3, parallel mode operation 1–2, serial modeoperationSCLK J6 Not populated, pin tied low 1–2, TSW1200 controlover SCLKSDATA J8 Not populated, pin tied low 1–2, TSW1200 controlover SDATASEN J5 2–3: EVM J16 controls parallel operation modes 1–2, TSW1200 controlover SENPD J9 Not populated, pin tied low, device operational 1–2, TSW1200 controlover PDINC_M JP1 2–3, Transformer-coupled analog input to channel C 1–2, Amplifier-coupled
path to channel CINC_P JP2 2–3, Transformer-coupled analog input to channel C 1–2, Amplifier-coupled
path to channel C
While the specifics of the deserializer are out of the scope of this user's guide, TI has partnered up withXilinx to deliver an open-source deserializer solution with application note documentation. When designingthe deserializer, users should consult Xilinx application note XAPP866, hosted on the Xilinx website. Inaddition, TI has provided a guide to understanding the different digital output modes of the ADC and howto pick the most appropriate digital output mode for deserialization. Users should consult Demystifying theDigital Output Choices of the ADS6XXX, TI application note SLAA348 .
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3 ADC Evaluation
3.1 Hardware Selection
3.1.1 Analog Input Signal Generator
3.1.2 Clock Signal Generator
ADC Evaluation
This chapter describes how to set up a typical ADC evaluation system that is similar to what TI uses toperform testing for datasheet generation. Consequently, the information in this section is generic in natureand is applicable to all high-speed, high-resolution ADC evaluations. This chapter covers signal toneanalysis, which yields ADC datasheet figures of merit such as signal-to-noise ratio (SNR) and spuriousfree dynamic range (SFDR).
To reveal the true performance of the ADC under evaluation, tremendous care should be taken inselecting both the ADC signal source and ADC clocking source. The hardware setup that TI uses for itsanalysis is shown graphically in Figure 3 .
When choosing the quality of the ADC analog input source, one should consider both harmonic distortionperformance of the signal generator and the noise performance of the source.
In many cases, the harmonic distortion performance of the signal generator is inferior to that of the ADC,and additional filtering is needed if users expect to reproduce the ADC SFDR numbers found in the datasheet. Users can easily evaluate the harmonic distortion of their signal generator by hooking it directly to aspectrum analyzer and measuring the power of the output signal and comparing that to the power of theinteger multiples of the output signal's frequency. If the harmonic distortion is worse then the ADC underevaluation, the ADC digitizes the performance of the signal generator and the ADC's true SFDR ismasked. To alleviate this, it is recommended that users provide additional LC filtering after the signalgenerator output.
Another important metric when deciding on a signal generator is its noise performance. As with thedistortion performance, if the noise performance is worse than that of the ADC under evaluation, the ADCdigitizes the performance of the source. Noise can be broken into two components, broadband noise andclose-in phase noise. Broadband noise can be improved by the LC filter added to improve distortionperformance; however, the close-in phase noise typically cannot be improved by additional filtering.Therefore, when selecting an analog signal source it is extremely important to review the manufacturer'sphase noise plots, and great care should be taken to choose a signal generator with the best phase-noiseperformance.
Equally important in the high-performance ADC evaluation setup is the selection of the clocking source.Most modern ADCs, the ADS64XX included, accept either a sinusoidal or a square-wave clock input. Thekey metric in selecting a clocking source is selecting a source with the lowest jitter. This becomesincreasingly important as the ADC's input frequency (Fin) increases, because the ADC SNR evaluationsetups can become jitter-limited (Tj) as shown by the following equation.
SNR (dBc) = 20 log (2 π×Fin ×Tj(rms))
In theory, a square-wave source with femtosecond jitter would be ideal for an ADC evaluation setup.However, in practical terms, most commercially available square-wave generators offer jitter measured inpicoseconds, which is too great for high-resolution ADC evaluation setups. Therefore, most evaluationsetups rely on the ADC's internal clock buffer to convert a sinusoidal input signal into a ultralow-jittersquare wave. When selecting a sinusoidal clocking source, it has been shown that phase noise has adirect impact on jitter performance. Consequently, great scrutiny should be applied to the phase-noiseperformance of the clocking signal generator. TI has found that high-Q monolithic crystal filters canimprove the phase noise of the signal generator, and they become essential elements of the evaluationsetup when high ADC input frequencies are being evaluated.
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