Texas Instruments LMG3410EVM-031 User manual

1
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
User's Guide
SNOU168–June 2019
LMG3410R150-031 EVM User Guide
The LMG3410EVM-031 features two LMG3410R150 600V GaN power transistors with integrated drivers
that are configured in a half bridge with all the required bias circuit and logic/power level shifting. Essential
power stage and gate driving high frequency current loops are fully enclosed on the board to minimize
parasitic inductances, reducing voltage overshoots and improving performance. The LMG3410EVM-031 is
configured to have a socket style external connection for easy interface with external power stages to run
the LMG3410R150 in various applications.
Contents
1 LMG3410EVM-031 User's Guide General TI High Voltage Evaluation User Safety Guidelines.................. 3
2 Description.................................................................................................................... 5
3 Schematic..................................................................................................................... 9
4 Test Setup................................................................................................................... 12
5 Test Procedure ............................................................................................................. 15
6 Typical Characteristics..................................................................................................... 16
7 EVM Assembly Drawing and PCB Layout .............................................................................. 18
8 Bill of Materials ............................................................................................................. 21
List of Figures
1 Simplified LMG3410EVM-031 Schematic ................................................................................ 5
2 Top Side View of LMG3410EVM-031..................................................................................... 6
3 Back Side View of LMG3410EVM-031 ................................................................................... 6
4 Top Side View of LMG3410EVM-031 in Isolated Power Supply Configuration ..................................... 7
5 Back Side View of LMG3410EVM-031 in Isolated Power Supply Configuration.................................... 7
6 LMG3410EVM-031 Schematic............................................................................................. 9
7 Recommended Footprint for LMG3410EVM-031 ...................................................................... 10
8 LMG34XX-BB-EVM Schematic .......................................................................................... 11
9 LMG3410EVM-031 Connected with LMG34XX-BB-EVM ............................................................ 12
10 Recommended Connection Points....................................................................................... 13
11 Recommended Probe Connection for Logic Signals.................................................................. 16
12 Recommended Probe Connection for High Voltage Switch Node................................................... 16
13 Recommended Configuration for Heatsink and Fan................................................................... 16
14 Switching Waveforms with 400V Input, 100kHz, 30% Duty Cycle, 4A Output..................................... 16
15 Low to High Transition Waveform with 400V Input, 100kHz, 30% Duty Cycle, 4A Output....................... 16
16 High to Low Transition Waveform with 400V Input, 100kHz, 30% Duty Cycle, 4A Output....................... 16
17 LMG3410EVM-031 Top Layer and Components ...................................................................... 18
18 LMG3410EVM-031 Inner Copper Layer 1 .............................................................................. 18
19 LMG3410EVM-031 Inner Copper Layer 2 .............................................................................. 19
20 LMG3410EVM-031 Bottom Layer and Components .................................................................. 19
21 LMG34XX-BB-EVM Top Layer and Components...................................................................... 20
22 LMG34XX-BB-EVM Bottom Layer and Components.................................................................. 20

www.ti.com
2SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
List of Tables
1 Logic Pin Function Description............................................................................................. 5
2 Power Pin Function Description ........................................................................................... 5
3 Test Point Functional Description........................................................................................ 14
4 List of Terminals............................................................................................................ 14
5 LMG3410EVM-031 List of Materials..................................................................................... 21
6 LMG34XX-BB-EVM List of Materials .................................................................................... 22
Trademarks
All trademarks are the property of their respective owners.

WARNING
www.ti.com LMG3410EVM-031 User's Guide General TI High Voltage Evaluation User Safety Guidelines
3
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
1 LMG3410EVM-031 User's Guide
General TI High Voltage Evaluation User Safety Guidelines
Always follow TI’s set-up and application instructions, including use of all interface components within their
recommended electrical rated voltage and power limits. Always use electrical safety precautions to help
ensure your personal safety and the safety of those working around you. Contact TI’s Product Information
Center http://support/ti./com for further information.
Save all warnings and instructions for future reference.
Failure to follow warnings and instructions may result in personal injury, property damage, or
death due to electrical shock and/or burn hazards.
The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed
printed circuit board assembly. It is intended strictly for use in development laboratory environments,
solely for qualified professional users having training, expertise, and knowledge of electrical safety risks in
development and application of high-voltage electrical circuits. Any other use and/or application are strictly
prohibited by Texas Instruments. If you are not suitably qualified, you must immediately stop from further
use of the HV EVM.
•Work Area Safety:
– Maintain a clean and orderly work area .
– Qualified observer(s) must be present anytime circuits are energized.
– Effective barriers and signage must be present in the area where the TI HV EVM and its interface
electronics are energized, indicating operation of accessible high voltages may be present, for the
purpose of protecting inadvertent access.
– All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other
related apparatus used in a development environment exceeding 50 VRMS/75 VDC must be
electrically located within a protected Emergency Power Off (EPO) protected power strip.
– Use a stable and non-conductive work surface.
– Use adequately insulated clamps and wires to attach measurement probes and instruments. No
freehand testing whenever possible.
•Electrical Safety:
As a precautionary measure, it is always a good engineering practice to assume that the entire
EVM may have fully accessible and active high voltages.
– De-energize the TI HV EVM and all its inputs, outputs, and electrical loads before performing any
electrical or other diagnostic measurements. Confirm that TI HV EVM power has been safely de-
energized.
– With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring,
measurement equipment hook-ups and other application needs, while still assuming the EVM circuit
and measuring instruments are electrically live.
– When EVM readiness is complete, energize the EVM as intended.
WARNING: While the EVM is energized, never touch the EVM or its electrical circuits as they
could be at high voltages capable of causing electrical shock hazard.
•Personal Safety:
– Wear personal protective equipment, for example, latex gloves and/or safety glasses with side
shields or protect EVM in an adequate lucent plastic box with interlocks from accidental touch.
•Limitation for Safe Use:
– EVMs are not to be used as all or part of a production unit.

!
LMG3410EVM-031 User's Guide General TI High Voltage Evaluation User Safety Guidelines www.ti.com
4SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Safety and Precautions
The EVM is designed for professionals who have received the appropriate technical training, and is
designed to operate from an AC power supply or a high-voltage DC supply. Please read this user guide
and the safety-related documents that come with the EVM package before operating this EVM.
CAUTION
Do not leave the EVM powered when unattended.
WARNING
Hot surface! Contact may cause burns. Do not touch!
WARNING
High Voltage! Electric shock is possible when connecting board to
live wire. Board must be handled with care by a professional.
For safety, use of isolated test equipment with overvoltage and
overcurrent protection is highly recommended.

12V
VDD
FAULT
Q1
FA_1
12V
VDD
FAULT
Q2
FA_2
VDC
PGND
VSW
LMG3410
LMG3410
www.ti.com Description
5
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
2 Description
The LMG3410EVM-031 operates as a daughter card as part of a larger custom designed system or with
the LMG34XX-BB-EVM breakout motherboard.
2.1 LMG3410EVM-031
The LMG3410EVM-031 configures two LMG3410R150 GaN FETs in a half bridge. All the bias and level
shifting components are included, allowing low side referenced signals to control both FETs. High
frequency bypass capacitors are included on the power stage in an optimized layout to minimize parasitic
inductance and reduce voltage overshoot.
There are 7 logic pins on the FET card.
Table 1. Logic Pin Function Description
PIN DESCRIPTION
AGND Logic and bias power ground return pin. Functionally isolated from PGND.
12V Auxiliary power input for Q2. Used as auxiliary power input for Q1 when the LMG3410EVM-031 is
configured in bootstrap mode.
5V Auxiliary power input for the LMG3410EVM-031. Used to power logic isolators. Used as input bias power
of LMG3410R050 devices when configured in isolated power mode.
FA_2 FAULT signal from bottom LMG3410R150 Q2. Pin is either pulled to AGND or 5V.
FA_1 FAULT signal from top LMG3410R150 Q1 Pin is either pulled to AGND or 5V.
Q2 AGND referenced logic gate signal input for bottom LMG3410R150 Q2. Compatible with both 3.3V and
5V logic.
Q1 AGND referenced logic gate signal input for top LMG3410R150 Q1. Compatible with both 3.3V and 5V
logic.
There are 3 power pins on the FET card.
Table 2. Power Pin Function Description
PIN DESCRIPTION
VSW Switch node of the half bridge
VDC Input DC voltage of the half bridge
PGND Power ground of the half bridge. Connected to AGND.
Figure 1. Simplified LMG3410EVM-031 Schematic

Description www.ti.com
6SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
WARNING
To minimize the risk of electrical shock hazard caused by high-
voltage levels on the evaluation module whenever it is energized,
proper precautions must be taken when working with the EVM.
Refer Section 1 for high voltage evaluation user safety guidelines.
2.1.1 FAULT
The FA_1 and FA_2 are the fault signal for top and bottom LMG3410EVM-031 respectively. They are
active low when an under voltage lockout on an auxiliary voltage rail, over temperature or overcurrent
even occurs on the LMG3410R150. The fault signal FA_1 for the top LMG3410R150 device is level
shifted to AGND and the fault signal FA_2 for the bottom LMG3410R150 device is referenced to AGND.
CAUTION
Please do NOT ignore fault signal when using LMG3410EVM-031. Turn off
both top and bottom devices, if any device is generating fault signal. The device
under fault condition may operate in undesired 3rd-quadrant mode and may be
over heated and damaged due to the high source-drain voltage drop if the other
device is still switching.
2.1.2 Power Pins
While there are some power stage bypass capacitors on the LMG3410EVM-031 from VDC to PGND to
minimize voltage overshoot during switching, more bulk capacitance is required to hold up the DC voltage
during operation. It is highly recommended to minimize, and ideally prevent, any overlap and parasitic
capacitance from VSW to VDC, PGND and any logic pins. The two grounds PGND and AGND are
connected to each other on the LMG3410EVM-031.
2.1.3 Bootstrap Mode
The LMG3410EVM-031 operates in bootstrap mode, where the 12V bias voltage is used to power both
LMG3410R150 devices. The isolated power supply board can be separated from the main board along
the score line to save the space. The isolated power supply board must not be connected to the main
board under the bootstrap mode.
2.1.4 Isolated Power Supply Mode
The LMG3410EVM-031 card can be modified to enable the top LMG3410R150 Q1 to operate in the
isolated power supply mode. This can be achieved by populating a 0 Ωresistor on R1 and two 2-position
sockets with 1.27 mm pitch mating such as M50-3140245 on J4 and J5. The isolated power supply board
needs to be separated from the main board along the score line and placed on the main board though J4
and J5, shown in Figure 4 and Figure 5. Make sure the direction of the isolated power supply following the
illustration in Figure 5. To disconnect from the boostrap mode, D1 and R2 needs to be removed. Do NOT
power up the LMG3410EVM-031 when R1, R2 and D1 are all populated with the isolated power supply
board connected.
2.1.5 Heatsink
The heatsink is installed to help with heat dissipation of the LMG3410R150. Exposed copper pads that are
attached to the die attach pad (DAP) of both the high and low side devices are provided for a low thermal
impedance point to a heatsink. The two copper pads have high voltage potential difference between them
so an electrically isolative thermal interface material (TIM) is required. Please refer to Section 8 for the
recommended TIM and mechanical fixture.

Isolated power
supply board
Main board
www.ti.com Description
7
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Figure 2. Top Side View of LMG3410EVM-031
Figure 3. Back Side View of LMG3410EVM-031
Figure 4. Top Side View of LMG3410EVM-031 in Isolated
Power Supply Configuration Figure 5. Back Side View of LMG3410EVM-031 in Isolated
Power Supply Configuration

Description www.ti.com
8SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
2.2 LMG34XX-BB-EVM
To allow for quick operation the LMG34XX-BB-EVM is available to interface with the LMG3410EVM-031.
This mother board is designed to operate the LMG3410R150 as a synchronous open loop buck converter.
Easy probe locations are provided for measurement of logic and power stage voltages.
2.2.1 Bias Supply
The motherboard requires one 12V bias supply. When the LMG3410EVM-031 is configured in bootstrap
mode the 12V input is used to power the two LMG3410R150 devices. A linear drop off regulator steps the
voltage down to a tightly regulated 5V for logic power of the LMG3410R150. When the LMG3410EVM-031
is configured in isolated power supply mode the 5V is also used for auxiliary power for the top
LMG3410R150 Q1.
2.2.2 Logic PWM Input
The LMG34XX-BB-EVM supports a single PWM, with complimentary signal and corresponding dead time
generated on board. A 0 V to 5 V magnitude input square wave is required. The complementary PWM
generation circuit creates 50 ns of dead time between both transitions of the PWM signals.
2.2.3 Fault Protection
There is an option to disable PWM input to the FET card in the event of a fault signal from the
LMG3410EVM-031. When the FAULT Protect jumper is placed in the EN mode PWM is disabled when
either LMG3410R050 has an active fault. This disable is not latching, so when the fault clears PWM
immediately resumes. If FAULT Protect mode is not desired it can be disabled by placing the jumper in
the DIS position. The FAULT LED will still illuminate when either LMG3410R150 has an active fault,
regardless of the position of FAULT Protect jumper.
2.3 Typical Applications
The LMG3410EVM-031 is designed for use in AC/DC, DC/DC and DC/AC applications.
• Totem-Pole PFC converters
• Phase-Shifted Full Bridge or LLC Converter
• Buck converter such as the LMG34XX-BB-EVM
2.4 Features
The LMG3410EVM-031 has the following features and specifications:
• Two options to bias the LMG3410, from bootstrap diode or using isolated power
• Over temperature, overcurrent, and under voltage lockout protection with FAULT indication that is level
shifted to an AGND referenced signal
• Gate logic input support of either 3.3V or 5V logic
• Maximum recommended operating voltage of 480V and absolute maximum voltage of 600V
The LMG34XX-BB-EVM has the following features and specifications:
• Requires only a single 12V bias supply
• Requires only a single 0V to 5V PWM input to generate gate drive signal
• PWM disable in the event of a fault from the LMG3410EVM-031
• Maximum recommended operating voltage of 480V and absolute maximum voltage of 600V
• Maximum recommended operating inductor current of 5A

ISO7731DBQR
VCC1
1
GND1
2
INA
3
INB
4
OUTC
5
NC
6
EN1
7
GND1
8GND2 9
EN2 10
NC 11
INC 12
OUTB 13
OUTA 14
GND2 15
VCC2 16
U1
AGND
20
R2
TP3
TP2
TP1
5V_H
VM12V_H
VM12V_L
IN_L
5V
AGND
Aux Connector
Power Connector
HVBUS
ISO_RET_H
HVBUS
600V
D1
68pF
C6
ISO_12V_H
AGND
ISONC1
ISONC2
ISONC3
68pF
C7
68pF
C17
5V_H
5V_L
SW_L
FAULT_L
5V_L
ISO_RET_H
5V_H
SW_H
IN_H
49.9
R4 22pF
C3
49.9
R9
22pF
C18
5V-AI
20V
D3
DIODE_SCHOTTKY
20V
D2
DIODE_SCHOTTKY
16V
D4
49.9
R3
0.1uF
C20
ISONC4
4.7uF
C21
4.7uF
C23
4.7uF
C22
4.7uF
C24
ISO_12V_H_AO
ISO_12V_H_B
15k 100V/ns
15k 100v/ns
15k
R6
40.2k 60V/ns
0.1uF
C2
1uF
C1
475uH
1
25
6
4 3
T1
D1 1
D2 3
VCC
2
GND 4
EN
5
CLK
6
U2
SN6505
1
2
34
L3
ISO_RET_H
ISO_RET_H
ISO_RET_L
ISO_RET_L
ISO_RET_H_B
-ISO_RET_H_AO
0.022µF
C8
0.022µF
C9
0.022µF
C10
0.022µF
C11
0
R1
FAULT_H
15k
R8
12V
12V
4.7uF
C15
1uF
C19
1uF
C14
Bot_FET
1
2
J2
IN Pin on daughter board
1
2
J3
OUT Pin on daughter board
1
2
J4
Pin to J1
5V
AGND
1
2
J5
Pin for J3
ISO_RET_H
ISO_12V_H
AGND
12V
Bot_FET
Top_FET
Top_FET
5V
AGND
AGND
10µH
L1
10µH
L2
4.7uF
C4
FAULT_H
FAULT_L
0.047uF
C12
0.047uF
C13
40.2k 60V/ns
0.1uF
C5
0.1uF
C16
1 2
3 4
5 6
7 8
J1
0
R5
0
R7
ISO_RET_H
ISO_RET_H
ISO_RET_L
ISO_RET_L
ISO_RET_L
DRAIN 1
DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
DRAIN 6
DRAIN 7
DRAIN 8
DRAIN 9
DRAIN 10
DRAIN 11
SOURCE 12
SOURCE 13
SOURCE 14
SOURCE 15
SOURCE 16
NC
17
SOURCE 18
SOURCE 19
SOURCE 20
SOURCE 21
SOURCE 22
SOURCE 23
SOURCE 24
LDO5V
25
VNEG
26
VDD
27
BBSW
28
LPM
29
RDRV
30
IN
31
FAULT
32
PAD 33
LMG3410R150RWHT
Q1
DRAIN 1
DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
DRAIN 6
DRAIN 7
DRAIN 8
DRAIN 9
DRAIN 10
DRAIN 11
SOURCE 12
SOURCE 13
SOURCE 14
SOURCE 15
SOURCE 16
NC
17
SOURCE 18
SOURCE 19
SOURCE 20
SOURCE 21
SOURCE 22
SOURCE 23
SOURCE 24
LDO5V
25
VNEG
26
VDD
27
BBSW
28
LPM
29
RDRV
30
IN
31
FAULT
32
PAD 33
LMG3410R150RWHT
Q2
AGND_AI
www.ti.com Schematic
9
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
3 Schematic
Figure 6. LMG3410EVM-031 Schematic

Schematic www.ti.com
10 SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Figure 7. Recommended Footprint for LMG3410EVM-031

AGND
1
2 3 4 5
J3
112404
AGND
1 6
5
2
U1A
SN74LVC2G14DCKR
1µF
C9
AGND
5V
39pF
C13
D2
BAT54WS-7-F
AGND
AGND
HDEAD1
PWM
1µF
C11 5V
3 4
5
2
U3B
SN74LVC2G14DCKR
39pF
C5
D1
BAT54WS-7-F
AGND
AGND
5V
LDEAD1
1µF
C4 5V
AGND
1.20k
R1
1.20k
R5
HVIN
PGND1
Vin
HVOUT
PGND2
Vout
LOW
HIGH
FAULT
1000pF
C14
AGND
PGND
1µF
C6
1
2
7
48
U2A
SN74LVC2G08IDCTRQ1
5
6
3
48
U2B
SN74LVC2G08IDCTRQ1
5V
AGND
5V
5V
5V
12V aux
FAULT Indicator
SW1 PGND3
AGND
0
R9
1
2
J6
282834-2
5µF
C1
5µF
C15
HIGH
LOW
PGND
PGND
PGND PGND
39pF
C7
0
R2
AGND
0
R4
39pF
C12
AGND
39pF
C10
AGND
0
R3 VDC
PGND
SW
AGND
5V
1 6
5
2
U3A
SN74LVC2G14DCKR
0.1µF
630V
C3
0.1µF
630V
C2
0.1µF
630V
C17
0.1µF
630V
C16
1µF
C18
AGND
1µF
C20
LOW_2
HIGH_2
HIGH_2
LOW_2
5
4
1
2
3
6
J4
TSW-106-07-G-S
1µF
C8
VAUX
ACMGND
1
2
3
4
5
6
J2
0448120024
AGND1
AGND4
5V
AGND
3 4
5
2
U1B
SN74LVC2G14DCKR
AGND3
0
R23
0
R21
IN
1OUT 3
GND 2 TAB
4
U4
LM2940IMP-5.0/NOPB 33µF
C19
10µF
C21
12V
12V
12V
Green
1
2
D4
Red
1
2
D3
1.6k
R6
1.6k
R8
30k
R10
30k
R16
30k
R11
30k
R17
30k
R18
30k
R12
30k
R13
30k
R19
30k
R20
30k
R14
1
2
3
J7
TSW-103-07-G-S
5V
Red
1
2
D5
PGND
SH-J1
1
2
J5
282841-2
1
2
J1
282841-2
1
2
3
4
47µH
L3
DRQ73-470-R
TI HV Synchronous Buck Motherboard
150µH
L1
150µH
L2
10.0k
R7
5V
AGND
AGND
AGND
AGND2
Copyright © 2016, Texas Instruments Incorporated
www.ti.com Schematic
11
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Figure 8. LMG34XX-BB-EVM Schematic

Test Setup www.ti.com
12 SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
4 Test Setup
4.1 Test Equipment
DC Voltage Source: Capable of supplying the input of the EVM up to 480 V.
DC Bias Source: Capable of 12 V output at up to 0.7 A.
Function Generator: Capable of 0 V to 5 V square wave output with adjustable duty cycle and frequency in
desired operating range. It is recommended to operate the LMG3410EVM-018 and LMG34XX-BB-EVM
with a switching frequency between 50 kHz to 200 kHz.
Oscilloscope: Capable of at least 200 MHz operation. A 1 GHz or greater oscilloscope and probes with
short ground springs are recommended for accurate measurements.
DC Multimeter(s): Capable of 600 V measurement, suitable for determining operation and efficiency (if
desired).
DC Load: Capable of 600 V operation at up to 5 A in current-mode operation.
Fan: 200 LFM minimum airflow is recommended.
4.2 Recommended Test Setup
The LMG3410EVM-031 connects to the LMG34XX-BB-EVM as Figure 9 shows.
Figure 9. LMG3410EVM-031 Connected with LMG34XX-BB-EVM

F
G
B
ACD
E
H
www.ti.com Test Setup
13
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
The LMG34XX-BB-EVM power and probe connection points are shown in Figure 10.
Figure 10. Recommended Connection Points
PCB Notes:
• A: Probe points for gate drive logic
• B:100 mil header for PWM input, PWM signals to LMG3410EVM-018 and FAULT output
• C: BNC connector for PWM input
• D: 12V bias supply input
• E: FAULT Protection option header
• F: Power stage high voltage input
• G: Probe point for power stage switch node
• H: Power stage high voltage output
WARNING
To minimize the risk of the electrical shock and burn hazard,
precautions must be taken when handling the board due to the
high voltages and elevated temperatures on the EVM.

Test Setup www.ti.com
14 SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
4.3 List of Test Points
Key test points on this EVM have been designed for use with oscilloscope probes with short ground
springs. Using the short ground spring instead of the alligator ground lead will minimize measurement
error and produce a cleaner signal with the fast switching GaN devices used on this EVM. The data
shown in this user guide has been obtained using such a measurement method.
Table 3. Test Point Functional Description
NAME DESCRIPTION
VAUX 12 V bias input connection before filter
ACMGND Ground for 12 V bias input before filter
5V 5 V bias
AGND1 Analog ground for logic
PWM Single input PWM signal
LDEAD1 Low side PWM signal before dead time generation
AGND3 Analog ground for logic
HDEAD1 High side PWM signal before dead time generation
AGND4 Analog ground for logic
LOW Low side PWM signal with dead time
HIGH High side PWM signal with dead time
AGND2 Analog ground for logic
12V 12 V bias after filter
PGND1 Power ground
HVIN DC input voltage
PGND2 Power ground
HVOUT DC output voltage
PGND3 Power ground
SW1 Switch node voltage
4.4 List of Terminals
Table 4. List of Terminals
TERMINAL NAME DESCRIPTION
J1 VIN Input DC voltage input
J5 VOUT Output DC voltage output
J6 12V AUX 12 V bias voltage input
J3 PWM INPUT Single 0 V to 5 V PWM input for gate
J4 LOGIC Header to connect PWM, FAULT logic
J2 HB Card PIN Connector to interface LMG3410EVM-031 board

www.ti.com Test Procedure
15
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
5 Test Procedure
5.1 Setup
The following procedure is recommended to set up the LMG34XX-BB-EVM with the LMG3410EVM-031:
• Connect LMG3431EVM-018 to LMG34XX-BB-EVM.
• Connect oscilloscope or multimeter probes to desired test points as shown in A or G.
• Connect the 12 V bias supply, load to the output, and input supply to the input.
• Connect the function generator to either the BNC connector PWM input at C or 100 mil header
connector input at pin 6 (PWM) and pin 5 (GND) at B.
• Cooling with an external fan is recommended to control the temperature of LMG3410R150 and the
heatsink attached to it. Place the fan next to the EVM as shown in Figure 13.
5.2 Startup and Operating Procedure
The following procedure is recommended to enable the LMG34XX-BB-EVM with the LMG3410EVM-031:
1. Power up the 12 V bias supply. Ensure the top right green “Aux Enable” LED is illuminated.
2. Enable PWM on the function generator.
3. Power up high voltage input supply. Ensure the red “HV Enable” LED is illuminated when the input
supply is above 20 V.
WARNING
Do NOT turn on device at absolute maximum voltage. It is
recommended to start at voltages at or below 480 V, and then
increase the input voltage slowly while monitoring VSW to insure the
peak voltage does not exceed the absolute maximum rating of 600
V.
5.3 Shutdown Procedure
1. Turn off input supply then PWM. Wait until red “HV Enable” LED turns off.
2. Disable 12 V bias supply.
5.4 Additional Operation Notes
• Fault protection on the LMG34XX-BB-EVM is not latching, so if a fault clears and the LMG34XX-BB-
EVM is still operational PWM will resume.

Typical Characteristics www.ti.com
16 SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
6 Typical Characteristics
Figure 11. Recommended Probe Connection for Logic
Signals Figure 12. Recommended Probe Connection for High
Voltage Switch Node
Figure 13. Recommended Configuration for Heatsink and
Fan
Figure 14. Switching Waveforms with 400V Input, 100kHz,
30% Duty Cycle, 4A Output

www.ti.com Typical Characteristics
17
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Figure 15. Low to High Transition Waveform with 400V
Input, 100kHz, 30% Duty Cycle, 4A Output Figure 16. High to Low Transition Waveform with 400V
Input, 100kHz, 30% Duty Cycle, 4A Output

EVM Assembly Drawing and PCB Layout www.ti.com
18 SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
7 EVM Assembly Drawing and PCB Layout
Figure 17. LMG3410EVM-031 Top Layer and Components
Figure 18. LMG3410EVM-031 Inner Copper Layer 1

www.ti.com EVM Assembly Drawing and PCB Layout
19
SNOU168–June 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Figure 19. LMG3410EVM-031 Inner Copper Layer 2
Figure 20. LMG3410EVM-031 Bottom Layer and Components

EVM Assembly Drawing and PCB Layout www.ti.com
20 SNOU168–June 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
LMG3410R150-031 EVM User Guide
Figure 21. LMG34XX-BB-EVM Top Layer and Components
Figure 22. LMG34XX-BB-EVM Bottom Layer and Components