Texas Instruments AM64x User manual

User’s Guide
AM64x/AM243x EVM User's Guide
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 EVM Revisions and Assembly Variants............................................................................................................................. 4
1.2 Inside the Box.................................................................................................................................................................... 4
2 Important Usage Notes...........................................................................................................................................................4
2.1 Power-On Usage Note....................................................................................................................................................... 4
2.2 EMC, EMI, and ESD compliance....................................................................................................................................... 4
3 System Description................................................................................................................................................................ 5
3.1 Key Features......................................................................................................................................................................6
3.2 Functional Block Diagram.................................................................................................................................................. 8
3.3 Power-On/Off Procedures..................................................................................................................................................9
3.3.1 Power-On Procedure...................................................................................................................................................9
3.3.2 Power-Off Procedure.................................................................................................................................................10
3.4 Peripheral and Major Component Description..................................................................................................................11
3.4.1 Clocking..................................................................................................................................................................... 11
3.4.1.1 Ethernet PHY Clock............................................................................................................................................ 11
3.4.1.2 AM64x/AM243x Clock.........................................................................................................................................11
3.4.1.3 PCIe Clock.......................................................................................................................................................... 11
3.4.2 Reset......................................................................................................................................................................... 12
3.4.3 Power........................................................................................................................................................................ 13
3.4.3.1 Power Input.........................................................................................................................................................13
3.4.3.2 Reverse Polarity Protection................................................................................................................................ 13
3.4.3.3 Current Monitoring.............................................................................................................................................. 13
3.4.3.4 Power Supply......................................................................................................................................................14
3.4.3.5 Power Sequencing..............................................................................................................................................16
3.4.3.6 AM64x/AM243x Power....................................................................................................................................... 17
3.4.4 Configuration............................................................................................................................................................. 18
3.4.4.1 Boot Modes.........................................................................................................................................................18
3.4.5 JTAG..........................................................................................................................................................................22
3.4.6 Test Automation.........................................................................................................................................................25
3.4.7 UART Interfaces........................................................................................................................................................ 28
3.4.8 Memory Interfaces.....................................................................................................................................................29
3.4.8.1 DDR4 Interface................................................................................................................................................... 29
3.4.8.2 MMC Interfaces...................................................................................................................................................30
3.4.8.3 OSPI Interface.................................................................................................................................................... 31
3.4.8.4 SPI EEPROM Interface.......................................................................................................................................32
3.4.8.5 Board ID EEPROM Interface.............................................................................................................................. 32
3.4.9 Ethernet Interface...................................................................................................................................................... 33
3.4.9.1 DP83867 PHY Default Configuration..................................................................................................................35
3.4.9.2 DP83869 PHY Default Configuration..................................................................................................................35
3.4.9.3 Ethernet LED...................................................................................................................................................... 41
3.4.10 Display Interface......................................................................................................................................................42
3.4.11 USB 2.0 Interface.....................................................................................................................................................43
3.4.12 PCIe Interface..........................................................................................................................................................43
3.4.13 High Speed Expansion Interface............................................................................................................................. 45
3.4.14 CAN Interface.......................................................................................................................................................... 53
3.4.15 Interrupt................................................................................................................................................................... 54
3.4.16 ADC Interface.......................................................................................................................................................... 54
3.4.17 Safety Connector.....................................................................................................................................................55
3.4.18 SPI Interfaces.......................................................................................................................................................... 55
3.4.19 I2C Interfaces.......................................................................................................................................................... 55
3.4.20 FSI Interface............................................................................................................................................................ 57
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4 Known Issues and Modifications........................................................................................................................................ 58
4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS................................................................................ 58
4.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging.....................................................................................................60
5 References............................................................................................................................................................................ 60
6 Revision History................................................................................................................................................................... 60
List of Figures
Figure 3-1. Top View of the AM64x/AM243x EVM Board............................................................................................................ 5
Figure 3-2. Bottom View of the AM64x/AM243x EVM Board.......................................................................................................6
Figure 3-3. General Processor Board Functional Block Diagram................................................................................................8
Figure 3-4. AM64x/AM243x EVM Clock Tree............................................................................................................................ 11
Figure 3-5. Overall Reset Architecture of the AM64x/AM243x EVM......................................................................................... 12
Figure 3-6. Power Good LEDs...................................................................................................................................................15
Figure 3-7. Power ON and OFF Sequencing.............................................................................................................................16
Figure 3-8. AM64x/AM243x Core Supply and Array Core Supply Options............................................................................... 17
Figure 3-9. AM64x/AM243x EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)........................................19
Figure 3-10. AM64x/AM243xEVM PCB, Boot Mode Selection Switches (SW2, SW3)............................................................. 19
Figure 3-11. JTAG Interface.......................................................................................................................................................23
Figure 3-12. Test Automation Header........................................................................................................................................26
Figure 3-13. AM64x/AM243xUART Interfaces...........................................................................................................................28
Figure 3-14. AM64x/AM243x DDR4 Interface........................................................................................................................... 29
Figure 3-15. Micro SD Interface.................................................................................................................................................30
Figure 3-16. eMMC Interface.....................................................................................................................................................31
Figure 3-17. AM64x/AM243x OSPI Interface............................................................................................................................ 32
Figure 3-18. Ethernet Interface - CPSW Domain...................................................................................................................... 33
Figure 3-19. Ethernet Interface - ICSSG Domain...................................................................................................................... 34
Figure 3-20. AM64x/AM243xEthernet Interfaces - CPSW Ethernet Strap Settings.................................................................. 38
Figure 3-21. AM64x/AM243x Ethernet Interfaces - ICSSG1 Ethernet Strap Settings............................................................... 39
Figure 3-22. AM64x/AM243x Ethernet Interfaces - ICSSG2 Ethernet Strap Settings............................................................... 40
Figure 3-23. AM64x/AM243x EVM Ethernet Interface LED.......................................................................................................41
Figure 3-24. AM64x/AM243x USB 2.0 Host Interface............................................................................................................... 43
Figure 3-25. AM64x/AM243x PCIe Interface............................................................................................................................. 44
Figure 3-26. AM64x/AM243x High Speed Expansion Connector..............................................................................................51
Figure 3-27. AM64x/AM243x High Speed Expansion Connector - Part 1................................................................................. 52
Figure 3-28. AM64x/AM243x High Speed Expansion Connector - Part 2................................................................................. 53
Figure 3-29. AM64x/AM243x CAN Interfaces............................................................................................................................54
Figure 3-30. AM64x/AM243x I2C Interfaces and Address Assignment of Peripherals............................................................. 56
Figure 3-31. AM64x/AM243x FSI Interface............................................................................................................................... 57
Figure 4-1. AM64x/AM243x EVM Modification Label Location..................................................................................................58
Figure 4-2. XDS110 CCS Connection Error Dialog................................................................................................................... 59
Figure 4-3. XDS110 debug reset utility command-line function.................................................................................................59
List of Tables
Table 1-1. AM64x/AM243x EVM PCB design revisions, and asssembly variants....................................................................... 4
Table 3-1. Source Clock Selection for the Clock Buffer............................................................................................................. 11
Table 3-2. VMAIN LED...............................................................................................................................................................13
Table 3-3. INA Devices I2C Slave Address............................................................................................................................... 13
Table 3-4. Power Test Points..................................................................................................................................................... 14
Table 3-5. Power LEDs.............................................................................................................................................................. 15
Table 3-6. SoC Power Supply....................................................................................................................................................18
Table 3-7. BOOTMODE Bits...................................................................................................................................................... 20
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]................................................................................................... 20
Table 3-9. Boot Device Selection BOOTMODE[6:3]..................................................................................................................20
Table 3-10. Primary Boot Media Configuration BOOTMODE[9:7]............................................................................................. 21
Table 3-11. Backup Boot Mode Selection BOOTMODE[12:10]................................................................................................. 21
Table 3-12. Backup Boot Media Configuration BOOTMODE[13].............................................................................................. 21
Table 3-13. Selection of HSE Connector and JTAG TRACE Functionality................................................................................ 22
Table 3-14. TI20 Pin Connector (J25) Pin-Out...........................................................................................................................22
Table 3-15. TI 60-Pin Connector (J33) Pin-Out......................................................................................................................... 24
Table 3-16. List of Signals Routed to Test Automation Header................................................................................................. 25
Table 3-17. Test Automation Header (J38) Pin-out....................................................................................................................27
Table 3-18. Board ID Memory Header Information.................................................................................................................... 32
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Table 3-19. Default Strap Setting of CPSW Ethernet PHY........................................................................................................ 36
Table 3-20. Default Strap Setting of ICSSG Ethernet PHYs......................................................................................................36
Table 3-21. Display Connector (J36) Pin-Out............................................................................................................................ 42
Table 3-22. PCIe Jumper Options to Enable Root Complex and Endpoint Mode..................................................................... 44
Table 3-23. PCIe Connector (J27) Pin-out.................................................................................................................................44
Table 3-24. Selection of PRG0 Signals on Application Connector............................................................................................ 46
Table 3-25. CAN (J31 and J32) Pin-out..................................................................................................................................... 53
Table 3-26. ADC Connector (J3) Pin-out................................................................................................................................... 54
Table 3-27. Safety Connector Pinouts....................................................................................................................................... 55
Table 3-28. I2C Test Header (J5) Pin-out.................................................................................................................................. 55
Table 3-29. I2C Test Header (J4) Pin-out.................................................................................................................................. 56
Table 3-30. FSI (J5) Connector Pin-out..................................................................................................................................... 57
Table 4-1. AM64x/AM243x EVM Known Issues and Modifications........................................................................................... 58
Trademarks
Sitara™ and Code Composer Studio™ are trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited.
All trademarks are the property of their respective owners.
1 Introduction
The TMDS64EVM/TMDS243EVM is a standalone test, development, and evaluation module (EVM) that lets
developers evaluate the AM64x/AM243x functionality and develop prototypes for a variety of applications. The
EVM implements either the Sitara™ AM6442 MPU or the AM2434 MCU. Additional supporting components allow
the user to make use of the various device interfaces including Industrial Ethernet, standard Ethernet, PCIe,
Fast Serial Interface (FSI) and others to easily create prototypes. An on-board display makes use of AM64x/
AM243x serial peripheral interface (SPI) ports to provide the ability for local visual outputs in addition to the
various LED provided. On-board current measurement capabilities are available to monitor power consumption
for power-conscious applications. The supplied USB cable paired with embedded emulation logic allows for
emulation and debugging using standard development tools such as Code Composer Studio™ software from TI.
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1.1 EVM Revisions and Assembly Variants
The various AM64x/AM243x EVM PCB design revisions, and asssembly variants are listed in the table below.
Specific PCB revision is indicated in silkscreen on the PCB. Specific assembly variant is indicated with additional
sticker label.
Table 1-1. AM64x/AM243x EVM PCB design revisions, and asssembly variants
PCB Revison Assembly Variant Revision and Assembly Variant Description
PROC101-004 C N/A First Production Release of the AM64x EVM
PROC101-005 C N/A First Production Release of the AM243x EVM
Note
Throughout this document, the AM6442 and AM2434 devices are interchangable in diagrams and
other tables, other than explicitly defined exception. The AM2434 MCU in the ALV package and the
AM6442 MPU are footprint and pinout compatible and the PCB has been designed to accommodate
both.
Note
For the board formerly known as AM64x/AM243x GP EVM please see AM64x/AM243x EVM User's
Guide (Rev. D)
Note
All AM64x/AM243x EVMs include high-security field-securable (HS-FS) silicon to customize keys and
encryption for security applications.
1.2 Inside the Box
• EVM
• Micro-SD Card
• USB Cable (Type-A to Micro-B) for serial terminal/logging
• Ethernet Cable
• Quick Start Guide
Note
The maximum length of the IO cables shall not exceed 3 meters.
2 Important Usage Notes
2.1 Power-On Usage Note
CAUTION
To avoid high inrush currents and prevent possible damage to the AM64x/AM243x EVM
components, the proper EVM power on and power off procedures are required. For more details,
see Section 3.3.
2.2 EMC, EMI, and ESD compliance
Components installed on the product are sensitive to Electric Static Discharge (ESD). It is recommended this
product be used in an ESD controlled enviorment. This may include a temperature and/or humidty controlled
enviorment to limit the buildup of ESD. It is also recommended to use ESD protection such as wrist straps and
ESD mats when interfacing with the product.
The product is used in the basic electromagnetic enviorment as in laboratory conditions, and the applied
standard is as per EN IEC 61326-1:2021
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3 System Description
The following sections describe the AM64x/AM243x EVM design. Top-down and bottom-up views of the PCB are
provided in Figure 3-1 and Figure 3-2 for reference to major IC and connector component locations.
Figure 3-1. Top View of the AM64x/AM243x EVM Board
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Figure 3-2. Bottom View of the AM64x/AM243x EVM Board
3.1 Key Features
AM64x System-on-Chip (SoC):
• AM64x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-
A53 cores, up to four Cortex-R5F MCUs, and a single Cortex-M4F MCU
AM243x Microcontroller (MCU):
• AM243x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two Cortex-R5F
MCU, and a single Cortex-M4F MCU
Memory
• 2GB DDR4 supporting data rate up to 1600MT/s
• 16GB eMMC Flash which can support HS400 speed of operation
• Micro Secure Digital (SD) Card with UHS-1 support
• 1 Kbit Serial Peripheral Interface (SPI) EEPROM
• 512 Mbit OSPI EEPROM
• 1 Mbit Inter-Integrated Circuit (I2C) Boot EEPROM
I/O Interface:
• One CPSW Gigabit Ethernet port and two Industrial Ethernet ports based on the Gigabit Industrial
Communication Subsystem (PRU-ICSS-Gb) paired with Texas Instruments Gigabit Ethernet PHY
• One USB2.0 interface with Micro AB connector
Expansion Bus:
• 10051922-1410ELF - 14-Pin FPC connector to interface with the OSD9616P0992-10 display
• High Speed Expansion (HSE) connector to connect application cards
• 2x5 header - 67997-410HLF FSI connector to connect with the C2000 EVM
• x4 PCIe connector to support 1 lane PCIe Card
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Debug:
• XDS110 On-Board Emulator
• Supports 20-pin JTAG connection from external emulator
• Automatic selection between on-board and external emulator (higher priority)
• Quad port Universal Asynchronous Receiver/Transmitter (UART) to USB circuit over microB USB connector
• Two I2C ports SoC_I2C0 and SoC_I2C1 connected to test headers for peripheral testing of the AM64x device
• 4x Push Buttons:
– 1x SoC Warm RESET
– 1x User GPIO
– 1x MCU Warm RESET
– 1x MCU/SoC PORz RESET
Power Supply:
Note
Please ensure that you are using the appropriately sized DC barrel jack for your particular EVM
revision, as these have changed from the board known as TMDS64GPEVM. A GP EVM Power
Supply can be adapted to this revision by using an adapter of part number DC PLUG-P1J-P1M
• DC Input: 12V
• Center positive 5.5mm x 2.5mm x 9.5mm Barrel Jack.
– Recommended mating connector - PJ-080BH.
– Recommended Power Supply - GlobTek Inc. RR9LE5000LCPCIMR6B ( IEC 320-C6 adapter cords sold
separately).
• Status Output: LEDs to indicate power status
• INA devices for current monitoring
Compliance:
• RoHS Compliant
• REACH Compliant
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3.2 Functional Block Diagram
Figure 3-3 shows the functional block diagram of the AM64x/AM243x EVM.
Figure 3-3. General Processor Board Functional Block Diagram
Note
Diagram is compatible with both the AM6442 MPU and the AM2434 MCU version of the system.
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3.3 Power-On/Off Procedures
Power to the EVM is provided through an external AC/DC converter providing 12 Volt, 5A (max) DC voltage to
the J6 power jack.
See the "Power Supply" list in Key Features for TI's recommendation on an appropriate AC/DC power converter
for your EVM revision.
CAUTION
To avoid high inrush currents, and prevent possible damage to the AM64x/AM243x EVM
components, the following EVM power on and power off procedures should be utilized.
3.3.1 Power-On Procedure
1. Place EVM power (SW1) switch in OFF position as shown in the figure below.
2. Place EVM boot switch selectors (SW2, SW3) into selected boot mode. For more details, see Boot Modes.
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3. Attach 12 V AC/DC regulator plug to EVM power jack (J6), but do not power converter from AC power.
4. Apply AC power to AC/DC converter. 12 V power LED (LD6 and LD12) should illuminate.
5. Place EVM power (SW1) switch in ON position as shown below.
6. Visually inspect LED against reference photo above. The following LED should be illuminated:
• LD1, LD2, LD3, LD4, LD6, LD7, LD8, LD9, LD10, LD15, LD24, LD25
Note
If using an AM243x EVM, LD2 will not be illuminated.
3.3.2 Power-Off Procedure
1. Switch EVM power switch (SW1) to OFF position.
2. Disconnect AC power from AC/DC converter.
3. Remove DC power plug from EVM power jack (J6).
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3.4 Peripheral and Major Component Description
The following sections provide an overview of the different interfaces and circuits on the AM64x/AM243x EVM.
3.4.1 Clocking
3.4.1.1 Ethernet PHY Clock
A clock generator of part number CDCLVC1310 is used to drive 25 MHz clock to the Ethernet PHYs.
CDCLVC1310 is a 1:10 LVCMOS clock buffer, which takes 25 MHz crystal/LVCMOS reference input and
provides ten 25 MHz LVCMOS clock outputs. The source for the clock buffer is either the CLKOUT0 pin from
the SoC or a 25 MHz oscillator (ASFLMB-25.000MHZ-LY-T), the selection is made using a set of resistors. This
selection can be made through the select lines of the clock buffer.
1. IN_SEL0, IN_SEL1 = [00] for selecting CLKOUT0.
2. IN_SEL0, IN_SEL1 = [01] for selecting oscillator input. This is the default condition.
The resistor termination for single ended Crystal input is provided as per device-specific data sheet.
Table 3-1. Source Clock Selection for the Clock Buffer
IN_SEL1 IN_SEL0 Clock Chosen Mount Unmount
0 0 EXT_REFCLK from SoC R40, R45 R248, R253
1 0 Oscillator input R253, R40 R45, R248
Figure 3-4. AM64x/AM243x EVM Clock Tree
Note
Resistors that are marked with red color box are DNI.
3.4.1.2 AM64x/AM243x Clock
Crystal of 25 MHz (ABM10W-25.0000MHZ-8-K1Z-T3) is provided on EVM as reference clock for the AM64x/
AM243x device. An optional output from the buffer driving the AM64x/AM243x is provided. Selection of clock for
SoC is done using resistors. By default, an output from clock buffer SoC_CLKIN is provided to SoC.
3.4.1.3 PCIe Clock
The PCIe reference clock to the SoC will be provided by the PCIe slot connector when processor is configured
as downstream port and PCIe reference clock from the SoC (SERDES0_REFCLK0) will be provided to the PCIe
slot connector during root complex mode of operation.
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3.4.2 Reset
The AM64x/AM243x device has the following reset signals:
• RESET_REQz is the warm reset input for MAIN domain.
• RESETSTATz is the warm reset status output for MAIN domain.
• PORz_OUT is the power ON reset status output from MAIN and MCU domain.
• MCU_PORz is the power ON/Cold Reset input for MCU and MAIN domain.
• MCU_RESETz is the Warm Reset input for MCU domain.
• MCU_RESETSTATz is the Warm Reset status output for MCU domain.
The two supervisor outputs and reset from JTAG are input to an AND gate to generate the PORz signal. This
PORz, the CONN_MCU_PORz from safety connector, and PCIe_MCU_PORz from PCIe connector are input to
another AND gate to generate the MCU_PORz signal.
Three push button switches are available to provide reset for MCU_PORz, MCU_RESETz and RESET_REQz.
Warm reset can also be applied through Test automation header or manual reset switches SW4(SoC) and
SW6(MCU).
MCU_PORz input can be applied though switch SW7.
The CONN_MCU_RESETz and CONN_MCU_PORz from the safety connector are routed to MCU_RESETz and
MCU_PORz respectively thereby providing option for safety connector to create a warm reset and a cold reset
as shown in the Figure 3-5.
Most peripheral resets are “ANDED” with the RESETSTATz output from the SoC along with a GPIO control as
shown in Figure 3-5. This ensures that the peripheral reset is asserted until the SoC is out of reset and allows
the AM64x to manually assert reset to the peripheral.
Figure 3-5. Overall Reset Architecture of the AM64x/AM243x EVM
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3.4.3 Power
3.4.3.1 Power Input
The following sections describe the power distribution network topology that supplies the EVM board, supporting
components and reference voltages.
The AM64x/AM243x EVM board includes a power solution based on discrete power supply components. The
initial stage of the power supply will be 12 V from a barrel jack connector with part reference J6. J6 supports 8A
current rating and necessary diodes for reverse polarity protection and voltage surge protection. The 12 V input
(VMAIN) of the EVM that is used to generate all necessary voltages required by the EVM.
A ON/OFF switch with part reference SW1 is provided to turn ON/OFF the EVM by connecting this switch to
Enable pin of LM5140, thereby, allowing the switch to turn on or off the board based on the switch position. The
board is in off condition when switch is grounded position 1-2 and in on condition when the switch is in position
2-3. Additionally GPIO from the test automation header is also connected to the switch to control ON/OFF of the
EVM via the test automation board. A fault indication LED LD5 will be in ON status in case of reverse polarity.
LD6 will be in ON status to indicate VMAIN power good.
Note
The Switch SW1 does not turn of VMAIN. It only disables the VCC_5V0 output of LM5140 from which
all other power supplies are derived.
3.4.3.2 Reverse Polarity Protection
A Schottky barrier rectifier with reference D3 is kept for reverse polarity protection, which has average forward
current: IF(AV) ≤ 15 A, reverse voltage: VR ≤ 45 V. LD6 status will give power polarity.
Table 3-2. VMAIN LED
LED ON Status OFF Status
LD5 Power polarity reversed Power polarity good
LD6 Board Power on Board Power off
3.4.3.3 Current Monitoring
INA226 power monitor devices are used to monitor current and voltage of various power rails of AM64x/AM243x
processor. The INA226 interfaces to the AM64x/AM243x through I2C interface. Four terminal, high precision
shunt resistors are provided to measure load current.
Table 3-3. INA Devices I2C Slave Address
Power Source Supply Net
Slave Address
(IN HEX)
Value of the Shunt Connected
to the Supply Rail
VCC_CORE VDD_CORE 40 2mΩ ±1%
VDD_0V85 VDDAR_CORE 41 10mΩ ± 0.5%
VCC_3V3_SYS SoC_DVDD3V3 4C 10mΩ ± 0.5%
VCC1V8 SoC_DVDD1V8 4B 10mΩ ± 0.5%
VDDA1V8 VDDA_1V8 4E 10mΩ ± 0.5%
VCC1V2_DDR VDD_DDR4 46 10mΩ ± 0.5%
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3.4.3.4 Power Supply
The EVM utilizes an array of DC-DC converters to supply the various memories, clocks, SoC and other
components on the card with the necessary voltage and the power required. Table 3-5 gives power-good LEDs
provided on EVM board to give users positive confirmation of the status of output of each supply.
Test points for each power outputs are provided on the EVM Board and are mentioned in the below Table 3-4.
Table 3-4. Power Test Points
Sl.No Power Supply Test Point Voltage
Top Side
1 VMAIN TP81 12 V
2 VCC_5V0 TP18 5 V
3 VCC3V3_PREREG TP12 3.3 V
4 VCC_3V3_SYS TP44 3.3 V
5 VDD_2V5 TP6 2.5 V
6 VDD_1V1 TP28 1.1 V
7 VDDA1V8 TP29 1.8 V
8 VDD_CORE TP14 0.75 V (1)
9 VCC_CORE TP23 0.75 V
10 VDD_0V85 TP8 0.85 V
11 VDDAR_CORE TP10 0.85 V
12 VCC1V2_DDR TP4 1.2 V
13 VDD_2V8 TP99 2.8 V
14 VCC3V3_TA TP96 3.3 V
15 VDD_1V0 TP56 1 V
16 VPP_DDR_2V5 TP47 2.5 V
17 VDDR_VTT TP48 0.6 V
18 VCC1V8 TP51 1.8 V
19 VPP_1V8 TP52 1.8 V
(1) AM243x EVM should be 0.85 V.
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Table 3-5. Power LEDs
Sl.No Power Supply LED REF
Before SW1 TURN ON
1 VMAIN LD6
2 VCC3V3_TA LD24
After SW1 TURN ON
3 VCC_5V0 LD15
4 VCC3V3_PREREG LD4
5 VCC_3V3_SYS LD9
6 VDD_2V5 LD1
7 VDD_1V1 LD10
8 VDDA1V8 LD8
9 VDD_CORE LD2
10 VCC_CORE LD7
11 VDD_2V8 LD25
12 VCC1V2_DDR LD3
Figure 3-6. Power Good LEDs
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3.4.3.5 Power Sequencing
Figure 3-7 shows the Power Up and Power Down sequence of all the Power supplies present on the EVM
Board.
Figure 3-7. Power ON and OFF Sequencing
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3.4.3.6 AM64x/AM243x Power
The Core voltage of the AM64x/AM243x can be powered by 0.75 V or 0.8 V or 0.85 V based on
the power optimization requirement. It is recommended to use a single voltage source when the SoC
Core voltage (VDD_CORE) and SoC Array Core Voltage (VDDR_CORE) and other array core voltages
(VDDA_0P85_SERDES0_C, VDDA_0P85_SERDES0, VDDA_0P85_USB0, VDD_DLL_MMC0, VDD_MMC0) is
0.85 V. In cases where the SoC Core voltage is required to be 0.75 V or 0.8 V and SoC Array Core Voltage and
other Array Core voltages is required to be 0.85 V then there needs to be separate voltage supply for the SoC
Core voltage and an separate supply for the SoC Array Core voltages.
This EVM has a provision for providing single voltage supply or different voltage supply to the SoC Core
and SoC Array Core and other Array Core Voltages and based requirement. This can be configured by the
placement of resistors as mentioned in Figure 3-8.
Figure 3-8. AM64x/AM243x Core Supply and Array Core Supply Options
Note
• PROC101x-001 BOM variant, implements the AM6442 and requires 0.75 V supplied to the
VDD_CORE and 0.85 V supplied to VDDR_CORE. In this variant R2 and R4 are installed by
default and VDD_CORE supply (U25) is setup for 0.75 V operation.
• PROC101x-002 BOM variant, implements the AM2434 and requires 0.85 V supplied to
VDD_CORE and VDDR_CORE. In this variant R1 and R3 are installed by default and VDD_CORE
supply (U25) is setup for 0.85 V operation.
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The SoC has different IO groups. Each IO group is powered by specific power supplies as shown in Table 3-6.
Table 3-6. SoC Power Supply
SI.No. Power Supply SoC Supply Rails IO Power Group Power
1 VDDA_CORE VDDA_0P85_SERDES
0
SERDES0 0.85
VDDA_0P85_SERDES
0_C
0.85
VDDA_0P85_USB0 USB0 0.85
VDD_MMC0 MMC0 0.85
2 SoC_DVDD3V3 VDDS_MCU MCU 3.3
VDDA_3P3_USB0 USB0 3.3
VDDSHV0 General 3.3
VDDSHV1 PRG0 3.3
VDDSHV2 PRG1 3.3
VDDSHV3 GPMC 3.3
3 VDDA_1V8_MCU VDDA_MCU MCU 1.8
4 VDDA_MCU_ADC VDDA_ADC ADC0 1.8
5 VDDA_1V8_SERDES VDDA_1P8_SERDES0 SERDES0 1.8
6 VDDA_1V8_USB0 VDDA_1P8_USB0 USB0 1.8
7 VDDA_1V8 VDDS_OSC OSC0 1.8
VDDA_TEMP_0/1 1.8
VDDA_PLL_0/1/2 1.8
8 VDD_DDR4 VDDS_DDR DDR0 1.2
VDDS_DDR_C 1.2
9 SOC_DVDD1V8 VDDSHV4 FLASH 1.8
VDDS_MMC0 MMC0 1.8
10 VDDSHV_SD_IO VDDSHV5 MMC1 1.8
3.4.4 Configuration
3.4.4.1 Boot Modes
The boot mode for the EVM is defined by either a bank of switches SW2 and SW3 or by the I2C buffer (U96)
connected to the test automation connector (J38). All the boot mode pins have a weak pull-down resistor and a
switch capable of connecting to a strong pull up resistor. Switch set to “ON” corresponds to logic “HIGH” while
“OFF” corresponds to logic “LOW”.
For a full description of all AM64x SoC supported bootmodes, see the AM64x Sitara™ Processors Data Manual
and AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products Technical Reference
Manual.
The following boot modes are supported by EVM (and subject to change):
1. OSPI
2. MMC1 - SD Card
3. MMC0 - eMMC installed
4. USB - boot using host mode with bulk storage. USB 2.0 mass storage using FAT16/32 (thumb drive)
5. USB - device boot DFU
6. UART
7. No-Boot
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Figure 3-9. AM64x/AM243x EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)
Figure 3-10. AM64x/AM243xEVM PCB, Boot Mode Selection Switches (SW2, SW3)
The BOOTMODE pins provide means to select the boot mode before the device is powered up. They are divided
into the following categories:
Note
The following bit pattern is reversed in the table from the switch order.
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Table 3-7. BOOTMODE Bits
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RSVD RSVD Backup
Boot
Mode
Config
Backup Boot Mode Primary Boot Mode
Config
Primary Boot Mode PLL Config
BOOTMODE[2:0] - Denote system clock frequency for PLL configuration. By default, these bits are set for 25
MHz.
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]
SW2.3 SW2.2 SW2.1 PLL REF CLK (MHz)
off off off 19.2
off off on 20
off on off 24
off on on 25
on off off 26
on off on 27
on on off RSVD
on on on RSVD
BOOTMODE[6:3] - This provides primary boot mode configuration to select the requested boot mode after POR,
that is, the peripheral/memory to boot from.
Table 3-9. Boot Device Selection BOOTMODE[6:3]
SW2.7 SW2.6 SW2.5 SW2.4
Primary Boot Device
Selected
off off off off RSVD
off off off on OSPI
off off on off QSPI
off off on on SPI
off on off off RSVD
off on off on RSVD
off on on off I2C
off on on on UART
on off off off MMC/SD Card
on off off on eMMC
on off on off USB
on off on on GPMC NAND
on on off off GPMC NOR
on on off on PCIe
on on on off xSPI
on on on on No-boot / Dev-boot
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