Texas Instruments PGA855 User manual

User’s Guide
PGA855 Evaluation Module
ABSTRACT
This user's guide contains information and support documentation for the PGA855 evaluation module (EVM).
Included are the circuit description, jumper settings, required connections, printed circuit board (PCB) layout,
schematic, and bill of materials of the PGA855EVM. Throughout this document, the terms evaluation board,
evaluation module, and EVM are synonymous with the PGA855EVM.
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Table of Contents
1 Overview..................................................................................................................................................................................3
1.1 Related Documentation......................................................................................................................................................3
1.2 Electrostatic Discharge Caution......................................................................................................................................... 3
1.3 Hot Surface Warning..........................................................................................................................................................3
2 EVM Circuit Description.........................................................................................................................................................4
3 Jumper Settings......................................................................................................................................................................5
4 Power-Supply Connections................................................................................................................................................... 6
5 Analog Input and Output Connections.................................................................................................................................8
6 Digital Input Pins and Gain Control...................................................................................................................................... 9
7 Modifications.........................................................................................................................................................................10
8 Schematic, PCB Layout, and Bill of Materials................................................................................................................... 10
8.1 Schematic........................................................................................................................................................................ 10
8.2 PCB Layout...................................................................................................................................................................... 10
8.3 Bill of Materials.................................................................................................................................................................16
List of Figures
Figure 2-1. PGA855EVM Simplified Schematic...........................................................................................................................4
Figure 3-1. PGA855EVM Default Jumper Settings......................................................................................................................5
Figure 4-1. PGA855EVM Voltage Supply Connections...............................................................................................................7
Figure 5-1. PGA855EVM Analog Input and Output Connections................................................................................................ 8
Figure 6-1. PGA855EVM Gain Control........................................................................................................................................9
Figure 8-1. PGA855EVM Schematic......................................................................................................................................... 10
Figure 8-2. Top Overlay PCB Layout......................................................................................................................................... 11
Figure 8-3. Top Layer PCB Layout............................................................................................................................................ 12
Figure 8-4. Ground Layer PCB Layout...................................................................................................................................... 13
Figure 8-5. Power Layer PCB Layout........................................................................................................................................ 14
Figure 8-6. Bottom Layer PCB Layout.......................................................................................................................................15
List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 3
Table 3-1. Default Jumper Configuration..................................................................................................................................... 5
Table 4-1. PGA855EVM Supply-Range Specifications................................................................................................................6
Table 5-1. PGA855EVM Analog Input and Output Connections..................................................................................................8
Table 6-1. PGA855EVM Gain Control......................................................................................................................................... 9
Table 8-1. PGA855EVM Bill of Materials................................................................................................................................... 16
Trademarks
All trademarks are the property of their respective owners.
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1 Overview
The PGA855 is a precision, high-bandwidth programmable gain instrumentation amplifier with fully differential
outputs optimized to drive high-performance analog-to-digital converters (ADCs) and fully differential inputs. The
PGA855 is equipped with eight binary gain settings, from an attenuating gain of 0.125 V/V to a maximum of 16
V/V, using three digital gain-selection pins. The output common-mode voltage can be independently set using
the VOCM pin. The device features super-beta input transistors from Texas Instruments, which provide ultra-low
input offset voltage, offset drift, input bias current, input voltage noise, and current noise. For a full list of the
electrical characteristics for the PGA855, see the PGA855 Low-Noise, High-Bandwidth, Fully Differential Output
Programmable-Gain Instrumentation Amplifier data sheet.
1.1 Related Documentation
The following document provides information regarding Texas Instruments integrated circuits used in the
assembly of the PGA855EVM. This user's guide is available from the TI website under literature number
SBOU296. Any letter appended to the literature number corresponds to the document revision that is current at
the time of the writing of this document. Newer revisions are available from the TI website at https://www.ti.com/,
or call the Texas Instruments Literature Response Center at [phone] or the Product Information Center at
[phone]. When ordering, identify the document by both title and literature number.
Table 1-1. Related Documentation
Device Literature Number
PGA855 SBOSAE0
1.2 Electrostatic Discharge Caution
CAUTION
Many of the components on the PGA855EVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and
handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
1.3 Hot Surface Warning
WARNING
Device can become hot under high-current conditions. Take care when handling the EVM.
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2 EVM Circuit Description
This EVM provides access to the features and measures the performance of the PGA855 device. The PGA855
is equipped with eight binary gain settings, from an attenuating gain of 0.125 V/V to a maximum of 16 V/V, using
three digital gain selection pins. By default, the PGA855EVM programmable gain amplifier is configured to a gain
of 0.125 V/V. The evaluation board provides shunt jumpers J10, J11, and J12 to set the PGA855 gain.
The device uses two sets of voltage supplies: input stage and output stage. The output-stage power supplies
are decoupled from the input stage to limit the PGA855 output-swing voltage level protecting the ADC or
downstream device against overdrive damage. The input-stage supplies, VS+ and VS–, are accessible using
connector J13. The output-stage supplies, LVDD+ and LVSS–, are accessible using connector J14. Selectable
jumpers J9 and J16 set the output-stage supply voltage level equal to the input-stage supplies (default), or to
external voltages using connector J14.
The PGA855 incorporates features that simplify interfacing to a fully differential ADC. The output common-mode
voltage can be independently set by using the VOCM pin. The VOCM connector sets the output common-mode
voltage. If the VOCM connector is not driven, the output common-mode voltage defaults to the PGA855 output
stage mid-supply value. The PGA855EVM allows access to the FDA_IN– and FDA_IN+ pins with optional
capacitors C4 and C14. These capacitors are in parallel with the PGA855 output-stage internal-feedback
resistors to implement noise filtering. Figure 2-1 displays a simplified block diagram of the PGA855EVM. For
a full schematic of the PGA855EVM, see Figure 8-1.
D2
36 V
SMA
Connector
J3
J6
SMA
Connector
VCC
VEE
IN+
IN–
R4 100

R9 100

C10
C6
C13
100 pF
10pF
10pF
R8 100

C8
100 pF
J4.4
J4.1
J4.3
J4.2
Output
Connector
OUT+
OUT–
DNP
DNPC4
C14
VCC
C2
100 nF
VEE
LVDD+_ext
1
2
3
LVSS-_ext
J14.1
J14.2
J14.4
J14.3
VCC
LVDD+
J9
1
2
3
VEE
LVSS–
J16
C15
100 nF
C19
100 nF
VCC
VEE
VCC
VEE
PGA855 Output
Stage Supplies
J1.1
J1.2
VCC
VEE
R2
VOCM
Connector
D1
D3
1
2
3
J5
1
2
3
J7
C1
100 nF
R5 100

J13.1
J13.2
J13.3 VCC
VEE
100

R1
10 k

R3
10 k

FDA_IN+
+
OUT+
IN+
IN–
R3
R1
R2R4
FDA_IN–
+
+
PGA855
+
Gain Network
A0 A1 A2
A0
A1A2
Overvoltage
Protection
Overvoltage
Protection
VS+
DGND
OUT–
–
–
–
–
D5
36 V
VEE
D4
36 V
VCC
LVDD+ C3
100 nF
J2
SMA
Connector
OUT+
J8
SMA
Connector
OUT–
C16
100 nF
LVSS–
J10 J11 J12
1
2
1
2
1
2
A2 A1 A0
A0
A1
A2
100 k

100 k

100 k

VCC
J15.1
J15.2
J15.3
J15.4
PGA855 Gain
Control
PGA855 Input
Stage Supplies
R16
R17
R18
GND
GND
VOCM LVDD
VS– LVSS
C23
100 nF
C17
10 µF
C20
10 µF
C18
100 nF
C21
100 nF
Figure 2-1. PGA855EVM Simplified Schematic
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3 Jumper Settings
Figure 3-1 details the default jumper settings of the PGA855EVM. Table 3-1 explains the configuration for these
jumpers.
Figure 3-1. PGA855EVM Default Jumper Settings
Table 3-1. Default Jumper Configuration
Jumper Function Default Position Description
J5 Positive (noninverting) input, IN+ Shunt 2-3 Shunt 2-3: Input signal to SMA connector J3
Shunt 1-2 connects IN+ to GND
J7 Negative (inverting) input, IN– Shunt 2-3 Shunt 2-3: Input signal to SMA connector J6
Shunt 1-2 connects IN– to GND
J9 LVDD+ connection Shunt 1-2 Shunt 1-2: Sets output stage supply LVDD+ to +VCC supply
Shunt 2-3 connects LVDD+ to external connector J14 pin 1
J16 LVSS– connection Shunt 1-2 Shunt 1-2: Sets output stage supply LVDD- to –VEE supply
Shunt 2-3 connects LVDD– to external connector J14 pin 3
J10 PGA gain CTRL A2 Open Open: Sets A2 to GND or 0
Shunt 1-2: Sets A2 to VCC or 1
J11 PGA gain CTRL A1 Open Open: Sets A1 to GND or 0
Shunt 1-2: Sets A1 to VCC or 1
J12 PGA gain CTRL A0 Open Open: Sets A0 to GND or 0
Shunt 1-2: Sets A0 to VCC or 1
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4 Power-Supply Connections
The PGA855EVM uses two sets of voltage supplies: input stage and output stage. The device operates using
input-stage power supplies from ±4 V (8 V) to ±18 V (36 V) and output-stage power supplies from ±2.25 V
(4.5 V) to ±18 V (36 V). The output-stage supply voltage must not exceed the input-stage supply voltage.
The input-stage power-supply connections for the PGA855EVM are provided through connector J13 at the top
of the EVM. The input-stage positive power-supply connection is labeled +VCC, the negative power-supply
connection is labeled –VEE, and the ground connection is labeled GND. To connect power to the PGA855EVM,
insert wires into each terminal of J13 and then tighten the screws to make the connection. Table 4-1 summarizes
the pin definition for supply connector J1 and the allowed voltage range for each supply connection.
Table 4-1. PGA855EVM Supply-Range Specifications
Connector Pin
Number Supply Connection Voltage Range
J13.3 Input-stage positive supply
(+VCC)
Single supply, VS = +VCC: 8 V to 36 V
Dual supply, VS = (+VCC) – (–VEE): 4 V to 18 V
J13.2 Ground 0 V
J13.1 Negative supply (–VEE) Single supply, VS = +VCC: 0 V (GND)
Dual supply, VS = (+VCC) – (–VEE): –4 V to –18 V
J14.1 LVDD+_ext
Single supply, LVDD+_ext: 4.5 V to 36 V
Dual supply, output stage supply (LVSS+) – (LVSS–):
2.25 V to 18 V
J14.2 Ground 0 V
J14.3 LVSS–_ext
Single supply, LVSS–_ext: 0 V (GND)
Dual supply, output stage supply (LVSS+) – (LVSS–):
–2.25 V to –18 V
J14.4 Ground 0 V
By default, the output-stage supply-voltage levels (+LVDD and –LVSS) are set to the PGA855 positive (+VCC)
and negative (–VEE) supplies, respectively. The +LVDD pin is connected to +VCC through jumper J9 1-2, and
the –LVSS pin is connected to –VEE through J16 1-2. Screw terminal connector J14 provides access to the
output-stage supply pins. To set the voltage level of LVDD and LVSS with an external supply, shunt jumper J9
2-3 to access the +LVDD using connector J14.1. In a similar fashion, shunt jumper J16 2-3 to access the –LVSS
pin using connector J14.3.
Figure 4-1 shows the PGA855EVM voltage supply connections.
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1
3
J13
Input Stage
Power-Supply
Connector
D2
36 V
2
TP11
VCC
VCC
VEE
TP16
VEE
1
2
3
VCC
LVDD+
J9
1
2
3
VEE
LVSS–
J16
VCC
VEE
VCC
VEE
PGA855 Output
Stage Supplies
D1
D3
D5
36 V
D4
36 V
PGA855 Input
Stage Supplies
VCC
C2
100 nF
VEE
C15
100 nF
FDA_IN+
+
OUT+
IN+
IN–
R3
R1
R2R4
FDA_IN–
+
+
PGA855
+
Gain Network
A0 A1 A2
A0
A1A2
Overvoltage
Protection
VS+
DGND
DGND
LVDD
OUT–
–
–
–
–
LVDD+ C3
100 nF
C16
100 nF
LVSS–
1
3
J14
2
4
Output Stage
Power-Supply
Connector
TP15
LVSS–
TP10
LVDD+
VCC+
GND
VEE–
LVDD+
GND
LVSS–
GND
Overvoltage
Protection
VS– LVSS
VOCM
C19
100 nF
C22
100 nF
C21
100 nF
C18
100 nF
C20
10 µF
C17
10 µF
Figure 4-1. PGA855EVM Voltage Supply Connections
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5 Analog Input and Output Connections
The programmable amplifier input signal connections for the PGA855EVM are provided through the use of SMA
connectors J3, J6, and test points TP3, TP7, located at the left of the EVM. The VOCM input is provided through
screw-terminal connector J1, located on the left of the board.
The differential output amplifier connections are provided through screw-terminal connector J4, SMA connectors
J2 and J8, and test points TP4 and TP6, located at the right side of the EVM. Figure 5-1 displays a simplified
diagram of the PGA855EVM input and output connections.
SMA
Connector
J3
J6
SMA
Connector
IN+
IN–
R4 100

R9 100

C10
C6
C13
100 pF
10pF
10pF
R8 100

C8
100 pF
J4.4
J4.1
J4.3
J4.2
Output
Connector
OUT+
OUT–
DNP
DNPC4
C14
VCC
C2
100 nF
VEE
C15
100 nF
J1.1
J1.2
VCC
VEE
R2
VOCM
Connector
1
2
3
J5
1
2
3
J7
C1
100 nF
R5 100

100

R1
10 k

R3
10 k

FDA_IN+
+
OUT+
IN+
IN–
R3
R1
R2R4
FDA_IN–
+
+
PGA855
+
Gain Network
A0 A1 A2
A0
A1A2
Overvoltage
Protection
Overvoltage
Protection
VS+
DGND
LVDD
OUT–
–
–
–
–
LVDD+ C3
100 nF
J2
SMA
Connector
OUT+
J8
SMA
Connector
OUT–
C16
100 nF
LVSS–
TP3
IN+
TP7
IN–
TP4
OUT–
TP6
OUT+
TP1
VOCM
TP2
GND
TP9
GND
TP8
GND
TP5
GND
VS– LVSS
VOCM
Figure 5-1. PGA855EVM Analog Input and Output Connections
Table 5-1 summarizes the input and output connectors and corresponding test points.
Table 5-1. PGA855EVM Analog Input and Output Connections
Connector Designator Signal Comment Test Point
J3 IN+ SMA TP3
J6 IN– SMA TP7
J2 OUT– SMA TP4
J8 OUT+ SMA TP6
J4.4 OUT– Screw terminal TP4
J4.3 GND Screw terminal TP2
J4.2 GND Screw terminal TP9
J4.1 OUT+ Screw terminal TP6
J1.1 VOCM Screw terminal TP1
J1.2 GND Screw terminal N/A
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6 Digital Input Pins and Gain Control
The PGA855 provides eight binary gain settings, from an attenuating gain of 0.125 V/V to a maximum of 16 V/V.
The gain is controlled by three digital selection pins: A0, A1, and A2. By default, the PGA855 is configured to a
gain of 0.125 V/V.
The evaluation board provides shunt jumpers J10, J11, and J12 to set the PGA855 gain-control selection pins.
Table 6-1 lists the gain-control options. To set the gain-control pin high, install the shunt on the corresponding
jumper. To set the gain-control pin low, remove the shunt jumper.
Table 6-1. PGA855EVM Gain Control
A2
Jumper J10
Connector J15.1
A1
Jumper J11
Connector J15.2
A0
Jumper J12
Connector J15.3
PGA Gain (V/V)
Low (Open) Low (Open) Low (Open) 0.125
Low (Open) Low (Open) High (Shunt) 0.25
Low (Open) High (Shunt) Low (Open) 0.5
Low (Open) High (Shunt) High (Shunt) 1
High (Shunt) Low (Open) Low (Open) 2
High (Shunt) Low (Open) High (Shunt) 4
High (Shunt) High (Shunt) Low (Open) 8
High (Shunt) High (Shunt) High (Shunt) 16
Alternatively, the A0, A1, and A2 digital pins can be driven externally through connector J15. Any pin that is not
driven by an external source, or any shunt that is left open, is biased at DGND using pulldown resistors. Figure
6-1 shows the gain-setting block diagram.
J10 J11 J12
1
2
1
2
1
2
A2 A1 A0
A0
A1
A2
100 k

100 k

100 k

+VCC
R16 R17 R18
1
3
J15
2
4
PGA855 Gain
CTRL Connector
GND
PGA855
Gain Control
A1
DGND
A2
A0
Figure 6-1. PGA855EVM Gain Control
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7 Modifications
For flexibility, the EVM provides optional capacitors C4 and C18. These capacitors are in parallel with the
PGA855 output-stage internal-feedback resistors to implement noise filtering. In addition, the evaluation board
provides footprints R6, R10, C9, C5, and C12 for optional input low-pass filters, and footprints for load resistors
R7 and R11. These additional component footprints in the layout allow the user to customize the evaluation
circuit. For a full schematic of the PGA855EVM, see Figure 8-1.
8 Schematic, PCB Layout, and Bill of Materials
This section contains the schematic, PCB layout, and bill of materials for the PGA855EVM.
8.1 Schematic
Figure 8-1 illustrates the EVM schematic.
GND
GND
TP4
OUT-
TP6
OUT+
GND
GND
0R13
0 R15
LVDD+_ext
LVSS-_ext
GND GND
Note: R7, R11, are not populated, for flexibility
1
2 3 4 5
J6
1
2
3
4
5
J3
TP7
IN-
GND
GND
0R10
0R6
10uF
C17
100nF
C18
GND
1
2
3
J13
10uF
C20
100nF
C21
VCC
VEE
TP9
GND
GND
TP2
GND
GND
1
2
3
4 5
J2
GND
1
2
3
4
5
J8
GND
TP1
VOCM 10.0k
R1
10.0k
R3
VEE
VCC
1
2
J1
GND
VEE
VCC
GND
GND
GND
TP10
LVDD+
TP15
LVSS-
100nF
C19
GND
100nF
C22
GND
VCC
VEE
TP11
VCC
TP16
VEE
VEE
100
R5
100
R8
100
R9
100
R4
1.00k
R11
1.00k
R7
GNDGND
TP3
IN+
100nF
50V
C15
100nF
50V
C2
GND
100nF
50V
C1
100
R2
VCC
VEE
36V
D2
Note: C7, C11 are not populated, for flexibility
Note: C5, C9, C12 are not populated, for flexibility
TP5
GND
GND
TP8
GND
GND
50V
10pF
C6
50V
10pF
C13
50V
10pF
C5
50V
10pF
C12
100V
100pF
C8
50V
10pF
C7
50V
10pF
C11
1
2
3
J9
LVSS- to Vee
LVSS- to Ext
LVDD+ to Ext
LVDD+ to Vcc
0R12
VEE
1
2
3
J16
0R14
1
2
3
4
J4
1
2
3
4
1
2
3
4
J14
OSTTE040161
1 2
3
D1
VCC
VEE
1 2
3
D3
VCC
100V
100pF
C10
100V
100pF
C9
LVSS
OUTP
OUTN
INN
VOCM
INP
LVDD
VCC
FDA_INP
FDA_INN
A0
A1
A2
INN
3INP
2
A1
5
NC 8
VS- 15
A2
1
FDA_INP
12
LVSS 14
VOCM
13
A0
4
LVDD
7VS+
6
OUTN 11
FDA_INN
9
OUTP 10
DGND 16
PAD 17
PGA85xRGT
U1 PGA85x
VS+
VS-
VOCM
LVSS
LVDD
INP
INN
OUTN
OUTP
FDA_INP
FDA_INN
TP12
A2
A0
A1
A2
10.0k R16 10.0k R17 10.0k R18
TP13
A1
TP14
A0
PGA85x Gain CTRL
TP17
GND
VCC
1
2
J10
A2
1
2
J11
A1
1
2
J12
A0
4
1
2
3
J15
PGA85x Output Stage SuppliesPGA85x Input Stage Supplies
GND GND
GND
LVDD
LVSS
LVDD
GND
100nF
50V
C3
LVSS GND
100nF
50V
C16
VOCM
PGA85x
GND
VOCM
C0G/NP0
50V
10pF
C4
C0G/NP0
50V
10pF
C14
VCC
36V
D4
36V
D5
GND
VEE
GND
Note: C4, C14 Not populated. C4, C14 can be used to reduce BW / filter noise.
1
2
3
J5
1
2
3
J7
Note: DNP components are not populated.
Figure 8-1. PGA855EVM Schematic
8.2 PCB Layout
The PGA855EVM is a four-layer PCB design. Figure 8-2 to Figure 8-6 show the PCB layer illustrations. The
top layer consists of all signal path traces, and is poured with a solid ground plane. A symmetrical board layout
is used at the differential inputs and outputs to keep good performance matching and improve common-mode
noise rejection. Route traces as symmetrically as possible for both positive and negative pathways. The optional
differential input low-pass filter capacitor is placed in very close proximity to the PGA inputs to reduce extrinsic
noise. Capacitor C1 is placed in close proximity to VOCM to avoid injecting common-mode noise. Decoupling
capacitors C2, C15, C3 and C16 are positioned on the top layer as close as possible to the power-supply pins of
the device. The second internal layer is a dedicated solid GND plane. Independent vias are placed at the ground
connection of every component to provide a low-impedance path to ground. The third internal layer and bottom
layer route the input stage power supplies and the output-stage supply connections.
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Figure 8-2. Top Overlay PCB Layout
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Figure 8-3. Top Layer PCB Layout
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Figure 8-4. Ground Layer PCB Layout
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Figure 8-5. Power Layer PCB Layout
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Figure 8-6. Bottom Layer PCB Layout
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8.3 Bill of Materials
Table 8-1 lists the PGA855EVM bill of materials (BOM).
Table 8-1. PGA855EVM Bill of Materials
Designator Quantity Value Description Package Reference Part Number Manufacturer
!PCB1 1 Printed Circuit Board AMPS178 Any
C1, C2, C3, C15, C16 5 0.1 µF CAP, CERM, 0.1 uF, 50 V, +/- 5%, X7R, 0603 603 C0603C104J5RACTU Kemet
C6, C13 210 pF CAP, CERM, 10 pF, 50 V, +/- 1%, C0G/NP0, 0603 603 C0603C100F5GAC7867 Kemet
C7, C11 2 10 pF CAP, CERM, 10 pF, 50 V, +/- 5%, C0G/NP0, 0805 805 08055A100JAT2A AVX
C8, C10 2 100 pF CAP, CERM, 100 pF, 100 V, +/- 5%, C0G/NP0,
0805
805 C0805C101J1GACTU Kemet
C17, C20 2 10 µF CAP, CERM, 10 uF, 35 V, +/- 10%, X7R, 1206 1206 C3216X7R1V106K160AC TDK
C18, C19, C21, C22 40.1 µF CAP, CERM, 0.1 uF, 50 V, +/- 10%, X7R, 0805 805 08055C104KAT2A AVX
D1, D3 2Diode Array 1 Pair Series Connection Schottky 40
V 200 mA (DC) Surface Mount SC-70, SOT-323
SOT-323 BAT854SWF Nexperia
D2, D4, D5 3 36 V Diode, TVS, Uni, 36 V, 75 Vc, SOD-323 SOD-323 CDSOD323-T36S Bourns
H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips
panhead
Screw NY PMS 440 0025 PH B&F Fastener Supply
H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
J1 1 Terminal Block, 3.5mm Pitch, 2x1, TH 7.0x8.2x6.5mm ED555/2DS On-Shore Technology
J2, J3, J6, J8 4 Connector, End launch SMA, 50 ohm, SMT End Launch SMA 142-0701-801 Cinch Connectivity
J4, J14 2TERM BLOCK 3.5MM VERT 4POS PCB HDR4 OSTTE040161 On Shore Technology
J5, J7 2 Header, 100mil, 3x1, Gold, SMT Samtec_TSM-103-01-X-SV TSM-103-01-L-SV Samtec
J9, J16 2Header, 100mil, 3x1, Gold, TH PBC03SAAN PBC03SAAN Sullins Connector Solutions
J10, J11, J12 3Header, 100mil, 2x1, Gold, TH 2x1 Header TSW-102-07-G-S Samtec
J13 1 Terminal Block, 3.5mm Pitch, 3x1, TH 10.5x8.2x6.5mm ED555/3DS On-Shore Technology
J15 1 Header, 100mil, 4x1, Gold, TH 4x1 Header TSW-104-07-G-S Samtec
R1, R3 2 10 kΩ RES, 10.0 k, 1%, 0.1 W, 0603 603 ERJ-3EKF1002V Panasonic
R2 1100 Ω RES, 100, 1%, 0.1 W, 0603 603 RC0603FR-07100RL Yageo
R4, R5, R8, R9 4 100 Ω RES, 0, 0.1%, 0.125 W, 0805 805 RT0805BRD07100RL Yageo America
R6, R10 20 Ω RES, 0, 5%, 0.125 W, AEC-Q200 Grade 0, 0805 805 ERJ-6GEY0R00V Panasonic
R12, R13, R14, R15 4 0 Ω RES, 0, 5%, 0.1 W, 0603 603 RC0603JR-070RL Yageo
R16, R17, R18 310.0 kΩ RES, 10.0 k, 1%, 0.1 W, 0603 603 RCG060310K0FKEA Vishay Draloric
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Table 8-1. PGA855EVM Bill of Materials (continued)
Designator Quantity Value Description Package Reference Part Number Manufacturer
SH-J1, SH-J2, SH-
J3,SH-J4
,SH-J5,SH-J6
61 × 2 Shunt, 100mil, Flash Gold, Black Closed Top 100mil Shunt SPC02SYAN Sullins Connector Solutions
TP1, TP2, TP3, TP4,
TP5, TP6, TP7, TP8,
TP9, TP10, TP11, TP15,
TP16
13 Test Point, Miniature, SMT Test Point, Miniature, SMT 5019 Keystone
TP12, TP13, TP14,
TP17
4 Test Point, Compact, SMT Testpoint_Keystone_Comp
act
5016 Keystone
U1 1 Low-Noise, Wide-Bandwidth, Fully Differential
Output, Programmable Gain Amplifier
VQFN17 PGA855RGT Texas Instruments
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

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2
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.

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Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
https://www.ti.com/ja-jp/legal/notice-for-evaluation-kits-delivered-in-japan.html
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。https://www.ti.com/ja-jp/legal/notice-for-evaluation-kits-for-power-line-communication.html
3.4 European Union
3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.