Texas Instruments LMK5C33216EVM User manual

User’s Guide
LMK5C33216EVM User's Guide
ABSTRACT
The LMK5C33216EVM is an evaluation module for the LMK5C33216 Network Clock Generator and
Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 EVM Quick Start......................................................................................................................................................................4
3 EVM Configuration..................................................................................................................................................................7
3.1 Power Supply..................................................................................................................................................................... 8
3.2 Logic Inputs and Outputs................................................................................................................................................... 9
3.3 Switching Between I2C and SPI...................................................................................................................................... 10
3.4 Generating SYSREF Request..........................................................................................................................................11
3.5 XO Input........................................................................................................................................................................... 11
3.6 Reference Clock Inputs....................................................................................................................................................13
3.7 Clock Outputs...................................................................................................................................................................13
3.8 Status Outputs and LEDS................................................................................................................................................ 13
3.9 Requirements for Making Measurements........................................................................................................................ 13
4 EVM Schematics................................................................................................................................................................... 14
4.1 Power Supply Schematic................................................................................................................................................. 14
4.2 Power Distribution Schematic.......................................................................................................................................... 15
4.3 LMK5C33216 and Input Reference Inputs IN0 to IN1 Schematic....................................................................................16
4.4 Clock Outputs OUT0 to OUT3 Schematic........................................................................................................................17
4.5 Clock Outputs OUT4 to OUT9 Schematic........................................................................................................................18
4.6 Clock Outputs OUT10 to OUT15 Schematic....................................................................................................................19
4.7 XO Schematic.................................................................................................................................................................. 20
4.8 Logic I/O Interfaces Schematic........................................................................................................................................ 21
4.9 USB2ANY Schematic.......................................................................................................................................................22
5 EVM Bill of Materials.............................................................................................................................................................23
5.1 Loop Filter and Vibration Nonsensitive Capacitors.......................................................................................................... 27
6 Appendix A - TICS Pro LMK5C33216 Software..................................................................................................................28
6.1 Using the Start Page........................................................................................................................................................ 28
6.2 Using the Status Page..................................................................................................................................................... 30
6.3 Using the Input Page........................................................................................................................................................31
6.4 Using APLL1, 2, and 3 Pages.......................................................................................................................................... 34
6.5 Using the DPLL1, 2, and 3 Pages....................................................................................................................................36
6.6 Using the Validation Page................................................................................................................................................ 36
6.7 Using the GPIO Page.......................................................................................................................................................37
6.8 Using the Outputs Page................................................................................................................................................... 37
7 Revision History................................................................................................................................................................... 38
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
Overview
The LMK5C33216EVM is an evaluation module for the LMK5C33216 Network Clock Generator and
Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. The
LMK5C33216 integrates three Analog PLLs (APLL) and three Digital PLLs (DPLL) with programmable loop
bandwidth. The EVM includes SMA connectors for clock inputs, oscillator inputs, and clock outputs to interface
the device with 50-Ω test equipment.
The onboard TCXO allows the LMK5C33216 to be evaluated in free-running, locked, or holdover mode of
operation. The EVM can be configured through the onboard USB microcontroller (MCU) interface using a PC
with TI's TICS Pro software graphical user interface (GUI). TICS Pro can be used to program the LMK5C33216
registers.
Features
• LMK5C33216 DUT
What is Included
• LMK5C33216EVM
What is Needed
• Windows PC with TICS Pro Software GUI
• Test Equipment
– DC power supply (5 V, 2 A)
– Real-time oscilloscope
– Source signal analyzer
– Precision frequency counter
– Signal generator / reference clock
In Figure 1-1, jumper position is shown by the red markings. Dip switch positions are shown be either a green
box (for ON) or red box (for OFF) in the appropriate location.
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Figure 1-1. LMK5C33216EVM Default Setting of Jumpers and Dip Switches
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2 EVM Quick Start
Table 2-1 describes the default jumper positions for the EVM to power the device from a single 4.5 V supply
provided to VIN1. In positional information about jumpers, adj des means jumper is placed adjacent to
designator. Opp des means jumper is placed opposite designator.
Table 2-1. Default Jumper and DIP Switch Settings
CATEGORY REF DES POSITION DESCRIPTION
Power JP1 1-2 (adj des) DUT VDD = 3.3 V from LDO1 provided by U3.
JP2 1-2 (adj des) DUT VDDO = 3.3 V from LDO2 rail provided by U3.
JP3 1-2 (adj des) LDO3 IN powered from VIN1 external supply.
JP4 1-2 (adj des) XO VCC = 3.3 V from LDO3.
Communication JP5 1-2, 3-4 Connect I2C from onboard USB2ANY to DUT
LMK5C33216 Control Pins S3 S5[1:2] = OFF SCS_ADD = no pull-up or pull-down.
S1, S2, S4 Sx[1,2] = OFF
Sx[3,4] = ON
Enable 3.9k pull-down on GPIO0, GPIO1, and GPIO2
To begin using the LMK5C33216, follow the steps below.
Hardware Setup
1. Verify the EVM default jumper and DIP switch settings shown in Table 3-1.
2. Connect Power, +4.5 V from an external DC power supply (2-A limit), see Figure 3-2.
a. To VIN1 & GND terminals on header J1 (pins 1 and 4), or
b. To VIN1 SMA connector J2.
3. Connect references.
a. 156.25 MHz reference clock to IN0_P/N and/or,
b. 10 MHz reference clock to IN1_P/N
4. Connect USB cable to USB port at J41.
Software Setup
1. If not already installed, install TICS Pro software from TI website:
2. If the MATLAB R2015b (9.0)* 64-bit runtime is not already installed, download and install from MathWorks
website. While optional for programming and evaluating the default profile settings, the Matlab Runtime is
necessary for any application that needs to modify the DPLL loop filter settings. See
3. Start TICS Pro software
4. Select the LMK5C33216 profile from Select Device → Network Synchronizer Clock (Digital PLLs) →
LMK5C33216
5. Confirm communications with board by
a. From the menu bar, click USB communications.
b. Click Interface
c. In Communication Setup pop-up window.
i. Ensure USB2ANY is selected as the interface.
ii. In case of multiple USB2ANY, select desired interface. If a USB2ANY is currently in use in another
TICS Pro, you must release that interface by changing its interface setting to DemoMode
iii. Click identify to blink LED illustrated in Figure 2-1. This confirms you are connected to the board you
expect.
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Figure 2-1. USB LED
Program LMK5C33216
1. Toggle switch S5 (PDN/RESET).
2. Program all the registers by…
a. Pressing Write All Regs button in toolbar
b. From the menu bar click USB Communications then click Write All Registers, or
c. Pressing Ctrl + L.
3. Current consumption should be approximately 1.15 A.
4. Check LMK5C33216 Status
a. Status Page of GUI
b. Click Read Status Bits
c. To clear latched bits.
i. Press Clear Latched Bits button
ii. Read Status Bits
d. It may take some time for the DPLL status bits to reflect lock.
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Figure 2-2. Read Status Bits
Measure
Measurements may now be made at the clock outputs.
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3 EVM Configuration
The LMK5C33216 is a highly configurable clock chip with multiple power domains, PLL domains, and clock input
and output domains. To support a wide range of LMK5C33216 use cases, the EVM was designed with more
flexibility and functionality than needed to implement the chip in a customer system application.
This section describes the power, logic, and clock input and output interfaces on the EVM, as well as how to
connect, set up, and operate the EVM. Refer to Figure 4-1.
Table 3-1. Key Components REF DES and Descriptions
ITEM NO. REF DES DESCRIPTION
1 U1 LMK5C33216 DUT
2A J1 (VIN1 terminal block header), or External Supply, +5 V using default configuration.
B J2 (VIN1 SMA) Not populated by default
3A Y1, or
B J8
4 J4/5, J6/7 SMA Ports for DUT Clock Inputs (IN0_P/N and
IN1_P/N)
5
J9/11, J10/12, J13/15, J14/16, J17/19, J18/20,
J21/J23, J22/24, J25/27, J26/28, J29/31,
J30/32, J33/35, J34/36, J37/39, J38/40
SMA Ports for DUT Clock Outputs
6 S5
Normally open. Push button for DUT power down
(PDN pin). Connect R76 to enable control of the
PDN pin through the GUI
7 JP5 Jumper Header for I2C/SPI interface (MCU to
DUT)
8 D6 SCL or SCK busy indication LED.
9 J41 USB Port for MCU
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Figure 3-1. Key Components - EVM Top Side
3.1 Power Supply
The LMK5C33216 has VDD and VDDO supply pins that operate from 3.3 V ± 5%.
J1 is the main power terminal to the external power supply. Power SMA port VIN1 (J2) provides an alternative
connector style to apply power through coax cable. By default this SMA connector is not populated.
On the EVM, the default power configuration uses the onboard LDO regulators to power all VDD and VDDO pins
from an external 5-V supply input VIN1 to J1 (or J2). A Dual LDO regulator (U3) is used to power the VDD and
VDDO rails of the DUT and its peripheral circuitry. A separate LDO regulator (U4),also supplied from VIN1, is
used to power the onboard XO circuits.
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Note
Not every power connection is used or required to operate the EVM. Other power configurations are
possible. See the power schematics in Figure 4-1 and Figure 4-2.
Figure 3-2. Default Power Jumper Configuration
Figure 3-2 shows the default power jumper locations and settings. Table 3-2 shows the suggested power
configurations for the DUT.
Table 3-2. Suggested Power Configurations
CONNECTION NAME ONBOARD LDO REGULATORS
(DEFAULT)
DIRECT EXTERNAL SUPPLIES
VD = 3.3 V (LDO1)
VDDO = 3.3 V (LDO2)
VDD = 3.3 V (EXT. VIN1)
VDDO = 3.3 V (EXT. VIN2)
J1 PWR Pin 1 (VIN1): Connect to external 5-V
supply
Pin 2 (VIN2): n/a
Pin 3 (VIN3): n/a
Pin 4 (GND): Connect to supply ground
Pin 1 (VIN1): Connect to external 3.3-V supply
Pin 2 (VIN2): Connect to external 3.3-V supply Pin 3
(VIN3): n/a
Pin 4 (GND): Connect to supply ground
JP1 VDD Tie pins 1-2 (adjacent to designator) to
select 3.3 V from LDO1 to VDD Plane
Tie pins 2-3 (opposite to designator) to select
external VIN1 to VDD Plane
JP2 VDDO Tie pins 1-2 (adjacent to designator) to
select 3.3 V from LDO2 to VDDO Plane
Tie pins 2-3 (opposite to designator) to select
external VIN2 to VDDO Plane
3.2 Logic Inputs and Outputs
The logic I/O pins of the DUT support different functions depending on the device start-up mode chosen by the
GPIO1 input level upon POR.
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The default logic input pin states are determined by onboard pullup or pulldown resistors, but some input pins
can be driven to high or low state by the MCU output or DIP switch control. The MCU can be controlled from a
PC running TICS Pro software to program the device registers through I2C or SPI and also drive the DUT logic
inputs. To allow the MCU to control the pin input, SW[2] must be set to on.
See Table 3-3 for the logic pin mapping tables for the device start-up modes.
Table 3-3. Device Start-Up Modes
GPIO1 Input Level1Start-up Mode
0 I2C Mode
1 SPI Mode
1. The input levels on these pins are sampled only during POR.
3.3 Switching Between I2C and SPI
To switch the EVM between I2C and SPI modes, the switches and jumpers must be configured as follows:
Figure 3-3. I2C Mode Jumper Configuration Figure 3-4. SPI Mode Jumper Configuration
In SPI mode, GPIO2 must also be configured as STATUS or INT and SPI Readback Data (SDO) to support SPI
readback.
Figure 3-5. GPIO2 Setting for SPI Mode
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Figure 3-6. Communication Setup Window (Changing from I2C to SPI)
3.4 Generating SYSREF Request
GPIO0 and GPIO1 can be used to generate a SYSREF request. The TICS Pro software + EVM is designed to
use GPIO2 for SPI readback (SDO). Accordingly, GPIO2 is not listed in the pins as it is dedicated for SPI
readback. In user application, any GPIO pin may be used.
Connect the desired GPIO pin to the MCU by setting S2 as ON on the switch block for the desired GPIO. Then,
make sure the GPIO pin is configured for SYSREF_REQ on the GPIO tab of the GUI. A SYSREF Request can
now be issued by toggling the GPIO buttons in the Pins section of the User Controls tab.
Figure 3-7. GPIO Setting for SYSREF Request
Figure 3-8. SYSREF Request Control
Figure 3-9. GPIO Pin Selection for SYSREF
3.5 XO Input
The LMK5C33216 has an XO input (XO_P pin) to accept a reference clock for the Fractional-N APLLs. The XO
input determines the output frequency accuracy and stability in free-run or holdover modes. For synchronization
applications like SyncE or IEEE 1588, the XO input would typically be driven by a low frequency TCXO, OCXO,
or external traceable clock that conforms to the frequency accuracy and holdover stability requirements of the
application. For DPLL mode, the XO frequency must have a non-integer frequency relationship with the VCO
frequency of any APLLs which utilize XO input as their reference. For APLL only mode (DPLL not used), the XO
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frequency can have an integer relationship with the VCO to avoid fractional spurs. Any APLL may accept any
other APLL as a reference instead of the XO. The BAW on APLL3 provides a good option for a high frequency
cascaded referenced.
The XO input of the LMK5C33216 has programmable on-chip input termination and AC-coupled input biasing
options to support any clock interface type.
For flexibility, the EVM provides the XO input options (use one at a time). C70 allows an external reference to be
provided at SMA connector XO_P (J8). C71 allows one of the on board XO/TCXO/OCXO footprints to be used.
By default Y1 is populated with a 38.88 MHz TCXO and selected with the populated R43. Other XO/TCXO/
OCXO may be installed and connected using the appropriate resistor. Care should be taken if more than one
device is installed to remove resistors for isolation.
Figure 3-10. XO Input
3.5.1 38.88-MHz TCXO (Default)
By default, the EVM is populated with a 38.88-MHz, 3.3-V LVCMOS, low-jitter TCXO (Y1) to drive the XO_P
input of the DUT with the onboard termination and AC coupling. See Figure 3-10. Y1 can be used to evaluate
various frequency configurations.
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3.5.2 External Clock Input
Another option is to feed an external clock to the SMA ports (J8) to drive the XO_P input. See Figure 3-10. This
path can be connected to the XO_P input pins. Y1 should be powered down when using the external XO input
path.
3.6 Reference Clock Inputs
The LMK5C33216 has two DPLL reference clock input pairs (IN0_P/N and IN1_P/N) with configurable input
priority and input selection modes. The inputs have programmable input type, termination, and biasing options to
support any clock interface type.
External LVCMOS or Differential reference clock inputs can be applied to the SMA ports, labeled IN0_P/N and
IN1_P/N. All SMA inputs are routed through 50-Ω single-ended traces and DC coupled to the corresponding
IN0_P/N and IN1_P/N pins of the DUT. Single ended singles should be connected to the non-inverting input,
IN0_P or IN1_P.
3.7 Clock Outputs
The LMK5C33216 has 16 clock output pairs (OUT[0:15]_P/N).
Output clocks are AC-coupled to the SMA ports labeled OUT[0:15]_P/N.
3.8 Status Outputs and LEDS
Status outputs signals can be configured on the GPIO0, GPIO1, and GPIO2 pins. The status output signal,
output type (3.3-V LVCMOS or NMOS open-drain).
3.9 Requirements for Making Measurements
When performing measurements with the LMK5C33216EVM, the following procedures must be completed:
1. Ensure all required outputs have proper termination components installed to match the desired output types.
Recommended output terminations for each output type are shown in Figure 3-11.
LMK5C33216
Output Driver
Oscilloscope
100

Internal input biasing
RB RB
Driver
LVDS
CML*
LVPECL
HCSL
RB(

)
open
open
120
50
*CML driver has 50-

pull-up
Figure 3-11. Output Termination Recommendations
2. Ensure all enabled outputs that are not connected to any test equipment have a 50 Ω SMA termination. An
example of a 50 Ω SMA termination is shown in Figure 3-12.
Figure 3-12. 50 Ω SMA Termination
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4 EVM Schematics
4.1 Power Supply Schematic
SELECT LDO or BYPASS
1uF
C20
DUAL 1-A LDO REG (LDO1, LDO2) for DUT VDD & VDDO rails
VDDO_PLANE
TP5
VDDO
10uF
C19
0.1uF
C12
20V
D1
DIODE_SCHOTTKY
1uF
C21
22uF
C11
10uF
C7
0.01uF
C1
3.3V
LDO2
3.57k
R6
1.15k
R7
1.15k
R3
3.57k
R1
10uF
C2
10uF
C1510uF
C13
FB2
FB1
EN1
EN2
0.1uF
C16
0.1uF
C9
47k
R5
TP1
LDO1
DNP
TP7
VIN2
DNP
TP3
VIN1
DNP
0
R4
LDOIN
0.01uF
C17
DNP
0.01uF
C14
47k
R2
0.01uF
C8
DNP
47µF
C10
10uF
C25
30.9k
R9
10.0k
R10
1-A LDO REG (LDO3) for XO rail
LDO3
10uF
C23
3.6 to 5 V
47µF
C27
LDO3 OUT 3.3V
VIN2
VIN1
47k
R8
0.01uF
C24
EN3
OUT 1
OUT 2
FB/SNS 3
GND
4
EN
5
NR 6
IN
7
IN
8
PAD
9
U3
0.47uF
C22
0.47uF
C26
DUT VDDO OUTPUT POWER (3.3V)
LDO1 OUT: 3.3 V
LDO2 OUT: 3.3 V
1
2
3
4
J1
PWR
TP6
LDO3
DNP
TPS7A8801RTJR
IN1
1
IN1
2
GND 3
IN2
4
IN2
5
EN2
6
NR/SS2
7
SS_CTRL2
8PG2 9
FB2 10
OUT2 11
OUT2 12
GND 13
OUT1 14
OUT1 15
FB1 16
PG1 17 SS_CTRL1
18
NR/SS1
19
EN1
20
PAD 21
U2
1
2
3
JP3
M20-8770342
LDO3 IN
1uF
C5
VDD_PLANE
TP2
VDD
10uF
C4
1uF
C6
22uF
C3
DUT VDD CORE POWER (3.3V)
1
2
3
JP1
M20-8770342
LDO1
20V
D2
DIODE_SCHOTTKY
22uF
C18
1
2
3
JP2
M20-8770342
VDDO
TP4
LDO2
DNP
VIN3
1
2
3 4 5
J2
VIN1
DNP
1
2
3 4 5
J3
VIN2
DNP
POWER INPUT
SH3
SNT-100-BK-G
SH2
SNT-100-BK-G
SH1
SNT-100-BK-G
VDD
Figure 4-1. Power Supplies
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4.2 Power Distribution Schematic
VDD CORE SUPPLY DIST & FILTERING
FB2
FB4
FB6
FB8
FB1
FB7
10uF
C32
10uF
C38
10uF
C44
10uF
C50
VDDO OUTPUT SUPPLY DIST & FILTERING
VDD_PLANE VDDO_PLANE
10uF
C29
DNP
10uF
C47
0.1uF
C28
0.1uF
C46
0.1uF
C31
0.1uF
C37
0.1uF
C43
0.1uF
C49
VDDO_23
VDDO_4TO7
VDDO_8TO13
FB5
1uF
10V
C41
0.1uF
C40
FB3
10uF
C35
DNP
0.1uF
C34
FB9
10uF
C53
0.1uF
C52
TP19
GND
TP21
GND
TP23
GND
TP25
GND
Green
12
D3
VDD PWR
470
R13
Green
12
D4
VDDO PWR
470
R14
POWER LED INDICATORS (DUT, XO, TCXO)
Green
12
D5
XO PWR
470
R15
GND TEST POINTS
TP20
GND
TP22
GND
TP24
GND
TP26
GND
VDDGPIO
FB11
10uF
C59
0.1uF
C58
0.1uF
C55
10uF
C56
FB10
TP8
VDD_IN0
DNP
TP10
VDD_IN1
DNP
TP12
VDD_DIG
DNP
TP14
VDD_APLL1_XO
DNP
TP16
VDD_APLL2
DNP
TP18
VDD_APLL3
DNP
VDD_PLANE VDDO_PLANE VCC_XO
TP9
VDDO_01
DNP
TP11
VDDO_23
DNP
TP13
VDDO_4TO7
DNP
TP15
VDDO_8TO13
DNP
VDDO_1415
0.1uF
C42
0.1uF
C48
0.1uF
C54
0.1uF
C60
0.1uF
C30
0.1uF
C36
0.1uF
C33
0.1uF
C39
0.1uF
C57
0.1uF
C45
0.1uF
C51
NT1
NT_0603
0
R11
0
R16
0
R18
0
R20
0
R22
0
R25
0
R23
0
R21
0
R19
0
R17
0
R12
VDD_IN0
VDD_IN1
VDD_DIG
VDD_APLL1_XO
VDD_APLL2
VDD_APLL3
VDDO_01
TP17
VDDO_1415
0
R24
DNP
VDDO_1415 for LMK5C33216; VDD_IN23 for LMK5C33414
Figure 4-2. Power Distribution
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4.3 LMK5C33216 and Input Reference Inputs IN0 to IN1 Schematic
OUT1_P
OUT1_N
LF2
LF1
OUT0_P
OUT0_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
OUT4_P
OUT4_N
OUT5_P
OUT5_N
OUT6_P
OUT6_N
OUT7_P
OUT7_N
XO_P
LMKSDIO
LMKSCK
LMKGPIO0
LMKGPIO1
LMKGPIO2
LMKPDN
VDDO_23
VDD_APLL3
VDDO_01
VDDO_4TO7
VDDO_8TO13
VDD_APLL1_XO
VDD_IN1
VDD_DIG
DUT
DUT LDO BYP CAPS
LOOP FILTER C2 SELECTION
IN0_P
IN0_N
25V
100nF
C72
VDD_APLL2
25V
0.047µF
C76
DNP
470nF
10V
C75
25V
0.047µF
C73
DNP
OUT8_P
OUT8_N
OUT9_P
OUT9_N
OUT10_P
OUT10_N
OUT11_P
OUT11_N
OUT12_P
OUT12_N
OUT13_P
OUT13_N
IN1_P
IN1_N
OUT14_P
OUT14_N
OUT15_P
OUT15_N
LF3
LMKSCS_ADD
VDD_IN0
LMK5C33216RGCR
VDD_APLL1_XO
8
VDD_APLL2
23
VDD_APLL3
47
VDD_DIG
41
VDD_IN0
33
VDD_IN1
37
VDDO_01
1
VDDO_23
11
VDDO_1415
44
VDDO_4567
28
VDDO_8910111213
55
OUT0_N 3
OUT0_P 2
OUT1_N 4
OUT1_P 5
OUT2_N 13
OUT2_P 12
OUT3_N 14
OUT3_P 15
OUT4_N 26
OUT4_P 27
OUT5_N 25
OUT5_P 24
OUT6_N 30
OUT6_P 29
OUT7_N 31
OUT7_P 32
OUT8_N 52
OUT8_P 51
OUT9_N 53
OUT9_P 54
OUT10_N 57
OUT10_P 56
OUT11_N 58
OUT11_P 59
OUT12_N 61
OUT12_P 60
OUT13_N 62
OUT13_P 63
OUT14_N 43
OUT14_P 42
OUT15_N 45
OUT15_P 46
PD
36
SCK
17
SCS_ADD_TOD
18 SDIO
16
Thermal_Pad 65
XO_P
9
LF1 6
LF2 19
LF3 49
CAP_APLL1
7
CAP_APLL3
48
GPIO0
50
GPIO1
64
GPIO2
10
CAP1_APLL2
22
CAP2_APLL2
21
CAP3_APLL2
20
CAP_DIG
40
IN0_N
35 IN0_P
34
IN1_N
38 IN1_P
39
U1
EXT. SMA XO CLK
SMA_XO_P XO2_P
0
R41
1
2
3 4 5
J8
142-0701-201
49.9
R42
DNP
XO1_P
0.1uF
R40
0.1uF
C70
0.1uF
C71
25V
100nF
C67
25V
0.047µF
C68
DNP
SMA_IN0_P
SMA_IN0_N
0
R30
0
R26
0
R31
0
R27
51
R32
51
R28
DNP
R_IN0_P
R_IN0_N
100
R29
DNP
IN0_N
IN0_P
SMA_IN1_P
SMA_IN1_N
0
R37
0
R33
0
R38
0
R34
51
R39
DNP
51
R35
DNP
R_IN1_P
R_IN1_N
100
R36
DNP
IN1_P
IN1_N
VDDO_1415
100nF
50V
C61
10uF
C62
10uF
C6410uF
C63
10uF
C65
10uF
C66
1
2
3 4 5
J4
IN0_P
1
2
3 4 5
J5
IN0_N
DNP
1
2
3 4 5
J6
IN1_P
1
2
3 4 5
J7
IN1_N
XO3
DPLL INPUT 1
DPLL INPUT 0
C1PLL2
CPLL1
CDIG
C2PLL2
C3PLL2
CPLL3
50V
0.1µF
C69
DNP
50V
0.1µF
C74
DNP
50V
0.1µF
C77
DNP
TP27
LF1
TP28
LF2
TP29
LF3
ClassName: XO_trace ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_traceClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
ClassName: IN_trace
Requires capacitor at R27 if external
50 ohms to ground is used.
Figure 4-3. LMK5C33216 and Input Reference Inputs IN0 to IN1
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4.4 Clock Outputs OUT0 to OUT3 Schematic
OUT0-OUT3 CLOCK OUTPUTS
49.9
R78
DNP
49.9
R82
DNP
SMA_O0_P
SMA_O0_N
OUT0_P
OUT0_N
0.1uF
C97
0.1uF
C99
49.9
R79
DNP
49.9
R85
DNP
SMA_O1_P
SMA_O1_N
OUT1_P
OUT1_N
0.1uF
C98
0.1uF
C100
49.9
R86
DNP
49.9
R90
DNP
SMA_O2_P
SMA_O2_N
OUT2_P
OUT2_N
0.1uF
C101
0.1uF
C103
49.9
R88
DNP
49.9
R92
DNP
SMA_O3_P
SMA_O3_N
OUT3_P
OUT3_N
0.1uF
C102
0.1uF
C104
121
R80
DNP
121
R83
DNP
121
R81
DNP
121
R84
DNP
121
R87
DNP
121
R91
DNP
121
R89
DNP
121
R93
DNP
1
2
3 4 5
J9
OUT0_P
1
2
3 4 5
J11
OUT0_N
1
2
3 4 5
J10
OUT1_P
1
2
3 4 5
J12
OUT1_N
1
2
3 4 5
J14
OUT3_P
1
2
3 4 5
J16
OUT3_N
1
2
3 4 5
J13
OUT2_P
1
2
3 4 5
J15
OUT2_N
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1aClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
Figure 4-4. Clock Outputs OUT0 to OUT3
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4.5 Clock Outputs OUT4 to OUT9 Schematic
OUT4 to OUT9 CLOCK OUTPUTS
OUT4_P
OUT4_N
0.1uF
C105
0.1uF
C107
VDDO_4TO7
49.9
R96
DNP
49.9
R101
DNP
SMA_O5_P
SMA_O5_N
OUT5_P
OUT5_N
0.1uF
C106
0.1uF
C108
49.9
R103
DNP
49.9
R109
DNP
SMA_O6_P
SMA_O6_N
OUT6_P
OUT6_N
0.1uF
C109
0.1uF
C111
VDDO_4TO7
68nH
L1
68nH
L2
0
R98
DNP
121
R95
DNP
121
R100
DNP
49.9
R102
DNP
49.9
R108
DNP
0
R107
DNP
20
R97
20
R106
DNP
1
2
3 4 5
J17
OUT4_P
1
2
3 4 5
J19
OUT4_N
1
2
3 4 5
J18
OUT5_P
1
2
3 4 5
J20
OUT5_N
1
2
3 4 5
J21
OUT6_P
1
2
3 4 5
J23
OUT6_N
49.9
R105
DNP
49.9
R111
DNP
SMA_O7_P
SMA_O7_N
OUT7_P
OUT7_N
0.1uF
C110
0.1uF
C112
121
R104
DNP
121
R110
DNP
1
2
3 4 5
J22
OUT7_P
1
2
3 4 5
J24
OUT7_N
49.9
R113
DNP
49.9
R117
DNP
SMA_O8_P
SMA_O8_N
OUT8_P
OUT8_N
0.1uF
C113
0.1uF
C115
49.9
R115
DNP
49.9
R119
DNP
SMA_O9_P
SMA_O9_N
OUT9_P
OUT9_N
0.1uF
C114
0.1uF
C116
121
R114
DNP
121
R118
DNP
121
R112
DNP
121
R116
DNP
1
2
3 4 5
J25
OUT8_P
1
2
3 4 5
J27
OUT8_N
1
2
3 4 5
J26
OUT9_P
1
2
3 4 5
J28
OUT9_N
49.9
R94
DNP
49.9
R99
DNP
OUT4, Supported formats: LVDS, HSDS, LVPECL, and CML; Source may be VCO2 or VCO3
OUT6, Supported formats: LVDS, HSDS, LVPECL, and CML; Source may be VCO2 or VCO3
OUT8, Supported formats: LVDS, HSDS, LVPECL; Source may be VCO2 or VCO3
OUT5, Supported formats: LVDS, HSDS, and LVPECL; Source may be VCO2 or VCO3
OUT7, Supported formats: LVDS, HSDS, and LVPECL; Source may be VCO2 or VCO3
OUT9, Supported formats: LVDS, HSDS, and LVPECL; Source may be VCO2 or VCO3
SMA_O4_P
SMA_O4_N
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch2a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch2b ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1bClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2b
Figure 4-5. Clock Outputs OUT4 to OUT9
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4.6 Clock Outputs OUT10 to OUT15 Schematic
OUT10-OUT15 CLOCK OUTPUTS
49.9
R121
DNP
49.9
R125
DNP
SMA_O10_P
SMA_O10_N
OUT10_P
OUT10_N
0.1uF
C117
0.1uF
C119
121
R120
DNP
121
R124
DNP
1
2
3 4 5
J29
OUT10_P
1
2
3 4 5
J31
OUT10_N
49.9
R122
DNP
49.9
R127
DNP
SMA_O11_P
SMA_O11_N
OUT11_P
OUT11_N
0.1uF
C118
0.1uF
C120
121
R123
DNP
121
R126
DNP
1
2
3 4 5
J30
OUT11_P
1
2
3 4 5
J32
OUT11_N
49.9
R129
DNP
49.9
R133
DNP
SMA_O12_P
SMA_O12_N
OUT12_P
OUT12_N
0.1uF
C121
0.1uF
C123
49.9
R131
DNP
49.9
R135
DNP
SMA_O13_P
SMA_O13_N
OUT13_P
OUT13_N
0.1uF
C122
0.1uF
C124
121
R128
DNP
121
R132
DNP
121
R130
DNP
121
R134
DNP
1
2
3 4 5
J33
OUT12_P
1
2
3 4 5
J35
OUT12_N
1
2
3 4 5
J34
OUT13_P
1
2
3 4 5
J36
OUT13_N
49.9
R137
DNP
49.9
R140
DNP
0.1uF
C125
0.1uF
C127
49.9
R139
DNP
49.9
R142
DNP
SMA_OUT15_P
SMA_OUT15_N
0.1uF
C126
0.1uF
C128
121
R136
DNP
121
R141
DNP
121
R138
DNP
121
R143
DNP
FOR LMK5C33414, OUT15 is IN3
1
2
3 4 5
J37
OUT14_P
1
2
3 4 5
J39
OUT14_N
1
2
3 4 5
J38
OUT15_P
1
2
3 4 5
J40
OUT15_N
FOR LMK5C33414, OUT14 is IN2
OUT14_P
OUT14_N
OUT15_P
OUT15_N
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1aClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch1a
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch2a ClassName: OUT_LenMatch2b
ClassName: OUT_LenMatch1bClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1bClassName: OUT_LenMatch1b
ClassName: OUT_LenMatch1b
SMA_OUT14_P
SMA_OUT14_N
Figure 4-6. Clock Outputs OUT10 to OUT15
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4.7 XO Schematic
VCC_XO_FILT
3.3V LVCMOS XO (multiple footprints)
OUT_XO
EN_XO
0.1uF
C80
10k
R44
300 ohm
0.35 ohm
0.4A
FB12
Ferrite_Bead
10uF
C79
0.1uF
C78
10k
R45
DNP
VCC_XO
0.1uF
C81
DNP
1 2 3
JP4
XO_PWR
VCC
9
Enable/Disable
8
OUTPUT 5
NC
1NC
2NC
3NC
6NC
7NC
10
GND 4
Y1
ENA5591A
33
R43
±25ppm
48.0048MHz
VDD 4 E/C
GND OUT 3
Y2
DNP
XO3
SH4
SNT-100-BK-G
VDD 4 E/C
1
GND
2OUT 3
Y3
7X-50.000MBB-T
DNP
Control_Voltage(Vc)
Output 3 Supply_Voltage(Vcc)
GND 2
Y4
ROM9070PA
DNP
VCC
3OUTPUT 4
NC 1
NC 2
NC 5
NC 6
GND 7
Y5
ROX2522S4
DNP
VCC_XO_FILT EN_XO VCC_XO_FILT
VCC_XO_FILT
33
R49
DNP XO3
33
R47
DNP XO3
33
R48
DNP XO3
33
R46
DNP XO3
OE
1
NC
2GND 3
CLK+ 4
CLK- 5
VDD
6
CDC64XX-2520
U4
DNP 33
R50
DNP XO3VCC_XO_FILT
EN_XO
0.1uF
C82
DNP
0.1uF
C83
DNP
0.1uF
C85
DNP
ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
ClassName: XO_trace
Figure 4-7. XO
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