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SNVU596–October 2018
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LP8752x-Q1 Configuration Guide
2.2 NRST Pin
The NRST pin (pin 20) is used to reset the device logic/enable device internal logic and IO interface.
When the NRST voltage is below threshold level all power switches, references, controls, and bias
circuitry of the LP8752x-Q1 device are turned off. When NRST is set to high level (and VANA is above
UVLO level) this initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The
I2C host must allow at least 1.2 ms before writing or reading data to the LP8752x-Q1. Device enters
STANDBY-mode after internal startup sequence. The host can change the default register setting by I2C if
needed. The regulator(s) can be enabled/disabled by ENx pin(s) or by I2C interface.
2.3 ENx (GPIOx) Pins
Enable pins EN1 (GPIO1), EN2 (GPIO2), EN3 (GPIO3) (pins 7, 15, 2) are I2C configurable GPIO pins.
The direction, function, and output type (open-drain or push-pull) are programmable for the GPIOs. When
configured as EN pin, they can be used to start the buck converter startup sequence based on
programmed timing. Shutdown times can be programmed as well. It is recommended that the ENx pins be
driven low to until the device is configured to the desired settings. Drive these pins low to disable and high
to enable when programmed as enable signal.
2.4 nINT
The nINT pin (pin 19) is an open-drain, active low output from the LP8752x-Q1 PMIC, and should be
connected to a pullup resistor. In the default OTP an interrupt is generated on this pin whenever the
RESET_REG_INT bit is set high. The RESET_REG_INT bit is set high when either the VANA supply
voltage has decreased below the undervoltage threshold level or the host has requested a reset using the
SW_RESET bit in the RESET register or device is reset by NRST. By monitoring the nINT pin, the MCU
will know when the PMIC registers are reset to the values determined by the OTP, and can take the
necessary actions to ensure that the PMIC is configured as needed.
After a power-on reset the LP8752x-Q1 PMIC requires a delay of 1.2ms before there can be any
communication through the I2C interface. This required delay can be ensured by monitoring the nINT pin.
After a power-on reset the nINT pin is driven high while the registers are reset and the OTP is read to set
the registers to their initial values. After 1.2ms the nINT pin is driven low, signaling that the registers have
been reset and can be configured to fit the design requirements.
NOTE: To monitor the nINT pin correctly, the MCU must clear all interrupts before enabling all of the
outputs on the LP8752x-Q1 PMIC. Write a 1 to the RESET_REG bit in the INT_TOP2
register to clear this interrupt. If all interrupts are not cleared before enabling the LP8752x-
Q1 PMIC ouputs, then there will be no change on the nINT pin when an interrupt is
generated and the MCU will not be able to detect a register reset.
3 Configuration
This section describes the default OTP settings, and how to configure these settings to meet design
requirements.
3.1 Configuration Sequence
Using the setup described in Section 2 allows the MCU to easily configure the LP8752x-Q1 PMIC after a
power-on reset, or after any event causing a register reset. To ensure this is done correctly follow the
sequence described in this section. The following list shows the actions to take in order to ensure the
LP8752x-Q1 PMIC is configured correctly. These actions should be taken after a power-on reset or a
register reset.
1. Power on PMIC. (VVANA > VANAUVLO)
2. Set NRST high
3. Wait for nINT line to be set low. (Check RESET_REG bit, and set ENx pin low if necessary )
4. Set new configuration using I2C communication in recommended order. See Section 3.3
1. Voltage settings
