Texas Instruments TPS7A10EVM-004 User manual

TPS7A10EVM-004 Evaluation Module
User's Guide
Literature Number: SBVU040
February 2018

2SBVU040–February 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
User's Guide
SBVU040–February 2018
TPS7A10EVM-004 Evaluation Module
This user’s guide describes the operational use of the TPS7A10EVM-004 evaluation module (EVM) as a
reference design for engineering demonstration and evaluation of the TPS7A10YKA low-dropout linear
regulator (LDO). Setup and operating instructions, thermal and layout guidelines, a printed circuit board
(PCB) layout, a schematic diagram, and a bill of materials (BOM) are included in this user's guide.
Throughout this document, the terms demonstration kit,evaluation board, and evaluation module are
synonymous with the TPS7A10EVM-004.
The following related documents are available through the Texas Instruments website at www.ti.com.
Related Documentation
DEVICE LITERATURE NUMBER
TPS7A10 SBVS314
1 Trademarks
All trademarks are the property of their respective owners.

www.ti.com Introduction
3
SBVU040–February 2018
Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
2 Introduction
Texas Instruments' TPS7A10EVM-004 EVM helps design engineers evaluate the operation and
performance of the TPS7A10 family of linear regulators for possible use in circuit applications. This
particular EVM configuration contains a single linear regulator for handheld systems. The regulator is
capable of delivering up to 300 mA to the load with ultra-low VIN to VOUT dropout voltage. For stability,
use an output capacitor with a value between 2.2 µF and 47 µF.
2.1 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS7A10EVM-004. Observe all safety precautions.
Warning Warning Hot surface. Contact may cause burns. Do not touch.
CAUTION
The circuit module may be damaged by overtemperature. To avoid damage,
monitor the temperature during evaluation and , as needed, for your system
environment cool
CAUTION
Some power supplies can be damaged by application of external voltages. If
using more than one power supply, check your equipment requirements and
use blocking diodes or other isolation techniques, as needed, to prevent
damage to your equipment.
CAUTION
The circuit module is not a finished product or electrical appliance. The module
does not contain current or voltage thresholds for circuit protection. It must be
used by qualified personnel with additional equipment for evaluation only.

EVM Setup www.ti.com
4SBVU040–February 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
3 EVM Setup
This section describes how to properly connect and set up the TPS7A10EVM-004, including the jumpers
and connectors on the EVM board.
3.1 Input/Output Connectors and Jumper Descriptions
3.1.1 J1 – GND
Bias ground return connector.
3.1.2 J2 – BIAS_S
Bias sense pads for an SMA jack.
3.1.3 J3 – BIAS
Bias power-supply connector.
3.1.4 J4 – IN to BIAS short
Short this jumper to tie IN to BIAS.
3.1.5 J5 – IN
Input power-supply voltage connector. Twist together the positive input lead and ground return lead from
the input power supply, and keep the leads as short as possible to minimize input inductance.
3.1.6 J6 – OUT
Regulated output voltage connector.
3.1.7 J7 – IN_S
Input sense pads for an SMA jack.
3.1.8 J8 – OUT_S
Output sense pads for an SMA jack.
3.1.9 J9 – EN
Output enable. To enable the output, connect a jumper to short VIN to EN or BIAS to EN.
3.1.10 J10 – GND
Input ground return connector.
3.1.11 J11 – GND
Output ground return connector.
3.1.12 J12 – Short to Disable
Short this jumper to disable the output. Depending on the current drive capability of the input or bias
power supplies, removing a short on J9 may be required so that the power supplies do not over power the
R1 pulldown resistor.
3.1.13 TP1 – BIAS_S
Bias sense test point.

www.ti.com EVM Setup
5
SBVU040–February 2018
Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
3.1.14 TP2 – IN_S
Input sense test point.
3.1.15 TP3 – OUT_S
Output sense test point.
3.1.16 TP4 – EN
Enable test point.
3.1.17 TP5 – GND
Ground test point.
3.1.18 TP6 – GND
Ground test point.
3.2 Soldering Guidelines
To avoid damaging the integrated circuit (IC), use a hot-air system for any solder rework to modify the
EVM for repair or other application reasons.
3.3 Equipment Connection
1. Set the input power supply to 3.3 V (maximum) and turn the power supply off.
2. Set the bias power supply to 5.5 V (maximum) and turn the power supply off.
3. Connect the positive voltage lead from the input power supply to IN at the J5 connector of the EVM.
4. Connect the ground lead from the input power supply to GND at the J10 connector of the EVM.
5. Connect the positive voltage lead from the bias power supply to BIAS at the J3 connector of the EVM.
6. Connect the ground lead from the bias power supply to GND at the J1 connector of the EVM.
7. Connect a 0-A to 300-mA load between OUT and GND.
8. Float J9 and short J12 to disable the output.
4 Operation
1. Turn on the power supplies.
2. Short J9 (the EN pin) to IN or BIAS and float J12 to enable the output.
3. Vary the respective load and input voltage for test purposes if necessary.

PCB Layout www.ti.com
6SBVU040–February 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
5 PCB Layout
Figure 1 to Figure 3 show the PCB layout for this EVM.
Figure 1. Assembly Layer Figure 2. Top Layer Routing
Figure 3. Bottom Layer Routing

www.ti.com Schematic
7
SBVU040–February 2018
Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
6 Schematic
Figure 4 is the schematic for this EVM.

Schematic www.ti.com
8SBVU040–February 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
Figure 4. TPS7A10EVM-004 Schematic

www.ti.com Bill of Materials
9
SBVU040–February 2018
Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
7 Bill of Materials
Table 1 shows the BOM for this EVM.

Bill of Materials www.ti.com
10 SBVU040–February 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
TPS7A10EVM-004 Evaluation Module
(1) These assemblies are ESD sensitive; observe ESD precautions.
(2) These assemblies must be clean and free from flux and all contaminants. Do not use a no-clean flux.
(3) These assemblies must comply with workmanship standards according to IPC-A-610 Class 2.
(4) Unless otherwise noted in the Alternate Part Number or Alternate Manufacturer columns, all parts may be substituted with equivalents.
Table 1. TPS7A10EVM-004 BOM(1)(2)(3)(4)
Designator Quantity Value Description Package
Reference Part Number Manufacturer Alternate Part Number Alternate Manufacturer
!PCB1 1 Printed Circuit Board LP004 Any
C3, C4 2 2.2uF CAP, CERM, 2.2 uF, 10 V,
+ /- 20%, X5R, 0402 0402 GRM155R61A225ME95 MuRata
C7 1 0.1uF CAP, CERM, 0.1 uF, 10 V,
+ /- 10%, X7R, 0402 0402 GRM155R71A104KA01D MuRata
J1, J10, J11 3 Standard Banana Jack,
Insulated, Black 6092 6092 Keystone
J3 1 BANANA JACK, 15A,
Insulated, Nylon, Yellow 940x438x438 mil 108-0907-001 Cinch Connectivity
J4, J12 2 Header, 2.54 mm, 2x1,
Gold, R/A, SMT Header, 2.54 mm, 2x1, R/A, SMT 878980204 Molex
J5, J6 2 Standard Banana Jack,
Insulated, Red 6091 6091 Keystone
J9 1 Header, 100 mil, 3x1, Gold,
SMT Samtec_TSM-103- 01-X-SV TSM-103-01-L-SV Samtec
R1 1 10.2k RES, 10.2 k, 1%, 0.1 W,
0603 0603 CRCW060310K2FKEA Vishay-Dale
SH-J1, SH-J2 2 1x2 Shunt, 100 mil, Gold plated,
Black Shunt 969102-0000-DA 3M SNT-100-BK-G Samtec
TP1, TP2, TP3, TP4,
TP5, TP6 6 Test Point, Compact, SMT Testpoint_Keyston e_Compact 5016 Keystone
U1 1 300 mA Low VIN, Low
VOUT, Ultra-Low Dropout
Regulator, YKA0005AFAF (-
5) YKA0005AFAF TPS7A1011YKA Texas Instruments Texas Instruments
C1, C6 0 2.2uF CAP, CERM, 2.2 uF, 10 V,
+ /- 20%, X7R, 0805 0805 GRM21BR71A225MA01 L MuRata
C2, C5 0 2.2uF CAP, CERM, 2.2 uF, 10 V,
+ /- 10%, X7R, 0603 0603 GRM188R71A225KE15D MuRata
FID1, FID2, FID3 0 Fiducial mark. There is
nothing to buy or mount. N/A N/A N/A
J2, J7, J8 0 Connector, SMA Jack,
Vertical, Gold, SMD SMA 142-0711-201 Cinch Connectivity