Texas Instruments MMWCAS-DSP-EVM User manual

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MMWCAS-DSP-EVM
User's Guide
SPRUIS6–September 2019
MMWCAS-DSP-EVM
The MMWCAS-DSP-EVM is an evaluation platform utilizing the TDA2x high performance, multimedia
application processor based on enhance OMAP architecture implemented with 28-nm technology. The
MMWCAS-RF-EVM is a 4-device, cascaded, array of AWR1243P mmWave devices. This user guide
references the MMWCAS-RF-EVM and Radar Board as the same items. Both boards together provide a
full Radar system evaluation.
Contents
1 Introduction ................................................................................................................... 2
2 Hardware Specifications .................................................................................................... 3
3 mmWave Studio and Matlab Post Processing ......................................................................... 19
List of Figures
1 Caution Hot Surface Warning located on EVM ......................................................................... 3
2 MMWCAS-DSP-EVM Functional Block Diagram ....................................................................... 4
3 MMWCAS-DSP-EVM - Front .............................................................................................. 5
4 MMWCAS-DSP-EVM – Back ............................................................................................. 6
5 MMWCAS-DSP-EVM (bottom) and MMWCAS-RF-EVM (top) Board Alignment ................................... 7
6 System Power Distribution Network ...................................................................................... 8
7 DSP Host to RF Board Connector #1 (J1) .............................................................................. 9
8 DSP Host to RF Board Connector #2 (J18) ........................................................................... 12
9 FPGA Flash Programming Header Pinout ............................................................................. 16
List of Tables
1 DSP Host to RF Board Connector Pin Table (J1) ...................................................................... 9
2 DSP Host to RF Board Connector Pin Table (J18) ................................................................... 12
3 USB Connector Pin Table (J16) ......................................................................................... 15
4 GPIO List and Description ................................................................................................ 17
5 User Configurable Supported Boot Modes ............................................................................. 18
6 Push Button Functionality Information .................................................................................. 18
7 User and Status LED Reference Designator and Description ....................................................... 18
Trademarks
MicroSD is a trademark of SD-3C, LLC.
All other trademarks are the property of their respective owners.

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MMWCAS-DSP-EVM
1 Introduction
The MMWCAS-DSP-EVM is an evaluation platform utilizing the TDA2x high performance, multimedia
application processor based on enhance OMAP architecture implemented with 28-nm technology.
The MMWCAS-DSP-EVM provides a processing foundation for a cascaded imaging radar system.
Cascade radar devices can support front, long-range(LRR) beam-forming applications as well as corner
and side-cascade radar and sensor fusion platforms. The EVM supports SSD storage for longer term
capture scenarios and 1 Gigabit Ethernet connectivity for control and offloading captured data. The
MMWCAS-DSP-EVM may also be referred to as DSP Board throughout this guide.
The EVM interfaces with a companion Cascade Radar EVM (MMWCAS-RF-EVM). The MMWCAS-RF-
EVM is a 4-device, cascaded, array of AWR1243P mmWave devices. This user guide references the
MMWCAS-RF-EVM and Radar Board as the same items. Both boards together provide a full Radar
system evaluation.
1.1 Key Features
The key features of the MMWCAS-DSP-EVM are:
• TDA2SX ADAS SoC (23 mm × 23 mm)
• Four Lattice Crosslink Automotive Grade FPGAs
• 2GByte of DDR3L device
• PCIe 2.0 m.2 connector(m-keyed)
• MicroSD™ Card interface
• JTAG interface through FTDI FT2232HL Chip
• USB interface to provide UART, and I2C interfaces through the onboard FTDI device. This is used for
mmWave Studio.
• User LEDs, 3 push-button switches, and 1×6DIP switches for user BOOT configurations
• 1Gb/s RGMII Ethernet interface with RJ45 jack
• Video- one HDMI Out
• Two HiRose 120-pin Automotive Rated Board-to-Board connectors
• 12-V DC input (Wall supply not included in kit)
• Optimized Power Management IC (PMIC) Solution
• Dimension (L × W): 160 mm × 136 mm
• Expansion connector to support AWR Cascade Radar EVM

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MMWCAS-DSP-EVM
1.2 Kit Contents
The following items are included with the MMWCAS-DSP-EVM kit. Unbox the board and identify various
components and connectors as detailed in the user guide.
• MMWCAS-DSP-EVM Board
• 512GB NVMe PCIE m.2 2280 SSD(assembled on EVM)
• 16GB microSD Card
• Ethernet cable
• Power Cable assembly
• USBA to miniB Cable
• Mounting standoffs and screws
1.3 Thermal Compliance
There is elevated heat on the processor/heatsink; use caution at elevated ambient temperature. Although
the processor/heatsink is not a burn hazard, caution should be used when handling the EVM due to
increased heat in the area of the heatsink.
Figure 1. Caution Hot Surface Warning located on EVM
2 Hardware Specifications
2.1 Functional Block Diagram
The functional block diagram of the MMWCAS-DSP-EVM is shown in Figure 2.

Micron MT41K512M16
x16 8Gbit
Micron MT41K512M16
x16 8Gbit
TDA2x Host Processor (ABC) 2x Micron MT41K512M16
16Gbit, 2x(64 Meg x 16 x 8 banks)
Micron MT41K512M8
4Gbit, 1x(64 Meg x 8 x 8 banks)
OS and Application Memory
2Gbyte Total
ECC Memory
512Mbyte Total
VIN1A Lattice LIF MD6000 CrossFire
FPGA #1
CSI2.0 to VIN Bridge
VIN2A Lattice LIF MD6000 CrossFire
FPGA #2
CSI2.0 to VIN Bridge
VIN3A Lattice LIF MD6000 CrossFire
FPGA #3
CSI2.0 to VIN Bridge
VIN4A Lattice LIF MD6000 CrossFire
FPGA #4
CSI2.0 to VIN Bridge
DDR3-1066
32-Bit+ECC
EMIF1
DDR3-1066
32-Bit
EMIF2
2x Micron MT41K512M16
16Gbit (64 Meg x 16 x 8 banks)
OS and Application Memory
2Gbyte Total
Hirose FX23-120S-
0.5SV10
AWR1243 RF Board
Connectors
CSI2.0
AWR#1
CSI2.0
AWR#2
CSI2.0
AWR#3
CSI2.0
AWR#3
UART3 1:4 MUX
UART AWR#1
UART AWR#2
UART AWR#3
UART AWR#4
SPI1
SPI3
SPI AWR#1/4
SPI AWR#2/3
GPIO SOP
ERROR
UART
USB Bridge
USB2.0
Mini
Connector
UART1
USB3.0
Device
Connector
USB3.0
Super-Speed
(5Gbps)
EMU Port/VOUT
60-Pin MIPI
Debug Header
EMU
DP83867IRPAPR
1G Ethernet PHY RGMII
RJ-45
Magnetics
Micron MT25QL01GBBB8ESF
QSPI Flash, 133MHz, 1Gbit
(128M x 8)
QSPI
HDMI
Type-A
Connector
HDMI1.4a
PCIe m.2
Host Connector
PCIe 2.0
5Gbps
MicroSD Card
Connector MMC1
GPIO AWR_RESETS
2:1 MUX
VOUT 10GigE
Header VOUT
JTAG
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Figure 2. MMWCAS-DSP-EVM Functional Block Diagram

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MMWCAS-DSP-EVM
2.2 Board Dimensions & Description
The MMWCAS-DSP-EVM dimensions are 160 mm × 136 mm. It is a 22-layer board fabricated with epoxy
fiberglass (UL94V-0 Certified). Figure 3 and Figure 4 show the top and bottom layers with key
components identified.
Figure 3. MMWCAS-DSP-EVM - Front

MicroSD
Recepticle
MicroSD
Recepticle
Cascade RF board connector
Cascade RF board connector
Cascade RF board connector
Cascade RF board connector
PCIe m.2 SSD
connector and
screw hole
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MMWCAS-DSP-EVM
Figure 4. MMWCAS-DSP-EVM – Back

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2.3 Attaching MMWCAS-DSP-EVM to MMWCAS-RF-EVM
The MMWCAS-DSP-EVM is designed to have a companion RF board attached to capture radar data. The
EVM provides 5-V power and necessary control to the RF board upon connecting.
The boards align and attach through the board to board connectors (J1 and J18) on the EVM. The
connectors are keyed to prevent incorrect, 180 degree, opposite orientation. The four corner mounting
holes align the boards as well to outline the match. Depressing the RF board connectors into the EVM
connectors connects the boards together. Use the included standoffs to secure a single assembly of the
boards. Refer to Figure 5 for reference.
Figure 5. MMWCAS-DSP-EVM (bottom) and MMWCAS-RF-EVM (top) Board Alignment
2.4 Power
The MMWCAS-DSP-EVM is powered by 12-V power, either from a DC barrel connector (J10) or screw
terminal (J11). A wall DC power source or a bench power source can be used to power the EVM. The
power source should be rated at least 3 A. The typical power source is 12-V, 5-A Advantech Power supply
P/N: 96PSA-A60W12V1-1.
When power is provided, various LEDs around the edge of the board light up, indicating the proper
interfaces have the adequate power. Refer to the block diagram to see location of key status LEDs.
The companion power management IC (PMIC) for the SOC is TPS659039EP-Q1. A step-down 12-V to
3.3-V and 5-V converter is available in order to provide a 3.3-V and 5-V DC input to the PMIC as well as
3.3-V and 5-V power rails at the board level. Figure 6 shows the complete power supply tree.

CUI PJ-002AH DC
Power Jack
x 12V, 5A DC
Supply Input
x System 5.0V Supply
x System 3.3V Suppy
TPS43351QDAPRQ1
Switcher Controller
x TDA2 SoC LDO and SMPS
Supply
x Supplies all Core and Peripheral
Power for entire TDA2 SoC
TPS659039-Q1
(O9039A387IZWSRQ1) PMIC
x Ethernet PHY 1.1V
x Ethernet PHY 2.5V
x DDR3 SDRAM 1.35V Supply
x TDA2 DDR3 Controller 1.35
Supply
x DDR3 SDRAM VTT/VREF
Supply
TPS74801-Q1 LDO
TPS74801-Q1 LDO
TPS57112-Q1 2A, 2-MHz,
Synchronous Step-Down
TPS51200QDRCRQ1
Push-Pull VTT Regulator
Quad AWR1243 RF Board Connector
x 5V, 4A Load Expected
12V
5.0V
3.3V
LP5907QMFX-2.5Q1 LDO
x FPGA 2.5V
TPS62262TDRVRQ1 LDO
x FPGA 1.2V
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Figure 6. System Power Distribution Network
2.5 Connectors
2.5.1 RF Board Connectors (J1, J18)
The primary board to board connectors on the EVM (J1 and J18) are used to connect the board to
MMWCAS-RF-EVM. These connectors are each implemented with a Hirose FX23-120S-0.5SV10
receptacle. J1 contains all the reset, boot, digital control, and CSI2.0 data paths for AWR1243P #1 and
AWR1243P #2. J18 contains the same but for AWR1243P #3 and AWR1243P #4. Both connectors share
common 5-V and GND return paths.

Mates to AWR RF Board P1
AWR1_CSI
58
FPGA1_DPHY0_CLK_P
FPGA1_DPHY0_CLK_N
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N
AWR1_CS I
AWR2_CSI
58
FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N
AWR2_CS I
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N
FPGA1_DPHY0_CLK_P
58
I2C3
FPGA1_DPHY0_CLK_N
TDA_I2C3_SCL
TDA_I2C 3_SD A
TDA_I2C3_SCL
I2C3
TDA_I2C3_SDA
58
UART_AWR1
58
UART_AWR2
TDA_UART1_TXD
TDA_UART1_RXD
UART_AWR1
TDA_UART2_TXD
TDA_UART2_RXD
UART_AWR2
58
AWR_SOP0
58
AWR_SOP1
58
AWR_SOP2
58
AWR_WARM_RST
58
AWR1_RESETN
58
AWR2_RESETN
TDA_UART3_AWR1_RXD
TDA_UART3_AWR1_TXD
TDA_UART3_AWR2_TXD
TDA_UART3_AWR2_RXD
AWR_ERROR_OUTN
58
AWR2_SPI_SCLK
AWR2_SPI_CS0N
AWR2_SPI_MOSI
AWR2_SPI_MISO
AWR1_SPI_CS0N
AWR1_SPI_MOSI
AWR1_SPI_MISO
AWR1_SPI_SCLK
58
AWR1_SPI_SCLK
58
AWR1_SPI_CS0N
58
AWR1_SPI_MOSI
58
AWR1_SPI_MISO
58
AWR2_SPI_SCLK
58
AWR2_SPI_CS0N
58
AWR2_SPI_MOSI
58
AWR2_SPI_MISO
Net Class i
ClassName:AWR1_SPI
Net Class i
ClassName:AWR2_SPI
58
AWR1_SPI_INT
58
AWR2_SPI_INT
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N
FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
TDA_GPIO2_2_AWR1_RESETN
TDA_GPIO2_9_AWR2_RESETN
TDA_GPIO7_24_AWR1_SPI_INT
TDA_GPIO2_19_AWR_ERROR_OUTN
TDA_GPIO2_22_AWR_SOP0
TDA_GPIO2_25_AWR_SOP1
TDA_GPIO2_13_AWR_SOP2
TDA_GPIO2_12_AWR_WARM_RST
P1 P3
MH1 MH3
P2 P4
MH2 MH4
1
10
11
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J1
GND
Hirose_FX23-120S-0_5SV10
GND
AWR_CONN1_MON
AWR_ CONN_TP1
TP1
AWR_CONN_TP2
TP4
TP5
AWR_CONN_TP3
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N
FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N
FPGA1_DPHY0_CLK_P
FPGA1_DPHY0_CLK_N
58
TDA_AWR1_GPIO2
58
TDA_AWR1_GPIO1
58
TDA_AWR1_GPIO0
AWR_EXT_DIG_SYNC
AWR_CONN1_MON
AWR1_SPI_MISO
AWR1_SPI_CS0N
TDA_GPIO7_24_AWR1_SPI_INT
AWR1_SPI_MOSI
AWR1_SPI_SCLK
TDA_I2C3_SCL
TDA_I2C3_SDA
TP3
AWR_CONN_TP5
TDA_GPIO2_19_AWR_ERROR_OUTN
TDA_UART3_AWR1_TXD
TDA_UART3_AWR1_RXD
AWR1_SOP2
0
R1
TDA_GPIO2_13_AWR_SOP2
AWR1_SOP1
0
R2
TDA_GPIO2_25_AWR_SOP1
AWR1_SOP0
0
R3
TDA_GPIO2_22_AWR_SOP0
0
R4
TDA_GPIO2_2_AWR1_RESETN
AWR1_WARM_RST TDA_GPIO2_12_AWR_WARM_RST
AWR2_SPI_MISO
AWR2_SPI_CS0N
AWR2_SPI_MOSI
AWR2_SPI_SCLK
TDA_UART3_AWR2_TXD
TDA_UART3_AWR2_RXD
TDA_GPIO2_9_AWR2_RESETN
AWR2_WARM_RST TDA_GPIO2_12_AWR_WARM_RST
AWR2_SOP2 TDA_GPIO2_13_AWR_SOP2
AWR2_SOP1 TDA_GPIO2_25_AWR_SOP1
0
AWR2_SOP0
R5
0
TDA_GPIO2_22_AWR_SOP0
R6
0
R7
0
R8
10V
47uF
C2
GND
47uF
10V
C1
GND
SYSTEM_5V0
TDA_AWR1_GPIO0_GPIO4_18
TDA_AWR1_GPIO1_GPIO6_4
TDA_AWR1_GPIO2_GPIO6_5
TDA_AWR2_SPI_INT_GPIO5_10
TDA_AWR2_SPI_INT_GPIO5_10
AWR_EXT_DIG_SYNC
58
AWR_EXT_DIG_SYNC
TP191
TP1 92
AWR1_MSS_LOGGER
AWR1_BSS_LOGGER
AWR2_MSS_LOGGER
TP193
AWR2_BSS_LOGGER
TP194
DesignNote: TDA I2C3 interfaces
to primary AWR PMIC I2C port.
Design Note:FROM AWR devices
Design Note:TO AWR devices
Design Note:TO AWR devices
Design Note:FROM AWR devices
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Figure 7. DSP Host to RF Board Connector #1 (J1)
Table 1. DSP Host to RF Board Connector Pin Table (J1)
Host Board Connector 1 (J1) - Mated to RF Board P1
Pin Number Net Name Pin Type Function/Description
1 CONN_MON Passive Connector monitor
2 TP1 Passive Test Point
3 GND Power System ground return
4 NC None Unused
5 NC None Unused
6 GND Power System ground return
7 GND Power System ground return
8 NC None Unused
9 NC None Unused
10 GND Power System ground return
11 GND Power System ground return
12 AWR1_D3_P Input AWR #1 CSI2 TX3
13 AWR1_D3_N Input AWR #1 CSI2 TX3
14 GND Power System ground return
15 GND Power System ground return
16 AWR1_D2_P Input AWR #1 CSI2 TX2
17 AWR1_D2_N Input AWR #1 CSI2 TX2
18 GND Power System ground return
19 AWR1_CLK_P Input AWR #1 CSI2 Clock
20 AWR1_CLK_N Input AWR #1 CSI2 Clock
21 GND Power System ground return
22 TP4 Passive Test point
23 GND Power System ground return

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Table 1. DSP Host to RF Board Connector Pin Table (J1) (continued)
Host Board Connector 1 (J1) - Mated to RF Board P1
Pin Number Net Name Pin Type Function/Description
24 GND Power System ground return
25 AWR1_D1_P Input AWR #1 CSI2 TX1
26 AWR1_D1_N Input AWR #1 CSI2 TX1
27 GND Power System ground return
28 AWR1_D0_P Input AWR #1 CSI2 TX0
29 AWR1_D0_N Input AWR #1 CSI2 TX0
30 GND Power System ground return
31 GND Power System ground return
32 GND Power System ground return
33 NC Passive Unused
34 NC Passive Unused
35 GND Power System ground return
36 GND Power System ground return
37 NC Passive Unused
38 NC Passive Unused
39 GND Power System ground return
40 GND Power System ground return
41 AWR2_D3_P Input AWR #2 CSI2 TX3
42 AWR2_D3_N Input AWR #2 CSI2 TX3
43 GND Power System ground return
44 GND Power System ground return
45 AWR2_D2_P Input AWR #2 CSI2 TX2
46 AWR2_D2_N Input AWR #2 CSI2 TX2
47 GND Power System ground return
48 GND Power System ground return
49 AWR2_CLK_P Input AWR #2 CSI2 Clock
50 AWR2_CLK_N Input AWR #2 CSI2 Clock
51 GND Power System ground return
52 TP5 Passive
53 GND Power System ground return
54 GND Power System ground return
55 AWR2_D1_P Input AWR #2 CSI2 TX1
56 AWR2_D1_N Input AWR #2 CSI2 TX1
57 GND Power System ground return
58 AWR2_D0_P Input AWR #2 CSI2 TX0
59 AWR2_D0_N Input AWR #2 CSI2 TX0
60 GND Power System ground return
61 AWR1_GPIO2 Bidirectional AWR #1 GPIO2
62 AWR1_GPIO1 Bidirectional AWR #1 GPIO1
63 AWR1_GPIO0 Bidirectional AWR #1 GPIO0
64 TP_FSync Input Connected to EXT_DIG_SYNC fanout buffer on RF card
65 GND Power System ground return
66 SPI1_MISO Input AWR#1 SPI Slave MISO
67 AWR1_SPI_INT Input AWR#1 SPI Slave Interrupt
68 AWR1_CS0n Output AWR#1 SPI Slave CS0N
69 SPI1_MOSI Output AWR#1 SPI Slave MOSI