Texas Instruments MMWCAS-DSP-EVM User manual

1
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
User's Guide
SPRUIS6–September 2019
MMWCAS-DSP-EVM
The MMWCAS-DSP-EVM is an evaluation platform utilizing the TDA2x high performance, multimedia
application processor based on enhance OMAP architecture implemented with 28-nm technology. The
MMWCAS-RF-EVM is a 4-device, cascaded, array of AWR1243P mmWave devices. This user guide
references the MMWCAS-RF-EVM and Radar Board as the same items. Both boards together provide a
full Radar system evaluation.
Contents
1 Introduction ................................................................................................................... 2
2 Hardware Specifications .................................................................................................... 3
3 mmWave Studio and Matlab Post Processing ......................................................................... 19
List of Figures
1 Caution Hot Surface Warning located on EVM ......................................................................... 3
2 MMWCAS-DSP-EVM Functional Block Diagram ....................................................................... 4
3 MMWCAS-DSP-EVM - Front .............................................................................................. 5
4 MMWCAS-DSP-EVM – Back ............................................................................................. 6
5 MMWCAS-DSP-EVM (bottom) and MMWCAS-RF-EVM (top) Board Alignment ................................... 7
6 System Power Distribution Network ...................................................................................... 8
7 DSP Host to RF Board Connector #1 (J1) .............................................................................. 9
8 DSP Host to RF Board Connector #2 (J18) ........................................................................... 12
9 FPGA Flash Programming Header Pinout ............................................................................. 16
List of Tables
1 DSP Host to RF Board Connector Pin Table (J1) ...................................................................... 9
2 DSP Host to RF Board Connector Pin Table (J18) ................................................................... 12
3 USB Connector Pin Table (J16) ......................................................................................... 15
4 GPIO List and Description ................................................................................................ 17
5 User Configurable Supported Boot Modes ............................................................................. 18
6 Push Button Functionality Information .................................................................................. 18
7 User and Status LED Reference Designator and Description ....................................................... 18
Trademarks
MicroSD is a trademark of SD-3C, LLC.
All other trademarks are the property of their respective owners.

Introduction www.ti.com
2SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
1 Introduction
The MMWCAS-DSP-EVM is an evaluation platform utilizing the TDA2x high performance, multimedia
application processor based on enhance OMAP architecture implemented with 28-nm technology.
The MMWCAS-DSP-EVM provides a processing foundation for a cascaded imaging radar system.
Cascade radar devices can support front, long-range(LRR) beam-forming applications as well as corner
and side-cascade radar and sensor fusion platforms. The EVM supports SSD storage for longer term
capture scenarios and 1 Gigabit Ethernet connectivity for control and offloading captured data. The
MMWCAS-DSP-EVM may also be referred to as DSP Board throughout this guide.
The EVM interfaces with a companion Cascade Radar EVM (MMWCAS-RF-EVM). The MMWCAS-RF-
EVM is a 4-device, cascaded, array of AWR1243P mmWave devices. This user guide references the
MMWCAS-RF-EVM and Radar Board as the same items. Both boards together provide a full Radar
system evaluation.
1.1 Key Features
The key features of the MMWCAS-DSP-EVM are:
• TDA2SX ADAS SoC (23 mm × 23 mm)
• Four Lattice Crosslink Automotive Grade FPGAs
• 2GByte of DDR3L device
• PCIe 2.0 m.2 connector(m-keyed)
• MicroSD™ Card interface
• JTAG interface through FTDI FT2232HL Chip
• USB interface to provide UART, and I2C interfaces through the onboard FTDI device. This is used for
mmWave Studio.
• User LEDs, 3 push-button switches, and 1×6DIP switches for user BOOT configurations
• 1Gb/s RGMII Ethernet interface with RJ45 jack
• Video- one HDMI Out
• Two HiRose 120-pin Automotive Rated Board-to-Board connectors
• 12-V DC input (Wall supply not included in kit)
• Optimized Power Management IC (PMIC) Solution
• Dimension (L × W): 160 mm × 136 mm
• Expansion connector to support AWR Cascade Radar EVM

www.ti.com Introduction
3
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
1.2 Kit Contents
The following items are included with the MMWCAS-DSP-EVM kit. Unbox the board and identify various
components and connectors as detailed in the user guide.
• MMWCAS-DSP-EVM Board
• 512GB NVMe PCIE m.2 2280 SSD(assembled on EVM)
• 16GB microSD Card
• Ethernet cable
• Power Cable assembly
• USBA to miniB Cable
• Mounting standoffs and screws
1.3 Thermal Compliance
There is elevated heat on the processor/heatsink; use caution at elevated ambient temperature. Although
the processor/heatsink is not a burn hazard, caution should be used when handling the EVM due to
increased heat in the area of the heatsink.
Figure 1. Caution Hot Surface Warning located on EVM
2 Hardware Specifications
2.1 Functional Block Diagram
The functional block diagram of the MMWCAS-DSP-EVM is shown in Figure 2.

Micron MT41K512M16
x16 8Gbit
Micron MT41K512M16
x16 8Gbit
TDA2x Host Processor (ABC) 2x Micron MT41K512M16
16Gbit, 2x(64 Meg x 16 x 8 banks)
Micron MT41K512M8
4Gbit, 1x(64 Meg x 8 x 8 banks)
OS and Application Memory
2Gbyte Total
ECC Memory
512Mbyte Total
VIN1A Lattice LIF MD6000 CrossFire
FPGA #1
CSI2.0 to VIN Bridge
VIN2A Lattice LIF MD6000 CrossFire
FPGA #2
CSI2.0 to VIN Bridge
VIN3A Lattice LIF MD6000 CrossFire
FPGA #3
CSI2.0 to VIN Bridge
VIN4A Lattice LIF MD6000 CrossFire
FPGA #4
CSI2.0 to VIN Bridge
DDR3-1066
32-Bit+ECC
EMIF1
DDR3-1066
32-Bit
EMIF2
2x Micron MT41K512M16
16Gbit (64 Meg x 16 x 8 banks)
OS and Application Memory
2Gbyte Total
Hirose FX23-120S-
0.5SV10
AWR1243 RF Board
Connectors
CSI2.0
AWR#1
CSI2.0
AWR#2
CSI2.0
AWR#3
CSI2.0
AWR#3
UART3 1:4 MUX
UART AWR#1
UART AWR#2
UART AWR#3
UART AWR#4
SPI1
SPI3
SPI AWR#1/4
SPI AWR#2/3
GPIO SOP
ERROR
UART
USB Bridge
USB2.0
Mini
Connector
UART1
USB3.0
Device
Connector
USB3.0
Super-Speed
(5Gbps)
EMU Port/VOUT
60-Pin MIPI
Debug Header
EMU
DP83867IRPAPR
1G Ethernet PHY RGMII
RJ-45
Magnetics
Micron MT25QL01GBBB8ESF
QSPI Flash, 133MHz, 1Gbit
(128M x 8)
QSPI
HDMI
Type-A
Connector
HDMI1.4a
PCIe m.2
Host Connector
PCIe 2.0
5Gbps
MicroSD Card
Connector MMC1
GPIO AWR_RESETS
2:1 MUX
VOUT 10GigE
Header VOUT
JTAG
Hardware Specifications www.ti.com
4SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Figure 2. MMWCAS-DSP-EVM Functional Block Diagram

www.ti.com Hardware Specifications
5
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
2.2 Board Dimensions & Description
The MMWCAS-DSP-EVM dimensions are 160 mm × 136 mm. It is a 22-layer board fabricated with epoxy
fiberglass (UL94V-0 Certified). Figure 3 and Figure 4 show the top and bottom layers with key
components identified.
Figure 3. MMWCAS-DSP-EVM - Front

MicroSD
Recepticle
MicroSD
Recepticle
Cascade RF board connector
Cascade RF board connector
Cascade RF board connector
Cascade RF board connector
PCIe m.2 SSD
connector and
screw hole
Hardware Specifications www.ti.com
6SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Figure 4. MMWCAS-DSP-EVM – Back

www.ti.com Hardware Specifications
7
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
2.3 Attaching MMWCAS-DSP-EVM to MMWCAS-RF-EVM
The MMWCAS-DSP-EVM is designed to have a companion RF board attached to capture radar data. The
EVM provides 5-V power and necessary control to the RF board upon connecting.
The boards align and attach through the board to board connectors (J1 and J18) on the EVM. The
connectors are keyed to prevent incorrect, 180 degree, opposite orientation. The four corner mounting
holes align the boards as well to outline the match. Depressing the RF board connectors into the EVM
connectors connects the boards together. Use the included standoffs to secure a single assembly of the
boards. Refer to Figure 5 for reference.
Figure 5. MMWCAS-DSP-EVM (bottom) and MMWCAS-RF-EVM (top) Board Alignment
2.4 Power
The MMWCAS-DSP-EVM is powered by 12-V power, either from a DC barrel connector (J10) or screw
terminal (J11). A wall DC power source or a bench power source can be used to power the EVM. The
power source should be rated at least 3 A. The typical power source is 12-V, 5-A Advantech Power supply
P/N: 96PSA-A60W12V1-1.
When power is provided, various LEDs around the edge of the board light up, indicating the proper
interfaces have the adequate power. Refer to the block diagram to see location of key status LEDs.
The companion power management IC (PMIC) for the SOC is TPS659039EP-Q1. A step-down 12-V to
3.3-V and 5-V converter is available in order to provide a 3.3-V and 5-V DC input to the PMIC as well as
3.3-V and 5-V power rails at the board level. Figure 6 shows the complete power supply tree.

CUI PJ-002AH DC
Power Jack
x 12V, 5A DC
Supply Input
x System 5.0V Supply
x System 3.3V Suppy
TPS43351QDAPRQ1
Switcher Controller
x TDA2 SoC LDO and SMPS
Supply
x Supplies all Core and Peripheral
Power for entire TDA2 SoC
TPS659039-Q1
(O9039A387IZWSRQ1) PMIC
x Ethernet PHY 1.1V
x Ethernet PHY 2.5V
x DDR3 SDRAM 1.35V Supply
x TDA2 DDR3 Controller 1.35
Supply
x DDR3 SDRAM VTT/VREF
Supply
TPS74801-Q1 LDO
TPS74801-Q1 LDO
TPS57112-Q1 2A, 2-MHz,
Synchronous Step-Down
TPS51200QDRCRQ1
Push-Pull VTT Regulator
Quad AWR1243 RF Board Connector
x 5V, 4A Load Expected
12V
5.0V
3.3V
LP5907QMFX-2.5Q1 LDO
x FPGA 2.5V
TPS62262TDRVRQ1 LDO
x FPGA 1.2V
Hardware Specifications www.ti.com
8SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Figure 6. System Power Distribution Network
2.5 Connectors
2.5.1 RF Board Connectors (J1, J18)
The primary board to board connectors on the EVM (J1 and J18) are used to connect the board to
MMWCAS-RF-EVM. These connectors are each implemented with a Hirose FX23-120S-0.5SV10
receptacle. J1 contains all the reset, boot, digital control, and CSI2.0 data paths for AWR1243P #1 and
AWR1243P #2. J18 contains the same but for AWR1243P #3 and AWR1243P #4. Both connectors share
common 5-V and GND return paths.

Mates to AWR RF Board P1
AWR1_CSI
58
FPGA1_DPHY0_CLK_P
FPGA1_DPHY0_CLK_N
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N
AWR1_CS I
AWR2_CSI
58
FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N
AWR2_CS I
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N
FPGA1_DPHY0_CLK_P
58
I2C3
FPGA1_DPHY0_CLK_N
TDA_I2C3_SCL
TDA_I2C 3_SD A
TDA_I2C3_SCL
I2C3
TDA_I2C3_SDA
58
UART_AWR1
58
UART_AWR2
TDA_UART1_TXD
TDA_UART1_RXD
UART_AWR1
TDA_UART2_TXD
TDA_UART2_RXD
UART_AWR2
58
AWR_SOP0
58
AWR_SOP1
58
AWR_SOP2
58
AWR_WARM_RST
58
AWR1_RESETN
58
AWR2_RESETN
TDA_UART3_AWR1_RXD
TDA_UART3_AWR1_TXD
TDA_UART3_AWR2_TXD
TDA_UART3_AWR2_RXD
AWR_ERROR_OUTN
58
AWR2_SPI_SCLK
AWR2_SPI_CS0N
AWR2_SPI_MOSI
AWR2_SPI_MISO
AWR1_SPI_CS0N
AWR1_SPI_MOSI
AWR1_SPI_MISO
AWR1_SPI_SCLK
58
AWR1_SPI_SCLK
58
AWR1_SPI_CS0N
58
AWR1_SPI_MOSI
58
AWR1_SPI_MISO
58
AWR2_SPI_SCLK
58
AWR2_SPI_CS0N
58
AWR2_SPI_MOSI
58
AWR2_SPI_MISO
Net Class i
ClassName:AWR1_SPI
Net Class i
ClassName:AWR2_SPI
58
AWR1_SPI_INT
58
AWR2_SPI_INT
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N
FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
TDA_GPIO2_2_AWR1_RESETN
TDA_GPIO2_9_AWR2_RESETN
TDA_GPIO7_24_AWR1_SPI_INT
TDA_GPIO2_19_AWR_ERROR_OUTN
TDA_GPIO2_22_AWR_SOP0
TDA_GPIO2_25_AWR_SOP1
TDA_GPIO2_13_AWR_SOP2
TDA_GPIO2_12_AWR_WARM_RST
P1 P3
MH1 MH3
P2 P4
MH2 MH4
1
10
11
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J1
GND
Hirose_FX23-120S-0_5SV10
GND
AWR_CONN1_MON
AWR_ CONN_TP1
TP1
AWR_CONN_TP2
TP4
TP5
AWR_CONN_TP3
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N
FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N
FPGA1_DPHY0_CLK_P
FPGA1_DPHY0_CLK_N
58
TDA_AWR1_GPIO2
58
TDA_AWR1_GPIO1
58
TDA_AWR1_GPIO0
AWR_EXT_DIG_SYNC
AWR_CONN1_MON
AWR1_SPI_MISO
AWR1_SPI_CS0N
TDA_GPIO7_24_AWR1_SPI_INT
AWR1_SPI_MOSI
AWR1_SPI_SCLK
TDA_I2C3_SCL
TDA_I2C3_SDA
TP3
AWR_CONN_TP5
TDA_GPIO2_19_AWR_ERROR_OUTN
TDA_UART3_AWR1_TXD
TDA_UART3_AWR1_RXD
AWR1_SOP2
0
R1
TDA_GPIO2_13_AWR_SOP2
AWR1_SOP1
0
R2
TDA_GPIO2_25_AWR_SOP1
AWR1_SOP0
0
R3
TDA_GPIO2_22_AWR_SOP0
0
R4
TDA_GPIO2_2_AWR1_RESETN
AWR1_WARM_RST TDA_GPIO2_12_AWR_WARM_RST
AWR2_SPI_MISO
AWR2_SPI_CS0N
AWR2_SPI_MOSI
AWR2_SPI_SCLK
TDA_UART3_AWR2_TXD
TDA_UART3_AWR2_RXD
TDA_GPIO2_9_AWR2_RESETN
AWR2_WARM_RST TDA_GPIO2_12_AWR_WARM_RST
AWR2_SOP2 TDA_GPIO2_13_AWR_SOP2
AWR2_SOP1 TDA_GPIO2_25_AWR_SOP1
0
AWR2_SOP0
R5
0
TDA_GPIO2_22_AWR_SOP0
R6
0
R7
0
R8
10V
47uF
C2
GND
47uF
10V
C1
GND
SYSTEM_5V0
TDA_AWR1_GPIO0_GPIO4_18
TDA_AWR1_GPIO1_GPIO6_4
TDA_AWR1_GPIO2_GPIO6_5
TDA_AWR2_SPI_INT_GPIO5_10
TDA_AWR2_SPI_INT_GPIO5_10
AWR_EXT_DIG_SYNC
58
AWR_EXT_DIG_SYNC
TP191
TP1 92
AWR1_MSS_LOGGER
AWR1_BSS_LOGGER
AWR2_MSS_LOGGER
TP193
AWR2_BSS_LOGGER
TP194
DesignNote: TDA I2C3 interfaces
to primary AWR PMIC I2C port.
Design Note:FROM AWR devices
Design Note:TO AWR devices
Design Note:TO AWR devices
Design Note:FROM AWR devices
www.ti.com Hardware Specifications
9
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Figure 7. DSP Host to RF Board Connector #1 (J1)
Table 1. DSP Host to RF Board Connector Pin Table (J1)
Host Board Connector 1 (J1) - Mated to RF Board P1
Pin Number Net Name Pin Type Function/Description
1 CONN_MON Passive Connector monitor
2 TP1 Passive Test Point
3 GND Power System ground return
4 NC None Unused
5 NC None Unused
6 GND Power System ground return
7 GND Power System ground return
8 NC None Unused
9 NC None Unused
10 GND Power System ground return
11 GND Power System ground return
12 AWR1_D3_P Input AWR #1 CSI2 TX3
13 AWR1_D3_N Input AWR #1 CSI2 TX3
14 GND Power System ground return
15 GND Power System ground return
16 AWR1_D2_P Input AWR #1 CSI2 TX2
17 AWR1_D2_N Input AWR #1 CSI2 TX2
18 GND Power System ground return
19 AWR1_CLK_P Input AWR #1 CSI2 Clock
20 AWR1_CLK_N Input AWR #1 CSI2 Clock
21 GND Power System ground return
22 TP4 Passive Test point
23 GND Power System ground return

Hardware Specifications www.ti.com
10 SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 1. DSP Host to RF Board Connector Pin Table (J1) (continued)
Host Board Connector 1 (J1) - Mated to RF Board P1
Pin Number Net Name Pin Type Function/Description
24 GND Power System ground return
25 AWR1_D1_P Input AWR #1 CSI2 TX1
26 AWR1_D1_N Input AWR #1 CSI2 TX1
27 GND Power System ground return
28 AWR1_D0_P Input AWR #1 CSI2 TX0
29 AWR1_D0_N Input AWR #1 CSI2 TX0
30 GND Power System ground return
31 GND Power System ground return
32 GND Power System ground return
33 NC Passive Unused
34 NC Passive Unused
35 GND Power System ground return
36 GND Power System ground return
37 NC Passive Unused
38 NC Passive Unused
39 GND Power System ground return
40 GND Power System ground return
41 AWR2_D3_P Input AWR #2 CSI2 TX3
42 AWR2_D3_N Input AWR #2 CSI2 TX3
43 GND Power System ground return
44 GND Power System ground return
45 AWR2_D2_P Input AWR #2 CSI2 TX2
46 AWR2_D2_N Input AWR #2 CSI2 TX2
47 GND Power System ground return
48 GND Power System ground return
49 AWR2_CLK_P Input AWR #2 CSI2 Clock
50 AWR2_CLK_N Input AWR #2 CSI2 Clock
51 GND Power System ground return
52 TP5 Passive
53 GND Power System ground return
54 GND Power System ground return
55 AWR2_D1_P Input AWR #2 CSI2 TX1
56 AWR2_D1_N Input AWR #2 CSI2 TX1
57 GND Power System ground return
58 AWR2_D0_P Input AWR #2 CSI2 TX0
59 AWR2_D0_N Input AWR #2 CSI2 TX0
60 GND Power System ground return
61 AWR1_GPIO2 Bidirectional AWR #1 GPIO2
62 AWR1_GPIO1 Bidirectional AWR #1 GPIO1
63 AWR1_GPIO0 Bidirectional AWR #1 GPIO0
64 TP_FSync Input Connected to EXT_DIG_SYNC fanout buffer on RF card
65 GND Power System ground return
66 SPI1_MISO Input AWR#1 SPI Slave MISO
67 AWR1_SPI_INT Input AWR#1 SPI Slave Interrupt
68 AWR1_CS0n Output AWR#1 SPI Slave CS0N
69 SPI1_MOSI Output AWR#1 SPI Slave MOSI

www.ti.com Hardware Specifications
11
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 1. DSP Host to RF Board Connector Pin Table (J1) (continued)
Host Board Connector 1 (J1) - Mated to RF Board P1
Pin Number Net Name Pin Type Function/Description
70 SPI1_SCLK Output AWR#1 SPI Slave SCLK
71 GND Power System ground return
72 I2C3_SCL Output E_PMIC_SCL - Primary LP87524-Q1 PMIC I2C
73 I2C3_SDA Bidirectional E_PMIC_SDA - Primary LP87524-Q1 PMIC I2C
74 TP3 Output EXT_40MHZ_CLK_1V8
75 ERROR_OUTn Input Open-Drain OR'd ERROR_OUT from AWR#1, 2, 3 and 4
76 GND Power System ground return
77 AWR1_UART_TxD Output AWR#1 UART RX - TDA2x TX to AWR RX
78 AWR1_UART_RxD Output AWR#1 UART TX - AWR TX to TDA2x RX
79 TP191 Passive
80 TP192 Passive
81 GND Power System ground return
82 AWR_SOP_PMICCLKOUT Output AWR#1 PMICCLKOUT/SOP2
83 AWR_SOP_SYNCOUT Output AWR#1 SYNCOUT/SOP1 signal
84 AWR_SOP_TDO Output AWR#1 TDO/SOP0 signal
85 AWR1_RESETn Output AWR#1 NRESET signal
86 AWR_WARM_RST Output AWR#1 WARM_RESET signal
87 GND Power System ground return
88 NC Passive
89 NC Passive
90 NC Passive
91 NC Passive
92 GND Power System ground return
93 SPI3_MISO Input AWR#2 SPI Slave MISO
94 AWR2_SPI_INT AWR#2 SPI Slave Interrupt
95 GND Power System ground return
96 AWR2_CS0n Output AWR#2 SPI Slave CS0N
97 SPI3_MOSI Output AWR#2 SPI Slave MOSI
98 SPI3_SCLK Output AWR#2 SPI Slave SCLK
99 GND Power System ground return
100 AWR2_UART_TxD Output AWR#2 UART RX - TDA2x TX to AWR RX
101 AWR2_UART_RxD Input AWR#2 UART TX - AWR TX to TDA2x RX
102 TP192 Passive
103 TP194 Passive
104 GND Power System ground return
105 NC Passive
106 NC Passive
107 NC Passive
108 GND Power System ground return
109 AWR2_RESETn Output AWR#2 NRESET signal
110 AWR_WARM_RST Output AWR#2 WARM_RESET signal
111 GND Power System ground return
112 AWR_SOP_PMICCLKOUT Output AWR#2 PMICCLKOUT/SOP2
113 AWR_SOP_SYNCOUT Output AWR#2 SYNCOUT/SOP1 signal
114 AWR_SOP_TDO Output AWR#2 TDO/SOP0 signal
115 GND Power System ground return

AWR3_CSI
58
AWR4_CSI
58
FPGA3_DPHY0_CLK_P
FPGA3_DPHY0_CLK _N
FPGA3_DPHY0_D0_P
FPGA3_DPHY0_D0_N
FPGA3_DPHY0_D1_P
FPGA3_DPHY0_D1_N
FPGA3_DPHY0_D2_P
FPGA3_DPHY0_D2_N
FPGA3_DPHY0_D3_P
FPGA3_DPHY0_D3_N
AWR3_CS I
FPGA4_DPHY0_CLK _P
FPGA4_DPHY0_CLK _N
FPGA4_DPHY0_D0_P
FPGA4_DPHY0_D0_N
FPGA4_DPHY0_D1_P
FPGA4_DPHY0_D1_N
FPGA4_DPHY0_D2_P
FPGA4_DPHY0_D2_N
FPGA4_DPHY0_D3_P
FPGA4_DPHY0_D3_N
AWR4_CS I
58
I2C5
TDA_I2C5_SCL
I2C5
TDA_I2C5_SDA
58
UART_AWR3
58
UART_AWR4
TDA_UART3_AWR3_TXD
TDA_UART3_TXD
TDA_UART3_RXD
UART_AWR3
TDA_UART4_TXD
TDA_UART4_RXD
UART_AWR4
TDA_UART3_AWR4_TXD
TDA_UART3_AWR3_RXD
TDA_UART3_AWR4_RXD
58
AWR_PMIC_3V3_VD
58
AWR_SOP0
58
AWR_SOP1
58
AWR_SOP2
58
AWR_WARM_RST
58
AWR3_RESETN
58
AWR4_RESETN
Net Class i
Net Class i
ClassName: AWR3_CSI
ClassName: AWR4_CSI
TDA_I2C5_SCL
TDA_I2C5_SDA
AWR4_SPI_SCLK
AWR4_SPI_CS0N
AWR4_SPI_MOSI
AWR4_SPI_MISO
AWR3_SPI_CS0N
AWR3_SPI_MOSI
AWR3_SPI_MISO
AWR3_SPI_ SCLK
58
AWR3_SPI_SCLK
58
AWR3_SPI_CS0N
58
AWR3_SPI_MOSI
58
AWR3_SPI_MISO
58
AWR4_SPI_SCLK
58
AWR4_SPI_CS0N
58
AWR4_SPI_MOSI
58
AWR4_SPI_MISO
Net Class i
Net Class i
ClassName: AWR3_SPI
ClassName: AWR4_SPI
58
AWR3_SPI_INT
58
AWR4_SPI_INT
FPGA3_DPHY0_CLK_P
FPGA3_DPHY0_CLK_N
FPGA3_DPHY0_D0_P
FPGA3_DPHY0_D0_N
FPGA3_DPHY0_D1_P
FPGA3_DPHY0_D1_N
FPGA3_DPHY0_D2_P
FPGA3_DPHY0_D2_N
FPGA3_DPHY0_D3_P
FPGA3_DPHY0_D3_N
FPGA4_DPHY0_CLK_P
FPGA4_DPHY0_CLK_N
FPGA4_DPHY0_D0_P
FPGA4_DPHY0_D0_N
FPGA4_DPHY0_D1_P
FPGA4_DPHY0_D1_N
FPGA4_DPHY0_D2_P
FPGA4_DPHY0_D2_N
FPGA4_DPHY0_D3_P
FPGA4_DPHY0_D3_N
TDA_GPIO2_10_AWR3_RESETN
TDA_GPIO2_11_AWR4_RESETN
TDA_GPIO7_25_AWR4_SPI_INT
AWR_POWER_GOOD_TDA_GPIO2_17
TDA_GPIO2_22_AWR_SOP0
TDA_GPIO2_25_AWR_SOP1
TDA_GPIO2_13_AWR_SOP2
TDA_GPIO2_12_AWR_WARM_RST
P1 P3
MH1 MH3
P2 P4
MH2 MH4
1
10
11
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
J18
Mates to AWR RF Board P2
Hirose_FX23-120S-0_5SV10
0
TP185
R309
TDA_I2C5_SDA
TDA_I2C5_SCL
AWR_CONN_TP6
AWR_CONN2_MON
AWR4_SPI_SCLK
AWR4_SPI_MOSI
AWR4_SPI_CS0N
AWR4_SPI_MISO
AWR3_WARM_RST
AWR3_SOP0
AWR3_SOP1
AWR3_SOP2
AWR3_SPI_SCLK
AWR3_SPI_MOSI
AWR3_SPI_CS0N
AWR3_SPI_MISO
AWR4_SOP2
AWR4_SOP0
AWR4_SOP1
AWR4_WARM_RST
TDA_UART3_AWR4_RXD
TDA_UART3_AWR4_TXD
TDA_UART3_AWR3_RXD
TDA_UART3_AWR3_TXD
TDA_GPIO7_25_AWR4_SPI_INT
TDA_GPIO2_22_AWR_SOP0
TDA_GPIO2_25_AWR_SOP1
TDA_GPIO2_13_AWR_SOP2
TDA_GPIO2_22_AWR_SOP0
TDA_GPIO2_25_AWR_SOP1
TDA_GPIO2_13_AWR_SOP2
TDA_GPIO2_10_AWR3_RESETN
TDA_GPIO2_11_AWR4_RESETN
TDA_GPIO2_12_AWR_WARM_RST
GND GND
TDA_GPIO2_12_AWR_WARM_RST
AWR_CONN2_MON
AWR_POWER_GOOD_TDA_GPIO2_17
FPGA3_DPHY0_D3_P
FPGA3_DPHY0_D3_N
FPGA3_DPHY0_D2_P
FPGA3_DPHY0_D2_N
FPGA3_DPHY0_CLK_P
FPGA3_DPHY0_CLK_N
AWR_CONN_TP8
TP184
FPGA3_DPHY0_D1_P
FPGA3_DPHY0_D1_N
FPGA3_DPHY0_D0_P
FPGA3_DPHY0_D0_N
FPGA4_DPHY0_D3_P
FPGA4_DPHY0_D3_N
FPGA4_DPHY0_D2_P
FPGA4_DPHY0_D2_N
FPGA4_DPHY0_CLK_P
FPGA4_DPHY0_CLK_N
AWR_CONN_TP7
TP183
FPGA4_DPHY0_D1_P
FPGA4_DPHY0_D1_N
FPGA4_DPHY0_D0_P
0
R441
0
FPGA4_DPHY0_D0_N
R442
0
0
R443
0
R444
R445
0
0
R446
R447
TDA_AWR3_SPI_INT_GPIO5_11
10V
47uF
C625
TDA_AWR3_SPI_INT_GPIO5_11
GND
47uF
10V
C624
GND
SYSTEM_5V0
AWR4_BSS_LOGGER
AWR4_MSS_LOGGER
AWR3_BSS_LOGGER
TP195
AWR3_MSS_LOGGER
TP196
TP1 97
TP1 98
Design Note:FROM AWR devices
Design Note:TDAI2C5 interfaces to secondary
AWR PMIC I2C port and RF board temperature
sensors.
DesignNote: TO AWR devices
Des ign Note: The AWR RF boa rd provides the
3.3V I/O PMIC 3.3V as a "power good"signal.
Hardware Specifications www.ti.com
12 SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 1. DSP Host to RF Board Connector Pin Table (J1) (continued)
Host Board Connector 1 (J1) - Mated to RF Board P1
Pin Number Net Name Pin Type Function/Description
116 NC Passive
117 NC Passive
118 NC Passive
119 NC Passive
120 CONN_MON Passive Connector connection monitor - unused
121 GND Power System ground return
122 GND Power System ground return
123 EVM_5V0 Power
124 EVM_5V0 Power
125 GND Power System ground return
126 GND Power System ground return
127 GND Power System ground return
128 GND Power System ground return
Figure 8. DSP Host to RF Board Connector #2 (J18)
Table 2. DSP Host to RF Board Connector Pin Table (J18)
Host Board Connector 1(J18) - Mated to RF Board P2
Pin Number Net Name Pin Type Function/Description
1 CONN2_MON Passive Connection Monitor
2 NC Passive
3 NC Passive
4 NC Passive
5 NC Passive
6 GND Power System ground return

www.ti.com Hardware Specifications
13
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 2. DSP Host to RF Board Connector Pin Table (J18) (continued)
Host Board Connector 1(J18) - Mated to RF Board P2
Pin Number Net Name Pin Type Function/Description
7 AWR_SOP_TDO Output AWR#4 TDO/SOP0 signal
8 AWR_SOP_SYNCOUT Output AWR#4 SYNCOUT/SOP1 signal
9 AWR_SOP_PMICCLKOUT Output AWR#4 PMICCLKOUT/SOP2
10 GND Power System ground return
11 AWR_WARM_RST Output AWR#4 WARM_RESET signal
12 AWR4_RESETn Output AWR#4 NRESET signal
13 GND Power System ground return
14 NC Passive
15 NC Passive
16 NC Passive
17 GND Power System ground return
18 NC Passive Test Point 195
19 NC Passive Test Point 196
20 AWR4_UART_RxD Input AWR4_UART_TxD-AWR TX to TDA2x RX
21 AWR4_UART_TxD Output AWR4_UART_RxD-AWR TX to TDA2x RX
22 GND Power System ground return
23 SPI1_SCLK Output AWR#4 SPI Slave SCLK
24 SPI1_MOSI Output AWR#4 SPI Slave MOSI
25 AWR4_CS1n Output AWR#4 SPI Slave SCLK
26 GND Power System ground return
27 AWR4_SPI_INT Input AWR#4 SPI Slave Interrupt
28 SPI1_MISO Input AWR#4 SPI Slave MISO
29 GND Power System ground return
30 NC Passive
31 NC Passive
32 NC Passive
33 NC Passive
34 GND Power System ground return
35 AWR_WARM_RST Output AWR#3 WARM_RESET signal
36 AWR3_RESETn Output AWR#3 NRESET signal
37 AWR_SOP_TDO Output AWR#3 TDO/SOP0 signal
38 AWR_SOP_SYNCOUT Output AWR#3 SYNCOUT/SOP1 signal
39 AWR_SOP_PMICCLKOUT Output AWR#3 PMICCLKOUT/SOP2
40 GND Power System ground return
41 NC Passive Test Point 197
42 NC Passive Test Point 198
43 AWR3_UART_TxD Input AWR3_UART_RxD-AWR TX to TDA2x RX
44 AWR3_UART_RxD Output AWR3_UART_TxD-AWR TX to TDA2x RX
45 GND Power System ground return
46 NC Passive
47 NC Passive
48 I2C5_SDA Bidirectional E_PMIC_SDA - Primary LP87524-Q1 PMIC I2C
49 I2C5_SCL Output E_PMIC_SCL - Primary LP87524-Q1 PMIC I2C
50 GND Power System ground return
51 SPI3_SCLK Output AWR#3 SPI Slave SCLK
52 SPI3_MOSI Output AWR#3 SPI Slave MOSI

Hardware Specifications www.ti.com
14 SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 2. DSP Host to RF Board Connector Pin Table (J18) (continued)
Host Board Connector 1(J18) - Mated to RF Board P2
Pin Number Net Name Pin Type Function/Description
53 AWR3_CS1n Output AWR#3 SPI Slave SCLK
54 AWR3_SPI_INT Input AWR#3 SPI Slave Interrupt
55 SPI3_MISO Input AWR#3 SPI Slave MISO
56 GND Power
57 TP_tmp_al Input Test Point 185
58 NC Passive
59 NC Passive
60 NC Passive
61 GND Power System ground return
62 AWR4_D0_N Input AWR #4 CSI2 TX0
63 AWR4_D0_P Input AWR #4 CSI2 TX0
64 GND Power System ground return
65 AWR4_D1_N Input AWR #4 CSI2 TX1
66 AWR4_D1_P Input AWR #4 CSI2 TX1
67 GND Power System ground return
68 GND Power System ground return
69 TP_SP1 Passive Test Point 183
70 GND Power System ground return
71 AWR4_CLK_N Input AWR #4 CSI2 Clock
72 AWR4_CLK_P Input AWR #4 CSI2 Clock
73 GND Power System ground return
74 GND Power System ground return
75 AWR4_D2_N Input AWR #4 CSI2 TX2
76 AWR4_D2_P Input AWR #4 CSI2 TX2
77 GND Power System ground return
78 GND Power System ground return
79 AWR4_D3_N Input AWR #4 CSI2 TX3
80 AWR4_D3_P Input AWR #4 CSI2 TX3
81 GND Power System ground return
82 GND Power System ground return
83 NC Passive
84 NC Passive
85 GND Power System ground return
86 GND Power System ground return
87 NC Passive
88 NC Passive
89 GND Power System ground return
90 GND Power System ground return
91 GND Power System ground return
92 AWR3_D0_N Input AWR #3 CSI2 TX0
93 AWR3_D0_P Input AWR #3 CSI2 TX0
94 GND Power System ground return
95 AWR3_D1_N Input AWR #3 CSI2 TX1
96 AWR3_D1_P Input AWR #3 CSI2 TX1
97 GND Power System ground return
98 GND Power System ground return

www.ti.com Hardware Specifications
15
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 2. DSP Host to RF Board Connector Pin Table (J18) (continued)
Host Board Connector 1(J18) - Mated to RF Board P2
Pin Number Net Name Pin Type Function/Description
99 TP_SP2 Passive Test Point 184
100 GND Power System ground return
101 AWR3_CLK_N Input AWR #3 CSI2 Clock
102 AWR3_CLK_P Input AWR #3 CSI2 Clock
103 GND Power System ground return
104 AWR3_D2_N Input AWR #3 CSI2 TX2
105 AWR3_D2_P Input AWR #3 CSI2 TX2
106 GND Power System ground return
107 GND Power System ground return
108 AWR3_D3_N Input AWR #3 CSI2 TX3
109 AWR3_D3_P Input AWR #3 CSI2 TX3
110 GND Power System ground return
111 GND Power System ground return
112 NC Passive
113 NC Passive
114 GND Power System ground return
115 GND Power System ground return
116 NC Passive
117 NC Passive
118 GND Power
119 PWR_GOOD Input Power good from RF
120 CONN2_MON Passive Connector connection monitor - unused
121 EVM_5V0 Power
122 EVM_5V0 Power
123 GND Power System ground return
124 GND Power System ground return
125 GND Power System ground return
126 GND Power System ground return
127 GND Power System ground return
128 GND Power System ground return
2.5.2 USB Connector (J16)
The MMWCAS-DSP-EVM has one USB2.0 mini connector. Connector J16 allows access to the EVM
through UART, SPI, or I2C through the FTDI chip.
Table 3 provides the J16 connector pin information.
Table 3. USB Connector Pin Table (J16)
Pin No Signal Name Description
1 FTDI_USB_VBUS_5V0 5-V power from PC machine
2 FTDI_USB_D_CONN_N USB Data Signal Negative
3 FTDI_USB_D_CONN_P USB Data Signal Positive
4 No Connect No Connect
5 GND Ground

Power
Supplies
97531
10 8 6 4 2
FPGA1_SPI_MOSI
FPGA1_SPI_SCLK
FPGA1_FLASH_SPI_CSN
FPGA1_SPI_CSN (not used)
FPGA1_VCCIO
GND (not used)
FPGA1_CDONE (not used)
FPGA1_CRESETN
FPGA1_SPI_MISO
GND
Cascade Radar Host Board
FPGA Programming Header
Top-Down View. Reference
layout/assembly drawing for pin
orientation/positions.
VCC
ispEN/PROG
TCK/SCLK
TDI/SI
TRST
TDO/SO
GND
Lattice HW-USBN-2B
Programming Cable
Leads
Cascade Radar Host Board to
FPGA Programmer Hookup
For FPGA Flash Programming
DONE
Hardware Specifications www.ti.com
16 SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
2.5.3 Ethernet Jack (J12)
The MMWCAS-DSP-EVM supports a Gigabit Ethernet port to provide the connection to the network. The
Ethernet port is interfaced to the TDA2 through the Ethernet PHY DP83867, and is used to stream the
captured data over the network to the host PC.
The DP83867 device is a robust, low power, fully featured physical layer transceiver with integrated PMD
sublayers to support 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols. Optimized for ESD
protection, the DP83867 exceeds 8-kV IEC 61000-4-2(direct contact)
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It
has low latency and provides IEEE 1588 Start of Frame Detection.
2.5.4 PCIe m.2 socket(m-keyed) (J14)
The DSP EVM supports PCIe 2.0 through an m.2 connector. Out of the box, a 512 GB SSD is assembled
on the EVM. The connector is a JAE Electronics SM3ZS067U410AMR1000 PCI express m.2 connector.
The SSD drive provides 3.3 V through the connector, and the data lanes have been length and
impedance matched through the PCIE spec document. The EVM has a notch with a small standoff that
allows a size 2280 SSD card to be securely attached with the provided machine screw. The
recommended SSD is a single-sided card, but a double-sided card can be used if the SSD components do
not touch the board components, due to height.
2.5.5 Lattice FPGA Headers (J3,J5,J7,J9)
The EVM contains four programming headers for the on board FPGA and flash devices. Out of the box,
the FPGAs are flashed so they are ready to use. If the FPGAs must be flashed, refer to Figure 9 for
proper cable assembly. Lattice Diamond 3.10 (not included) and Lattice HW-USBN-2B Programmer (not
included) must be used. Along with each FPGA, there is a small NOR flash device used to hold the image
on power cycle.
Figure 9. FPGA Flash Programming Header Pinout

www.ti.com Hardware Specifications
17
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
2.5.6 JTAG and Emulator (J19)
The EVM has support of the following JTAG emulation headers:
• 60-pin MIPI Connector
• Standard 14-pin to 60-pin MIPI adapter
• 20-pin CTI to 60-pin MIPI adapter
2.5.7 Lattice ECP5 FPGA Prototyping Header (J20)
Included on the EVM is a Lattice Prototyping connector. The interface brings out the VOUT1 interface,
I2C5, and two I2C GPIO expander pins to allow for interfacing to a separate Lattice ECP5 FPGA card,
which performs VOUT to 10GBase-KR bridging.
2.6 GPIO, Switches, Push Buttons, and LEDs
2.6.1 GPIO List
The MMWCAS-DSP-EVM supports a number of GPIOs, some of which can be user controlled. Table 4
shows the GPIO list.
Table 4. GPIO List and Description
GPIO for EVM Function/Description
TDA_GPIO1_15_ALERT# PCIe SSD Alert notification to master. Active Low. Open-Drain with pullup on board. '0' -
Active '1' - Inactive(Default)
GPIO_EXP_P13(PERST#) PCIe Reset - functional reset to the card '0' - Hold in reset until stable(Default) '1' - Release
from reset
GPIO_EXP_P14(CLKREQ#) PCIe Reference Clock Request '0' - Request for clock '1' - Not Active(Default)
GPIO6_8 Selects between AWR and FPGA/Flash for SPI1 '0' - Selects AWR(Default) '1' - Selects
FPGA/Flash
GPIO6_6 When ganged. Controls FPGA1/2/3/4 CRESETN signals '0' - Holds FPGA in Reset(Default)
'1' - released FPGA from Reset
GPIO7_31 Controls FPGA1 CRESETN signals '0' - Holds FPGA1 in Reset(Default) '1' - released
FPGA1 from Reset
GPIO7_30 Controls FPGA2 CRESETN signals '0' - Holds FPGA2 in Reset(Default) '1' - released
FPGA2 from Reset
GPIO5_13 Controls FPGA3 CRESETN signals '0' - Holds FPGA3 in Reset(Default) '1' - released
FPGA3 from Reset
GPIO5_14 Controls FPGA4 CRESETN signals '0' - Holds FPGA4 in Reset(Default) '1' - released
FPGA4 from Reset
GPIO1_14 Control FPGA1/2/3/4 Flash RESETn Signals '0' - Hold in Reset '1' - Release from Reset
(Default)
GPIO7_27 AWR Extern SYNC
SMB_CLK SMBus Clock. I2C1 SCL for PCIe
SMB_DATA SMBus Data. I2C1 SDA for PCIe
I2C1 SCL EEPROM(U100) Serial Clock Address: 0x50
I2C1 SDA EEPROM(U100) Serial Data Address: 0x50

Hardware Specifications www.ti.com
18 SPRUIS6–September 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
2.6.2 Switches
The MMWCAS-DSP-EVM has a 1×6 DIP(S4) switch for boot selection (as shown in Table 5). Out of the
box, the EVM has S4.5 and S4.6 "ON" so that it boots from the SD card.
Table 5. User Configurable Supported Boot Modes
Boot Mode S4 Configuration[5:0]
USB boot 010000
UART boot 010011
eMMC boot 111000
eMMC boot partition 111011
SD boot 110000 (Default)
2.6.3 Push Buttons
The MMWCAS-DSP-EVM supports three push buttons for POR reset, SoC Reset, and an ON/OFF button.
By default, the ON/OFF button is disabled. Refer to SCH for resistor options for ON/OFF functionality.
Table 6. Push Button Functionality Information
Reference Usage Description
S1 ON/OFF Turns the EVM on and off with each push. By default, the switch is disabled
so that the EVM powers up when power is applied. Refer to the SCH for
resistor options in order to toggle ON/OFF functionality.
S2 PORz Reset Generates a PORz reset upon pushing.
S3 SoC Reset Generates a reset on the SoC.
2.6.4 LEDs
The MMWCAS-DSP-EVM supports LEDs for user indications, as listed in Table 7.
Table 7. User and Status LED Reference Designator and Description
Reference Usage Description Color
D3 Status Ethernet Activity Green
D4 Status TPS74801 - Ethernet 1.0V Power Good Green
D5 Status FTDI Power Enable – 5V Green
D6 Status FTDI RX Green
D7 Status FTDI TX Green
D9 User GPIO User programmable Green
D10 Status Ethernet 2.5V Power Good Green
D11 Status TDA2 Reset out Green
D12 Status 12V Input Green
D13 User GPIO User programmable Green
D14 User GPIO User programmable Green
D15 User GPIO User programmable Green
D16 Status TDA2 PORz – Power On Reset Green
D17 Status FPGA1 LED Green
D18 User GPIO User programmable Green
D19 User GPIO User programmable Green
D20 Status TDA2 Reset – Reset based on status of VDD_MPU Green
D21 Status TDA2 PMIC Reset out Green
D22 Status FPGA2 LED Green
D23 Status TPS43351 - 3.3V and 5V Power Good Green

www.ti.com mmWave Studio and Matlab Post Processing
19
SPRUIS6–September 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
Table 7. User and Status LED Reference Designator and Description (continued)
Reference Usage Description Color
D24 Status TPS57112 DDR3 1.35V Power Good Green
D25 Status FPGA3 LED Green
D26 Status TPS51200 DDR3 VTT and VREF Power Good Green
D27 Status FPGA4 LED Green
3 mmWave Studio and Matlab Post Processing
TI provides the following evaluation software to get started with the Cascade DSP evaluation module:
• mmWave Studio GUI and Lua scriptable configuration environment
• TDA2x ADC IF data capture application running on the MMWCAS-DSP-EVM
• Matlab post processing sample codes for reading captured ADC IQ sample datasets and example
TDMA-MIMO and TX-Beamforming use modes
For details on getting started with these demos, see the mmWave Studio User Guide

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated