Texas Instruments TMS320C6745 DSP User manual

TMS320C6745/C6747 DSP
Technical Reference Manual
Literature Number: SPRUH91D
March 2013–Revised September 2016

2SPRUH91D–March 2013–Revised September 2016
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Contents
Contents
Preface....................................................................................................................................... 64
1 Overview........................................................................................................................... 65
1.1 Introduction.................................................................................................................. 66
2 DSP Subsystem ................................................................................................................. 68
2.1 Introduction.................................................................................................................. 69
2.2 TMS320C674x Megamodule ............................................................................................. 70
2.2.1 Internal Memory Controllers ..................................................................................... 70
2.2.2 Internal Peripherals ............................................................................................... 70
2.3 Memory Map................................................................................................................ 74
2.3.1 DSP Internal Memory............................................................................................. 74
2.3.2 External Memory .................................................................................................. 74
2.4 Advanced Event Triggering (AET) ....................................................................................... 75
3 System Interconnect........................................................................................................... 76
3.1 Introduction.................................................................................................................. 77
3.2 System Interconnect Block Diagram..................................................................................... 78
4 System Memory ................................................................................................................. 79
4.1 Introduction.................................................................................................................. 80
4.2 DSP Memories.............................................................................................................. 80
4.3 Peripherals .................................................................................................................. 81
5 Memory Protection Unit (MPU)............................................................................................. 82
5.1 Introduction.................................................................................................................. 83
5.1.1 Purpose of the MPU .............................................................................................. 83
5.1.2 Features ............................................................................................................ 83
5.1.3 Block Diagram ..................................................................................................... 83
5.1.4 MPU Default Configuration....................................................................................... 84
5.2 Architecture ................................................................................................................. 84
5.2.1 Privilege Levels.................................................................................................... 84
5.2.2 Memory Protection Ranges...................................................................................... 85
5.2.3 Permission Structures ............................................................................................ 86
5.2.4 Protection Check .................................................................................................. 87
5.2.5 DSP L1/L2 Cache Controller Accesses ........................................................................ 87
5.2.6 MPU Register Protection......................................................................................... 87
5.2.7 Invalid Accesses and Exceptions ............................................................................... 88
5.2.8 Reset Considerations............................................................................................. 88
5.2.9 Interrupt Support .................................................................................................. 88
5.2.10 Emulation Considerations....................................................................................... 88
5.3 MPU Registers.............................................................................................................. 89
5.3.1 Revision Identification Register (REVID)....................................................................... 91
5.3.2 Configuration Register (CONFIG)............................................................................... 91
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT).............................................................. 92
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT)........................................................... 93
5.3.5 Interrupt Enable Set Register (IENSET) ....................................................................... 94
5.3.6 Interrupt Enable Clear Register (IENCLR)..................................................................... 94
5.3.7 Fixed Range Start Address Register (FXD_MPSAR) ........................................................ 95

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5.3.8 Fixed Range End Address Register (FXD_MPEAR) ......................................................... 95
5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)................................. 96
5.3.10 Programmable Range nStart Address Registers (PROGn_MPSAR) .................................... 97
5.3.11 Programmable Range nEnd Address Registers (PROGn_MPEAR) ..................................... 98
5.3.12 Programmable Range nMemory Protection Page Attributes Register (PROGn_MPPA).............. 99
5.3.13 Fault Address Register (FLTADDRR)........................................................................ 100
5.3.14 Fault Status Register (FLTSTAT)............................................................................. 101
5.3.15 Fault Clear Register (FLTCLR) ............................................................................... 102
6 Device Clocking................................................................................................................ 103
6.1 Overview................................................................................................................... 104
6.2 Frequency Flexibility...................................................................................................... 105
6.3 Peripheral Clocking....................................................................................................... 107
6.3.1 USB Clocking..................................................................................................... 107
6.3.2 EMIFB Clocking.................................................................................................. 109
6.3.3 EMIFA Clocking.................................................................................................. 111
6.3.4 EMAC Clocking .................................................................................................. 112
6.3.5 I/O Domains ...................................................................................................... 114
7 Phase-Locked Loop Controller (PLLC) ................................................................................ 115
7.1 Introduction ................................................................................................................ 116
7.2 PLL0 Control .............................................................................................................. 116
7.2.1 Device Clock Generation ....................................................................................... 118
7.2.2 Steps for Changing PLL0 Domain Frequency ............................................................... 119
7.3 Locking/Unlocking PLL Register Access .............................................................................. 120
7.4 PLLC Registers ........................................................................................................... 121
7.4.1 Revision Identification Register (REVID) ..................................................................... 122
7.4.2 Reset Type Status Register (RSTYPE)....................................................................... 122
7.4.3 PLL Control Register (PLLCTL)................................................................................ 123
7.4.4 OBSCLK Select Register (OCSEL) ........................................................................... 124
7.4.5 PLL Multiplier Control Register (PLLM)....................................................................... 125
7.4.6 PLL Pre-Divider Control Register (PREDIV) ................................................................. 125
7.4.7 PLL Controller Divider 1 Register (PLLDIV1) ................................................................ 126
7.4.8 PLL Controller Divider 2 Register (PLLDIV2) ................................................................ 126
7.4.9 PLL Controller Divider 3 Register (PLLDIV3) ................................................................ 127
7.4.10 PLL Controller Divider 4 Register (PLLDIV4) ............................................................... 127
7.4.11 PLL Controller Divider 5 Register (PLLDIV5) ............................................................... 128
7.4.12 PLL Controller Divider 6 Register (PLLDIV6) ............................................................... 128
7.4.13 PLL Controller Divider 7 Register (PLLDIV7) ............................................................... 129
7.4.14 Oscillator Divider 1 Register (OSCDIV)...................................................................... 130
7.4.15 PLL Post-Divider Control Register (POSTDIV)............................................................. 131
7.4.16 PLL Controller Command Register (PLLCMD) ............................................................. 131
7.4.17 PLL Controller Status Register (PLLSTAT) ................................................................. 132
7.4.18 PLL Controller Clock Align Control Register (ALNCTL) ................................................... 133
7.4.19 PLLDIV Ratio Change Status Register (DCHANGE) ...................................................... 134
7.4.20 Clock Enable Control Register (CKEN)...................................................................... 135
7.4.21 Clock Status Register (CKSTAT)............................................................................. 136
7.4.22 SYSCLK Status Register (SYSTAT) ......................................................................... 137
7.4.23 Emulation Performance Counter 0 Register (EMUCNT0)................................................. 138
7.4.24 Emulation Performance Counter 1 Register (EMUCNT1)................................................. 138
8 Power and Sleep Controller (PSC) ...................................................................................... 139
8.1 Introduction ................................................................................................................ 140
8.2 Power Domain and Module Topology.................................................................................. 140
8.2.1 Power Domain States........................................................................................... 142
8.2.2 Module States.................................................................................................... 142

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8.3 Executing State Transitions ............................................................................................. 144
8.3.1 Power Domain State Transitions .............................................................................. 144
8.3.2 Module State Transitions ....................................................................................... 144
8.4 IcePick Emulation Support in the PSC................................................................................. 145
8.5 PSC Interrupts............................................................................................................. 145
8.5.1 Interrupt Events .................................................................................................. 145
8.5.2 Interrupt Registers............................................................................................... 146
8.5.3 Interrupt Handling................................................................................................ 147
8.6 PSC Registers............................................................................................................. 148
8.6.1 Revision Identification Register (REVID) ..................................................................... 149
8.6.2 Interrupt Evaluation Register (INTEVAL) ..................................................................... 149
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)................................... 150
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)................................... 150
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ...................................... 151
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ...................................... 151
8.6.7 Power Error Pending Register (PERRPR) ................................................................... 152
8.6.8 Power Error Clear Register (PERRCR)....................................................................... 152
8.6.9 Power Domain Transition Command Register (PTCMD)................................................... 153
8.6.10 Power Domain Transition Status Register (PTSTAT)...................................................... 154
8.6.11 Power Domain 0 Status Register (PDSTAT0).............................................................. 155
8.6.12 Power Domain 1 Status Register (PDSTAT1).............................................................. 156
8.6.13 Power Domain 0 Control Register (PDCTL0)............................................................... 157
8.6.14 Power Domain 1 Control Register (PDCTL1)............................................................... 158
8.6.15 Power Domain 0 Configuration Register (PDCFG0)....................................................... 159
8.6.16 Power Domain 1 Configuration Register (PDCFG1)....................................................... 160
8.6.17 Module Status nRegister (MDSTATn)....................................................................... 161
8.6.18 PSC0 Module Control nRegister (modules 0-15) (MDCTLn)............................................ 162
8.6.19 PSC1 Module Control nRegister (modules 0-31) (MDCTLn)............................................ 163
9 Power Management........................................................................................................... 164
9.1 Introduction ................................................................................................................ 165
9.2 Power Consumption Overview.......................................................................................... 165
9.3 PSC and PLLC Overview................................................................................................ 165
9.4 Features.................................................................................................................... 166
9.5 Clock Management....................................................................................................... 167
9.5.1 Module Clock ON/OFF.......................................................................................... 167
9.5.2 Module Clock Frequency Scaling.............................................................................. 167
9.5.3 PLL Bypass and Power Down ................................................................................. 167
9.6 DSP Sleep Mode Management......................................................................................... 168
9.6.1 C674x DSP CPU Sleep Mode ................................................................................. 168
9.6.2 C674x Megamodule Sleep Mode.............................................................................. 168
9.7 RTC-Only Mode........................................................................................................... 168
9.8 Additional Peripheral Power Management Considerations.......................................................... 169
9.8.1 USB PHY Power Down Control ............................................................................... 169
9.8.2 EMIFB Memory Clock Gating .................................................................................. 169
10 System Configuration (SYSCFG) Module............................................................................. 170
10.1 Introduction ................................................................................................................ 171
10.2 Protection .................................................................................................................. 172
10.2.1 Requirements to Access SYSCFG Registers............................................................... 173
10.3 Master Priority Control ................................................................................................... 174
10.4 Interrupt Support.......................................................................................................... 175
10.4.1 Interrupt Events and Requests................................................................................ 175
10.4.2 Interrupt Multiplexing........................................................................................... 175
10.4.3 Host-DSP Communication Interrupts ........................................................................ 175

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10.5 SYSCFG Registers....................................................................................................... 176
10.5.1 Revision Identification Register (REVID) .................................................................... 177
10.5.2 Device Identification Register 0 (DEVIDR0)................................................................. 177
10.5.3 Boot Configuration Register (BOOTCFG)................................................................... 178
10.5.4 Silicon Revision Identification Register (CHIPREVID)..................................................... 178
10.5.5 Kick Registers (KICK0R-KICK1R)............................................................................ 179
10.5.6 Host 1 Configuration Register (HOST1CFG) ............................................................... 180
10.5.7 Interrupt Registers.............................................................................................. 181
10.5.8 Fault Registers.................................................................................................. 184
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)............................................................ 186
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)............................................. 189
10.5.11 Suspend Source Register (SUSPSRC) .................................................................... 226
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................ 228
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) .............................................................. 229
10.5.14 Chip Configuration 0 Register (CFGCHIP0)............................................................... 230
10.5.15 Chip Configuration 1 Register (CFGCHIP1)............................................................... 231
10.5.16 Chip Configuration 2 Register (CFGCHIP2)............................................................... 235
10.5.17 Chip Configuration 3 Register (CFGCHIP3)............................................................... 237
10.5.18 Chip Configuration 4 Register (CFGCHIP4)............................................................... 238
11 Boot Considerations ......................................................................................................... 239
11.1 Introduction ................................................................................................................ 240
12 Programmable Real-Time Unit Subsystem (PRUSS).............................................................. 241
13 Enhanced Capture (eCAP) Module...................................................................................... 243
13.1 Introduction ................................................................................................................ 244
13.1.1 Purpose of the Peripheral ..................................................................................... 244
13.1.2 Features.......................................................................................................... 244
13.2 Architecture................................................................................................................ 245
13.2.1 Capture and APWM Operating Mode........................................................................ 246
13.2.2 Capture Mode Description..................................................................................... 247
13.3 Applications ............................................................................................................... 254
13.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example ......................................... 255
13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ........................... 257
13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example ....................................... 259
13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example ......................... 261
13.3.5 Application of the APWM Mode.............................................................................. 263
13.4 Registers................................................................................................................... 270
13.4.1 Time-Stamp Counter Register (TSCTR)..................................................................... 270
13.4.2 Counter Phase Control Register (CTRPHS)................................................................ 271
13.4.3 Capture 1 Register (CAP1).................................................................................... 271
13.4.4 Capture 2 Register (CAP2).................................................................................... 272
13.4.5 Capture 3 Register (CAP3).................................................................................... 272
13.4.6 Capture 4 Register (CAP4).................................................................................... 273
13.4.7 ECAP Control Register 1 (ECCTL1) ......................................................................... 273
13.4.8 ECAP Control Register 2 (ECCTL2) ......................................................................... 275
13.4.9 ECAP Interrupt Enable Register (ECEINT) ................................................................. 276
13.4.10 ECAP Interrupt Flag Register (ECFLG).................................................................... 278
13.4.11 ECAP Interrupt Clear Register (ECCLR)................................................................... 279
13.4.12 ECAP Interrupt Forcing Register (ECFRC)................................................................ 280
13.4.13 Revision ID Register (REVID) ............................................................................... 281
14 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 282
14.1 Introduction ................................................................................................................ 283
14.1.1 Introduction...................................................................................................... 283

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14.1.2 Submodule Overview .......................................................................................... 283
14.1.3 Register Mapping............................................................................................... 287
14.2 Architecture................................................................................................................ 288
14.2.1 Overview......................................................................................................... 288
14.2.2 Proper Interrupt Initialization Procedure..................................................................... 291
14.2.3 Time-Base (TB) Submodule................................................................................... 292
14.2.4 Counter-Compare (CC) Submodule.......................................................................... 301
14.2.5 Action-Qualifier (AQ) Submodule............................................................................. 306
14.2.6 Dead-Band Generator (DB) Submodule..................................................................... 324
14.2.7 PWM-Chopper (PC) Submodule.............................................................................. 328
14.2.8 Trip-Zone (TZ) Submodule .................................................................................... 332
14.2.9 Event-Trigger (ET) Submodule ............................................................................... 336
14.2.10 High-Resolution PWM (HRPWM) Submodule............................................................. 340
14.3 Applications to Power Topologies ...................................................................................... 347
14.3.1 Overview of Multiple Modules ................................................................................ 347
14.3.2 Key Configuration Capabilities................................................................................ 348
14.3.3 Controlling Multiple Buck Converters With Independent Frequencies................................... 349
14.3.4 Controlling Multiple Buck Converters With Same Frequencies........................................... 352
14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters...................................................... 355
14.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................ 358
14.3.7 Practical Applications Using Phase Control Between PWM Modules ................................... 362
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter...................................................... 363
14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter...................................... 368
14.4 Registers................................................................................................................... 371
14.4.1 Time-Base Submodule Registers ............................................................................ 371
14.4.2 Counter-Compare Submodule Registers.................................................................... 375
14.4.3 Action-Qualifier Submodule Registers....................................................................... 378
14.4.4 Dead-Band Generator Submodule Registers............................................................... 382
14.4.5 PWM-Chopper Submodule Register......................................................................... 385
14.4.6 Trip-Zone Submodule Registers.............................................................................. 386
14.4.7 Event-Trigger Submodule Registers ......................................................................... 390
14.4.8 High-Resolution PWM Submodule Registers............................................................... 393
15 Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 396
15.1 Introduction ................................................................................................................ 397
15.2 Architecture................................................................................................................ 400
15.2.1 EQEP Inputs..................................................................................................... 400
15.2.2 Functional Description ......................................................................................... 400
15.2.3 Quadrature Decoder Unit (QDU) ............................................................................. 402
15.2.4 Position Counter and Control Unit (PCCU).................................................................. 405
15.2.5 eQEP Edge Capture Unit...................................................................................... 413
15.2.6 eQEP Watchdog................................................................................................ 416
15.2.7 Unit Timer Base................................................................................................. 417
15.2.8 eQEP Interrupt Structure ...................................................................................... 417
15.3 eQEP Registers........................................................................................................... 418
15.3.1 eQEP Position Counter Register (QPOSCNT) ............................................................. 419
15.3.2 eQEP Position Counter Initialization Register (QPOSINIT)............................................... 419
15.3.3 eQEP Maximum Position Count Register (QPOSMAX)................................................... 419
15.3.4 eQEP Position-Compare Register (QPOSCMP) ........................................................... 420
15.3.5 eQEP Index Position Latch Register (QPOSILAT)......................................................... 420
15.3.6 eQEP Strobe Position Latch Register (QPOSSLAT) ...................................................... 420
15.3.7 eQEP Position Counter Latch Register (QPOSLAT)....................................................... 421
15.3.8 eQEP Unit Timer Register (QUTMR) ........................................................................ 421
15.3.9 eQEP Unit Period Register (QUPRD)........................................................................ 421

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15.3.10 eQEP Watchdog Timer Register (QWDTMR)............................................................. 422
15.3.11 eQEP Watchdog Period Register (QWDPRD) ............................................................ 422
15.3.12 QEP Decoder Control Register (QDECCTL) .............................................................. 423
15.3.13 eQEP Control Register (QEPCTL) ......................................................................... 423
15.3.14 eQEP Capture Control Register (QCAPCTL) ............................................................. 426
15.3.15 eQEP Position-Compare Control Register (QPOSCTL) ................................................. 427
15.3.16 eQEP Interrupt Enable Register (QEINT).................................................................. 428
15.3.17 eQEP Interrupt Flag Register (QFLG)...................................................................... 429
15.3.18 eQEP Interrupt Clear Register (QCLR) .................................................................... 430
15.3.19 eQEP Interrupt Force Register (QFRC).................................................................... 432
15.3.20 eQEP Status Register (QEPSTS)........................................................................... 433
15.3.21 eQEP Capture Timer Register (QCTMR).................................................................. 434
15.3.22 eQEP Capture Period Register (QCPRD) ................................................................. 434
15.3.23 eQEP Capture Timer Latch Register (QCTMRLAT)...................................................... 434
15.3.24 eQEP Capture Period Latch Register (QCPRDLAT)..................................................... 435
15.3.25 eQEP Revision ID Register (REVID) ....................................................................... 435
16 Enhanced Direct Memory Access (EDMA3) Controller........................................................... 436
16.1 Introduction ................................................................................................................ 437
16.1.1 Overview......................................................................................................... 437
16.1.2 Features.......................................................................................................... 437
16.1.3 Functional Block Diagram ..................................................................................... 439
16.1.4 Terminology Used in This Document ........................................................................ 439
16.2 Architecture................................................................................................................ 441
16.2.1 Functional Overview............................................................................................ 441
16.2.2 Types of EDMA3 Transfers ................................................................................... 444
16.2.3 Parameter RAM (PaRAM)..................................................................................... 447
16.2.4 Initiating a DMA Transfer ...................................................................................... 457
16.2.5 Completion of a DMA Transfer................................................................................ 460
16.2.6 Event, Channel, and PaRAM Mapping ...................................................................... 461
16.2.7 EDMA3 Channel Controller Regions......................................................................... 464
16.2.8 Chaining EDMA3 Channels ................................................................................... 466
16.2.9 EDMA3 Interrupts............................................................................................... 466
16.2.10 Event Queue(s)................................................................................................ 473
16.2.11 EDMA3 Transfer Controller (EDMA3TC)................................................................... 475
16.2.12 Event Dataflow ................................................................................................ 478
16.2.13 EDMA3 Prioritization.......................................................................................... 479
16.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................ 481
16.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................ 482
16.2.16 Reset Considerations......................................................................................... 482
16.2.17 Power Management .......................................................................................... 482
16.2.18 Emulation Considerations.................................................................................... 483
16.3 Transfer Examples........................................................................................................ 483
16.3.1 Block Move Example........................................................................................... 483
16.3.2 Subframe Extraction Example ................................................................................ 485
16.3.3 Data Sorting Example.......................................................................................... 486
16.3.4 Peripheral Servicing Example................................................................................. 488
16.4 Registers................................................................................................................... 500
16.4.1 Parameter RAM (PaRAM) Entries............................................................................ 500
16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................ 507
16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers........................................................ 546
16.5 Tips ......................................................................................................................... 567
16.5.1 Debug Checklist ................................................................................................ 567
16.5.2 Miscellaneous Programming/Debug Tips ................................................................... 568

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16.6 Setting Up a Transfer .................................................................................................... 569
17 EMAC/MDIO Module.......................................................................................................... 570
17.1 Introduction ................................................................................................................ 571
17.1.1 Purpose of the Peripheral ..................................................................................... 571
17.1.2 Features.......................................................................................................... 571
17.1.3 Functional Block Diagram ..................................................................................... 572
17.1.4 Industry Standard(s) Compliance Statement................................................................ 573
17.1.5 Terminology ..................................................................................................... 573
17.2 Architecture................................................................................................................ 574
17.2.1 Clock Control.................................................................................................... 574
17.2.2 Memory Map .................................................................................................... 575
17.2.3 Signal Descriptions............................................................................................. 575
17.2.4 Ethernet Protocol Overview ................................................................................... 578
17.2.5 Programming Interface......................................................................................... 579
17.2.6 EMAC Control Module ......................................................................................... 590
17.2.7 MDIO Module ................................................................................................... 591
17.2.8 EMAC Module................................................................................................... 596
17.2.9 MAC Interface................................................................................................... 598
17.2.10 Packet Receive Operation ................................................................................... 602
17.2.11 Packet Transmit Operation .................................................................................. 607
17.2.12 Receive and Transmit Latency .............................................................................. 608
17.2.13 Transfer Node Priority ........................................................................................ 608
17.2.14 Reset Considerations......................................................................................... 609
17.2.15 Initialization..................................................................................................... 610
17.2.16 Interrupt Support .............................................................................................. 612
17.2.17 Power Management .......................................................................................... 616
17.2.18 Emulation Considerations.................................................................................... 616
17.3 Registers................................................................................................................... 617
17.3.1 EMAC Control Module Registers............................................................................. 617
17.3.2 MDIO Registers................................................................................................. 631
17.3.3 EMAC Module Registers....................................................................................... 644
18 External Memory Interface A (EMIFA).................................................................................. 694
18.1 Introduction ................................................................................................................ 695
18.1.1 Purpose of the Peripheral ..................................................................................... 695
18.1.2 Features.......................................................................................................... 695
18.1.3 Functional Block Diagram ..................................................................................... 695
18.2 Architecture................................................................................................................ 695
18.2.1 Clock Control.................................................................................................... 696
18.2.2 EMIFA Requests................................................................................................ 696
18.2.3 Pin Descriptions................................................................................................. 696
18.2.4 SDRAM Controller and Interface ............................................................................. 698
18.2.5 Asynchronous Controller and Interface...................................................................... 710
18.2.6 Data Bus Parking............................................................................................... 729
18.2.7 Reset and Initialization Considerations ...................................................................... 729
18.2.8 Interrupt Support................................................................................................ 730
18.2.9 EDMA Event Support .......................................................................................... 731
18.2.10 Pin Multiplexing................................................................................................ 731
18.2.11 Memory Map................................................................................................... 731
18.2.12 Priority and Arbitration........................................................................................ 732
18.2.13 System Considerations....................................................................................... 733
18.2.14 Power Management .......................................................................................... 734
18.2.15 Emulation Considerations.................................................................................... 735
18.3 Example Configuration................................................................................................... 736

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18.3.1 Hardware Interface ............................................................................................. 736
18.3.2 Software Configuration......................................................................................... 736
18.4 Registers................................................................................................................... 758
18.4.1 Module ID Register (MIDR) ................................................................................... 759
18.4.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 759
18.4.3 SDRAM Configuration Register (SDCR) .................................................................... 761
18.4.4 SDRAM Refresh Control Register (SDRCR)................................................................ 763
18.4.5 Asynchronous nConfiguration Registers (CE2CFG-CE5CFG) .......................................... 764
18.4.6 SDRAM Timing Register (SDTIMR).......................................................................... 766
18.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 767
18.4.8 EMIFA Interrupt Raw Register (INTRAW)................................................................... 768
18.4.9 EMIFA Interrupt Masked Register (INTMSK) ............................................................... 769
18.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET)....................................................... 770
18.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR).................................................... 771
18.4.12 NAND Flash Control Register (NANDFCR) ............................................................... 772
18.4.13 NAND Flash Status Register (NANDFSR)................................................................. 774
18.4.14 NAND Flash nECC Registers (NANDF1ECC-NANDF4ECC) .......................................... 775
18.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)....................................... 776
18.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) .................................................. 777
18.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) .................................................. 777
18.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) .................................................. 778
18.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) .................................................. 778
18.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1)................................. 779
18.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2)................................. 779
18.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)..................................... 780
18.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)..................................... 780
19 External Memory Interface B (EMIFB).................................................................................. 781
19.1 Introduction ................................................................................................................ 782
19.1.1 Purpose of the Peripheral ..................................................................................... 782
19.1.2 Features.......................................................................................................... 782
19.1.3 Functional Block Diagram ..................................................................................... 782
19.2 Architecture................................................................................................................ 783
19.2.1 Clock Control.................................................................................................... 783
19.2.2 EMIF Requests.................................................................................................. 783
19.2.3 Pin Descriptions................................................................................................. 783
19.2.4 Pin Multiplexing ................................................................................................. 784
19.2.5 Memory Map .................................................................................................... 784
19.2.6 SDRAM Controller and Interface ............................................................................. 784
19.2.7 Reset and Initialization Considerations ...................................................................... 802
19.2.8 Interrupt Support................................................................................................ 802
19.2.9 Power Management............................................................................................ 803
19.2.10 Emulation Considerations.................................................................................... 805
19.3 Example Configuration................................................................................................... 805
19.4 Registers................................................................................................................... 809
19.4.1 SDRAM Configuration Register (SDCFG) .................................................................. 810
19.4.2 SDRAM Refresh Control Register (SDRFC)................................................................ 812
19.4.3 SDRAM Timing 1 Register (SDTIM1)........................................................................ 813
19.4.4 SDRAM Timing 2 Register (SDTIM2)........................................................................ 814
19.4.5 Peripheral Bus Burst Priority Register (BPRIO) ............................................................ 816
19.4.6 Performance Counter 1 Register (PC1) ..................................................................... 817
19.4.7 Performance Counter 2 Register (PC2) ..................................................................... 817
19.4.8 Performance Counter Configuration Register (PCC) ...................................................... 818
19.4.9 Performance Counter Master Region Select Register (PCMRS) ........................................ 820

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19.4.10 Interrupt Raw Register (IRR) ................................................................................ 821
19.4.11 Interrupt Mask Register (IMR)............................................................................... 822
19.4.12 Interrupt Mask Set Register (IMSR) ........................................................................ 823
19.4.13 Interrupt Mask Clear Register (IMCR)...................................................................... 823
20 General-Purpose Input/Output (GPIO) ................................................................................. 824
20.1 Introduction ................................................................................................................ 825
20.1.1 Purpose of the Peripheral ..................................................................................... 825
20.1.2 Features.......................................................................................................... 825
20.1.3 Functional Block Diagram ..................................................................................... 825
20.1.4 Industry Standard(s) Compliance Statement................................................................ 825
20.2 Architecture................................................................................................................ 826
20.2.1 Clock Control.................................................................................................... 826
20.2.2 Signal Descriptions............................................................................................. 826
20.2.3 Pin Multiplexing ................................................................................................. 826
20.2.4 Endianness Considerations ................................................................................... 826
20.2.5 GPIO Register Structure....................................................................................... 827
20.2.6 Using a GPIO Signal as an Output........................................................................... 830
20.2.7 Using a GPIO Signal as an Input............................................................................. 831
20.2.8 Reset Considerations .......................................................................................... 831
20.2.9 Initialization ...................................................................................................... 832
20.2.10 Interrupt Support .............................................................................................. 832
20.2.11 EDMA Event Support......................................................................................... 833
20.2.12 Power Management .......................................................................................... 833
20.2.13 Emulation Considerations.................................................................................... 833
20.3 Registers................................................................................................................... 834
20.3.1 Revision ID Register (REVID)................................................................................. 835
20.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN)...................................................... 836
20.3.3 GPIO Direction Registers (DIRn)............................................................................. 837
20.3.4 GPIO Output Data Registers (OUT_DATAn)............................................................... 839
20.3.5 GPIO Set Data Registers (SET_DATAn).................................................................... 841
20.3.6 GPIO Clear Data Registers (CLR_DATAn)................................................................. 843
20.3.7 GPIO Input Data Registers (IN_DATAn).................................................................... 845
20.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn)........................................... 847
20.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn)........................................ 849
20.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn)........................................ 851
20.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn)..................................... 853
20.3.12 GPIO Interrupt Status Registers (INTSTATn)............................................................. 855
21 Host Port Interface (HPI).................................................................................................... 857
21.1 Introduction ................................................................................................................ 858
21.1.1 Purpose of the Peripheral ..................................................................................... 858
21.1.2 Features.......................................................................................................... 858
21.1.3 Functional Block Diagram ..................................................................................... 859
21.1.4 Industry Standard(s) Compliance Statement................................................................ 860
21.1.5 Terminology Used in This Document ........................................................................ 860
21.2 Architecture................................................................................................................ 861
21.2.1 Clock Control.................................................................................................... 861
21.2.2 Memory Map .................................................................................................... 861
21.2.3 Signal Descriptions............................................................................................. 861
21.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks................................................ 862
21.2.5 Protocol Description............................................................................................ 863
21.2.6 Operation ........................................................................................................ 863
21.2.7 Reset Considerations .......................................................................................... 878
21.2.8 Initialization ...................................................................................................... 878

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21.2.9 Interrupt Support................................................................................................ 879
21.2.10 EDMA Event Support......................................................................................... 880
21.2.11 Power Management .......................................................................................... 880
21.2.12 Emulation Considerations.................................................................................... 881
21.3 Registers................................................................................................................... 881
21.3.1 Revision Identification Register (REVID) .................................................................... 882
21.3.2 Power and Emulation Management Register (PWREMU_MGMT) ...................................... 882
21.3.3 GPIO Enable Register (GPIO_EN) .......................................................................... 883
21.3.4 GPIO Direction 1 Register (GPIO_DIR1).................................................................... 884
21.3.5 GPIO Data 1 Register (GPIO_DAT1)........................................................................ 884
21.3.6 GPIO Direction 2 Register (GPIO_DIR2).................................................................... 885
21.3.7 GPIO Data 2 Register (GPIO_DAT2)........................................................................ 886
21.3.8 Host Port Interface Control Register (HPIC) ................................................................ 887
21.3.9 Host Port Interface Write Address Register (HPIAW) ..................................................... 889
21.3.10 Host Port Interface Read Address Register (HPIAR) .................................................... 889
22 Inter-Integrated Circuit (I2C) Module ................................................................................... 890
22.1 Introduction ................................................................................................................ 891
22.1.1 Purpose of the Peripheral ..................................................................................... 891
22.1.2 Features.......................................................................................................... 891
22.1.3 Functional Block Diagram ..................................................................................... 892
22.1.4 Industry Standard(s) Compliance Statement................................................................ 892
22.2 Architecture................................................................................................................ 893
22.2.1 Bus Structure.................................................................................................... 893
22.2.2 Clock Generation ............................................................................................... 894
22.2.3 Clock Synchronization ......................................................................................... 895
22.2.4 Signal Descriptions............................................................................................. 895
22.2.5 START and STOP Conditions ................................................................................ 896
22.2.6 Serial Data Formats............................................................................................ 897
22.2.7 Operating Modes ............................................................................................... 899
22.2.8 NACK Bit Generation........................................................................................... 900
22.2.9 Arbitration........................................................................................................ 901
22.2.10 Reset Considerations......................................................................................... 902
22.2.11 Initialization..................................................................................................... 902
22.2.12 Interrupt Support .............................................................................................. 903
22.2.13 DMA Events Generated by the I2C Peripheral............................................................ 904
22.2.14 Power Management .......................................................................................... 904
22.2.15 Emulation Considerations.................................................................................... 904
22.3 Registers................................................................................................................... 905
22.3.1 I2C Own Address Register (ICOAR)......................................................................... 906
22.3.2 I2C Interrupt Mask Register (ICIMR)......................................................................... 907
22.3.3 I2C Interrupt Status Register (ICSTR) ...................................................................... 908
22.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH)....................................................... 911
22.3.5 I2C Data Count Register (ICCNT)............................................................................ 912
22.3.6 I2C Data Receive Register (ICDRR)......................................................................... 913
22.3.7 I2C Slave Address Register (ICSAR)........................................................................ 914
22.3.8 I2C Data Transmit Register (ICDXR) ........................................................................ 915
22.3.9 I2C Mode Register (ICMDR) .................................................................................. 916
22.3.10 I2C Interrupt Vector Register (ICIVR) ...................................................................... 920
22.3.11 I2C Extended Mode Register (ICEMDR)................................................................... 921
22.3.12 I2C Prescaler Register (ICPSC)............................................................................. 922
22.3.13 I2C Revision Identification Register (REVID1) ............................................................ 923
22.3.14 I2C Revision Identification Register (REVID2) ........................................................... 923
22.3.15 I2C DMA Control Register (ICDMAC)...................................................................... 924

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22.3.16 I2C Pin Function Register (ICPFUNC) .................................................................... 925
22.3.17 I2C Pin Direction Register (ICPDIR) ....................................................................... 926
22.3.18 I2C Pin Data In Register (ICPDIN) ......................................................................... 927
22.3.19 I2C Pin Data Out Register (ICPDOUT) .................................................................... 928
22.3.20 I2C Pin Data Set Register (ICPDSET) .................................................................... 929
22.3.21 I2C Pin Data Clear Register (ICPDCLR) .................................................................. 930
23 Liquid Crystal Display Controller (LCDC)............................................................................. 931
23.1 Introduction ................................................................................................................ 932
23.1.1 Purpose of the Peripheral ..................................................................................... 932
23.1.2 Features.......................................................................................................... 933
23.1.3 Terminology ..................................................................................................... 933
23.2 Architecture................................................................................................................ 933
23.2.1 Clocking.......................................................................................................... 933
23.2.2 LCD External I/O Signals...................................................................................... 935
23.2.3 DMA Engine..................................................................................................... 936
23.2.4 LIDD Controller.................................................................................................. 937
23.2.5 Raster Controller................................................................................................ 939
23.3 Registers................................................................................................................... 949
23.3.1 LCD Revision Identification Register (REVID).............................................................. 949
23.3.2 LCD Control Register (LCD_CTRL).......................................................................... 950
23.3.3 LCD Status Register (LCD_STAT)........................................................................... 952
23.3.4 LCD LIDD Control Register (LIDD_CTRL) .................................................................. 955
23.3.5 LCD LIDD CSnConfiguration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF)................ 957
23.3.6 LCD LIDD CSnAddress Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR)........ 958
23.3.7 LCD LIDD CSnData Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA)............. 959
23.3.8 LCD Raster Control Register (RASTER_CTRL)............................................................ 960
23.3.9 LCD Raster Timing Register 0 (RASTER_TIMING_0) .................................................... 967
23.3.10 LCD Raster Timing Register 1 (RASTER_TIMING_1)................................................... 969
23.3.11 LCD Raster Timing Register 2 (RASTER_TIMING_2)................................................... 973
23.3.12 LCD Raster Subpanel Display Register (RASTER_SUBPANEL) ...................................... 977
23.3.13 LCD DMA Control Register (LCDDMA_CTRL)............................................................ 979
23.3.14 LCD DMA Frame Buffer nBase Address Registers
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE) ........................................................ 980
23.3.15 LCD DMA Frame Buffer nCeiling Address Registers
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING) ................................................. 980
24 Multichannel Audio Serial Port (McASP).............................................................................. 981
24.0.16 Features ....................................................................................................... 982
24.0.17 Protocols Supported ......................................................................................... 983
24.0.18 Functional Block Diagram.................................................................................... 984
24.0.19 Definition of Terms ........................................................................................... 992
24.0.20 Overview ....................................................................................................... 995
24.0.21 Clock and Frame Sync Generators ........................................................................ 995
24.0.22 Reset Considerations ....................................................................................... 1035
24.0.23 EDMA Event Support ....................................................................................... 1035
24.0.24 Power Management......................................................................................... 1035
24.1 Registers ................................................................................................................. 1036
24.1.1 Register Bit Restrictions...................................................................................... 1039
24.1.2 Revision Identification Register (REV) ..................................................................... 1040
24.1.3 Pin Function Register (PFUNC)............................................................................. 1041
24.1.4 Pin Direction Register (PDIR) ............................................................................... 1043
24.1.5 Pin Data Output Register (PDOUT) ........................................................................ 1045
24.1.6 Pin Data Input Register (PDIN).............................................................................. 1047
24.1.7 Pin Data Set Register (PDSET)............................................................................. 1049

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24.1.8 Pin Data Clear Register (PDCLR) .......................................................................... 1051
24.1.9 Global Control Register (GBLCTL) ......................................................................... 1053
24.1.10 Audio Mute Control Register (AMUTE)................................................................... 1055
24.1.11 Digital Loopback Control Register (DLBCTL)............................................................ 1057
24.1.12 Digital Mode Control Register (DITCTL).................................................................. 1058
24.1.13 Receiver Global Control Register (RGBLCTL)........................................................... 1059
24.1.14 Receive Format Unit Bit Mask Register (RMASK) ...................................................... 1060
24.1.15 Receive Bit Stream Format Register (RFMT)............................................................ 1061
24.1.16 Receive Frame Sync Control Register (AFSRCTL)..................................................... 1063
24.1.17 Receive Clock Control Register (ACLKRCTL)........................................................... 1064
24.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL)..................................... 1065
24.1.19 Receive TDM Time Slot Register (RTDM) ............................................................... 1066
24.1.20 Receiver Interrupt Control Register (RINTCTL) ......................................................... 1067
24.1.21 Receiver Status Register (RSTAT)........................................................................ 1068
24.1.22 Current Receive TDM Time Slot Registers (RSLOT)................................................... 1069
24.1.23 Receive Clock Check Control Register (RCLKCHK).................................................... 1070
24.1.24 Receiver DMA Event Control Register (REVTCTL)..................................................... 1071
24.1.25 Transmitter Global Control Register (XGBLCTL)........................................................ 1072
24.1.26 Transmit Format Unit Bit Mask Register (XMASK)...................................................... 1073
24.1.27 Transmit Bit Stream Format Register (XFMT) ........................................................... 1074
24.1.28 Transmit Frame Sync Control Register (AFSXCTL) .................................................... 1076
24.1.29 Transmit Clock Control Register (ACLKXCTL) .......................................................... 1077
24.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) .................................... 1078
24.1.31 Transmit TDM Time Slot Register (XTDM)............................................................... 1079
24.1.32 Transmitter Interrupt Control Register (XINTCTL) ...................................................... 1080
24.1.33 Transmitter Status Register (XSTAT)..................................................................... 1081
24.1.34 Current Transmit TDM Time Slot Register (XSLOT).................................................... 1082
24.1.35 Transmit Clock Check Control Register (XCLKCHK)................................................... 1083
24.1.36 Transmitter DMA Event Control Register (XEVTCTL).................................................. 1084
24.1.37 Serializer Control Registers (SRCTLn)................................................................... 1085
24.1.38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5).......................................... 1086
24.1.39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)........................................ 1086
24.1.40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)..................................... 1087
24.1.41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ................................... 1087
24.1.42 Transmit Buffer Registers (XBUFn)....................................................................... 1088
24.1.43 Receive Buffer Registers (RBUFn)........................................................................ 1088
24.1.44 AFIFO Revision Identification Register (AFIFOREV) ................................................... 1089
24.1.45 Write FIFO Control Register (WFIFOCTL) ............................................................... 1090
24.1.46 Write FIFO Status Register (WFIFOSTS)................................................................ 1091
24.1.47 Read FIFO Control Register (RFIFOCTL)................................................................ 1092
24.1.48 Read FIFO Status Register (RFIFOSTS)................................................................. 1093
25 Multimedia Card (MMC)/Secure Digital (SD) Card Controller................................................. 1094
25.1 Introduction............................................................................................................... 1095
25.1.1 Purpose of the Peripheral.................................................................................... 1095
25.1.2 Features........................................................................................................ 1095
25.1.3 Functional Block Diagram.................................................................................... 1095
25.1.4 Supported Use Case Statement ............................................................................ 1095
25.1.5 Industry Standard(s) Compliance Statement.............................................................. 1096
25.2 Architecture .............................................................................................................. 1096
25.2.1 Clock Control .................................................................................................. 1097
25.2.2 Signal Descriptions............................................................................................ 1098
25.2.3 Protocol Descriptions ......................................................................................... 1099
25.2.4 Data Flow in the Input/Output FIFO ........................................................................ 1100

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25.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ........................................... 1102
25.2.6 FIFO Operation During Card Read Operation............................................................. 1103
25.2.7 FIFO Operation During Card Write Operation............................................................. 1105
25.2.8 Reset Considerations......................................................................................... 1105
25.2.9 Initialization..................................................................................................... 1107
25.2.10 Interrupt Support............................................................................................. 1110
25.2.11 DMA Event Support ......................................................................................... 1111
25.2.12 Power Management......................................................................................... 1111
25.2.13 Emulation Considerations .................................................................................. 1111
25.3 Procedures for Common Operations ................................................................................. 1112
25.3.1 Card Identification Operation ................................................................................ 1112
25.3.2 MMC/SD Mode Single-Block Write Operation Using CPU .............................................. 1115
25.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA........................................ 1117
25.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU.......................................... 1117
25.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ............................................ 1119
25.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU............................................. 1119
25.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA........................................... 1121
25.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................ 1121
25.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA .......................................... 1123
25.3.10 SDIO Card Function......................................................................................... 1123
25.4 Registers ................................................................................................................. 1124
25.4.1 MMC Control Register (MMCCTL).......................................................................... 1125
25.4.2 MMC Memory Clock Control Register (MMCCLK) ....................................................... 1126
25.4.3 MMC Status Register 0 (MMCST0)......................................................................... 1127
25.4.4 MMC Status Register 1 (MMCST1)......................................................................... 1129
25.4.5 MMC Interrupt Mask Register (MMCIM) ................................................................... 1130
25.4.6 MMC Response Time-Out Register (MMCTOR).......................................................... 1132
25.4.7 MMC Data Read Time-Out Register (MMCTOD)......................................................... 1133
25.4.8 MMC Block Length Register (MMCBLEN)................................................................. 1134
25.4.9 MMC Number of Blocks Register (MMCNBLK) ........................................................... 1135
25.4.10 MMC Number of Blocks Counter Register (MMCNBLC)............................................... 1135
25.4.11 MMC Data Receive Register (MMCDRR)................................................................ 1136
25.4.12 MMC Data Transmit Register (MMCDXR) ............................................................... 1136
25.4.13 MMC Command Register (MMCCMD) ................................................................... 1137
25.4.14 MMC Argument Register (MMCARGHL)................................................................. 1139
25.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ................................................... 1140
25.4.16 MMC Data Response Register (MMCDRSP)............................................................ 1142
25.4.17 MMC Command Index Register (MMCCIDX)............................................................ 1142
25.4.18 SDIO Control Register (SDIOCTL)........................................................................ 1143
25.4.19 SDIO Status Register 0 (SDIOST0)....................................................................... 1144
25.4.20 SDIO Interrupt Enable Register (SDIOIEN).............................................................. 1145
25.4.21 SDIO Interrupt Status Register (SDIOIST)............................................................... 1145
25.4.22 MMC FIFO Control Register (MMCFIFOCTL) ........................................................... 1146
26 Real-Time Clock (RTC)..................................................................................................... 1147
26.1 Introduction............................................................................................................... 1148
26.1.1 Purpose of the Peripheral.................................................................................... 1148
26.1.2 Features........................................................................................................ 1148
26.1.3 Block Diagram................................................................................................. 1148
26.2 Architecture .............................................................................................................. 1149
26.2.1 Clock Source................................................................................................... 1149
26.2.2 Signal Descriptions............................................................................................ 1149
26.2.3 Isolated Power Supply........................................................................................ 1149
26.2.4 Operation....................................................................................................... 1150

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26.2.5 Interrupt Requests ............................................................................................ 1152
26.2.6 Register Protection Against Spurious Writes.............................................................. 1153
26.2.7 General-Purpose Scratch Registers........................................................................ 1154
26.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) .............................. 1154
26.2.9 Emulation Modes of the Real-Time Clock ................................................................. 1154
26.2.10 Reset Considerations ....................................................................................... 1154
26.3 Registers ................................................................................................................. 1155
26.3.1 Second Register (SECOND)................................................................................. 1156
26.3.2 Minute Register (MINUTE)................................................................................... 1156
26.3.3 Hour Register (HOUR) ....................................................................................... 1157
26.3.4 Day of the Month Register (DAY)........................................................................... 1158
26.3.5 Month Register (MONTH).................................................................................... 1158
26.3.6 Year Register (YEAR) ........................................................................................ 1159
26.3.7 Day of the Week Register (DOTW)......................................................................... 1159
26.3.8 Alarm Second Register (ALARMSECOND) ............................................................... 1160
26.3.9 Alarm Minute Register (ALARMMINUTE).................................................................. 1160
26.3.10 Alarm Hour Register (ALARMHOUR)..................................................................... 1161
26.3.11 Alarm Day of the Month Register (ALARMDAY) ........................................................ 1162
26.3.12 Alarm Month Register (ALARMMONTH) ................................................................. 1163
26.3.13 Alarm Year Register (ALARMYEAR)...................................................................... 1163
26.3.14 Control Register (CTRL).................................................................................... 1164
26.3.15 Status Register (STATUS) ................................................................................. 1165
26.3.16 Interrupt Register (INTERRUPT) .......................................................................... 1166
26.3.17 Compensation (LSB) Register (COMPLSB) ............................................................. 1167
26.3.18 Compensation (MSB) Register (COMPMSB)............................................................ 1168
26.3.19 Oscillator Register (OSC)................................................................................... 1169
26.3.20 Scratch Registers (SCRATCH0-SCRATCH2) ........................................................... 1170
26.3.21 Kick Registers (KICK0R, KICK1R) ........................................................................ 1170
27 Serial Peripheral Interface (SPI) ........................................................................................ 1171
27.1 Introduction............................................................................................................... 1172
27.1.1 Purpose of the Peripheral.................................................................................... 1172
27.1.2 Features........................................................................................................ 1172
27.1.3 Functional Block Diagram.................................................................................... 1173
27.1.4 Industry Standard(s) Compliance Statement.............................................................. 1173
27.2 Architecture .............................................................................................................. 1174
27.2.1 Clock............................................................................................................ 1174
27.2.2 Signal Descriptions............................................................................................ 1174
27.2.3 Operation Modes.............................................................................................. 1174
27.2.4 Programmable Registers..................................................................................... 1175
27.2.5 Master Mode Settings ........................................................................................ 1176
27.2.6 Slave Mode Settings.......................................................................................... 1178
27.2.7 SPI Operation: 3-Pin Mode .................................................................................. 1179
27.2.8 SPI Operation: 4-Pin with Chip Select Mode ............................................................. 1180
27.2.9 SPI Operation: 4-Pin with Enable Mode ................................................................... 1182
27.2.10 SPI Operation: 5-Pin Mode................................................................................. 1184
27.2.11 Data Formats................................................................................................. 1186
27.2.12 Interrupt Support............................................................................................. 1189
27.2.13 DMA Events Support........................................................................................ 1190
27.2.14 Robustness Features ....................................................................................... 1190
27.2.15 Reset Considerations ....................................................................................... 1192
27.2.16 Power Management......................................................................................... 1192
27.2.17 General-Purpose I/O Pin.................................................................................... 1193
27.2.18 Emulation Considerations .................................................................................. 1193

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27.2.19 Initialization ................................................................................................... 1193
27.2.20 Timing Diagrams............................................................................................. 1194
27.3 Registers ................................................................................................................. 1200
27.3.1 SPI Global Control Register 0 (SPIGCR0)................................................................. 1200
27.3.2 SPI Global Control Register 1 (SPIGCR1)................................................................. 1201
27.3.3 SPI Interrupt Register (SPIINT0)............................................................................ 1203
27.3.4 SPI Interrupt Level Register (SPILVL)...................................................................... 1205
27.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1206
27.3.6 SPI Pin Control Register 0 (SPIPC0) ...................................................................... 1208
27.3.7 SPI Pin Control Register 1 (SPIPC1)....................................................................... 1209
27.3.8 SPI Pin Control Register 2 (SPIPC2)....................................................................... 1210
27.3.9 SPI Pin Control Register 3 (SPIPC3)....................................................................... 1211
27.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1212
27.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1213
27.3.12 SPI Transmit Data Register 0 (SPIDAT0)................................................................ 1214
27.3.13 SPI Transmit Data Register 1 (SPIDAT1)................................................................ 1215
27.3.14 SPI Receive Buffer Register (SPIBUF)................................................................... 1216
27.3.15 SPI Emulation Register (SPIEMU) ........................................................................ 1218
27.3.16 SPI Delay Register (SPIDELAY) .......................................................................... 1219
27.3.17 SPI Default Chip Select Register (SPIDEF).............................................................. 1222
27.3.18 SPI Data Format Registers (SPIFMTn)................................................................... 1223
27.3.19 SPI Interrupt Vector Register 1 (INTVEC1) .............................................................. 1225
28 64-Bit Timer Plus ............................................................................................................ 1226
28.1 Introduction............................................................................................................... 1227
28.1.1 Purpose of the Peripheral.................................................................................... 1227
28.1.2 Features........................................................................................................ 1227
28.1.3 Block Diagram................................................................................................. 1228
28.1.4 Industry Standard Compatibility Statement................................................................ 1228
28.1.5 Architecture – General-Purpose Timer Mode ............................................................. 1228
28.1.6 Architecture – Watchdog Timer Mode...................................................................... 1240
28.1.7 Reset Considerations......................................................................................... 1242
28.1.8 Interrupt Support .............................................................................................. 1242
28.1.9 DMA Event Support........................................................................................... 1242
28.1.10 TM64P_OUT Event Support ............................................................................... 1243
28.1.11 Interrupt/DMA Event Generation Control and Status ................................................... 1244
28.1.12 Power Management......................................................................................... 1244
28.1.13 Emulation Considerations .................................................................................. 1244
28.2 Registers ................................................................................................................. 1245
28.2.1 Revision ID Register (REVID) ............................................................................... 1247
28.2.2 Emulation Management Register (EMUMGT)............................................................. 1247
28.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN)............................................ 1248
28.2.4 GPIO Data and Direction Register (GPDATGPDIR) ..................................................... 1249
28.2.5 Timer Counter Registers (TIM12 and TIM34) ............................................................. 1250
28.2.6 Timer Period Registers (PRD12 and PRD34)............................................................. 1251
28.2.7 Timer Control Register (TCR) ............................................................................... 1252
28.2.8 Timer Global Control Register (TGCR)..................................................................... 1254
28.2.9 Watchdog Timer Control Register (WDTCR).............................................................. 1255
28.2.10 Timer Reload Register 12 (REL12) ....................................................................... 1256
28.2.11 Timer Reload Register 34 (REL34) ....................................................................... 1256
28.2.12 Timer Capture Register 12 (CAP12)...................................................................... 1257
28.2.13 Timer Capture Register 34 (CAP34)...................................................................... 1257
28.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) .......................................... 1258
29 Universal Asynchronous Receiver/Transmitter (UART) ....................................................... 1260

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29.1 Introduction............................................................................................................... 1261
29.1.1 Purpose of the Peripheral.................................................................................... 1261
29.1.2 Features........................................................................................................ 1261
29.1.3 Functional Block Diagram.................................................................................... 1261
29.1.4 Industry Standard(s) Compliance Statement.............................................................. 1261
29.2 Peripheral Architecture ................................................................................................. 1263
29.2.1 Clock Generation and Control............................................................................... 1263
29.2.2 Signal Descriptions............................................................................................ 1265
29.2.3 Pin Multiplexing................................................................................................ 1265
29.2.4 Protocol Description .......................................................................................... 1265
29.2.5 Operation....................................................................................................... 1267
29.2.6 Reset Considerations......................................................................................... 1271
29.2.7 Initialization..................................................................................................... 1271
29.2.8 Interrupt Support .............................................................................................. 1271
29.2.9 DMA Event Support........................................................................................... 1273
29.2.10 Power Management......................................................................................... 1273
29.2.11 Emulation Considerations .................................................................................. 1273
29.2.12 Exception Processing ....................................................................................... 1273
29.3 Registers ................................................................................................................. 1274
29.3.1 Receiver Buffer Register (RBR)............................................................................. 1275
29.3.2 Transmitter Holding Register (THR)........................................................................ 1276
29.3.3 Interrupt Enable Register (IER) ............................................................................. 1277
29.3.4 Interrupt Identification Register (IIR)........................................................................ 1278
29.3.5 FIFO Control Register (FCR)................................................................................ 1279
29.3.6 Line Control Register (LCR) ................................................................................. 1281
29.3.7 Modem Control Register (MCR)............................................................................. 1283
29.3.8 Line Status Register (LSR) .................................................................................. 1284
29.3.9 Modem Status Register (MSR).............................................................................. 1287
29.3.10 Scratch Pad Register (SCR) ............................................................................... 1288
29.3.11 Divisor Latches (DLL and DLH)............................................................................ 1288
29.3.12 Revision Identification Registers (REVID1 and REVID2) .............................................. 1290
29.3.13 Power and Emulation Management Register (PWREMU_MGMT) ................................... 1291
29.3.14 Mode Definition Register (MDR)........................................................................... 1292
30 Universal Serial Bus OHCI Host Controller......................................................................... 1293
30.1 Introduction............................................................................................................... 1294
30.1.1 Purpose of the Peripheral.................................................................................... 1294
30.2 Architecture .............................................................................................................. 1295
30.2.1 Clock and Reset .............................................................................................. 1295
30.2.2 Open Host Controller Interface Functionality.............................................................. 1296
30.2.3 Differences From OHCI Specification for USB............................................................ 1296
30.2.4 Implementation of OHCI Specification for USB1.1 ....................................................... 1297
30.2.5 OHCI Interrupts................................................................................................ 1298
30.2.6 USB1.1 Host Controller Access to System Memory...................................................... 1298
30.2.7 Physical Addressing .......................................................................................... 1298
30.3 Registers ................................................................................................................. 1299
30.3.1 OHCI Revision Number Register (HCREVISION) ........................................................ 1300
30.3.2 HC Operating Mode Register (HCCONTROL)............................................................ 1300
30.3.3 HC Command and Status Register (HCCOMMANDSTATUS).......................................... 1302
30.3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS)........................................... 1303
30.3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) ............................................... 1304
30.3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE).............................................. 1305
30.3.7 HC HCAA Address Register (HCHCCA)................................................................... 1306
30.3.8 HC Current Periodic Register (HCPERIODCURRENTED).............................................. 1306

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30.3.9 HC Head Control Register (HCCONTROLHEADED) .................................................... 1307
30.3.10 HC Current Control Register (HCCONTROLCURRENTED)........................................... 1307
30.3.11 HC Head Bulk Register (HCBULKHEADED) ............................................................ 1308
30.3.12 HC Current Bulk Register (HCBULKCURRENTED) .................................................... 1308
30.3.13 HC Head Done Register (HCDONEHEAD) .............................................................. 1309
30.3.14 HC Frame Interval Register (HCFMINTERVAL)......................................................... 1309
30.3.15 HC Frame Remaining Register (HCFMREMAINING) .................................................. 1310
30.3.16 HC Frame Number Register (HCFMNUMBER) ......................................................... 1310
30.3.17 HC Periodic Start Register (HCPERIODICSTART)..................................................... 1311
30.3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD)............................................. 1311
30.3.19 HC Root Hub A Register (HCRHDESCRIPTORA)...................................................... 1312
30.3.20 HC Root Hub B Register (HCRHDESCRIPTORB)...................................................... 1313
30.3.21 HC Root Hub Status Register (HCRHSTATUS)......................................................... 1314
30.3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1)..................................... 1315
30.3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2)..................................... 1317
31 Universal Serial Bus 2.0 (USB) Controller .......................................................................... 1319
31.1 Introduction............................................................................................................... 1320
31.1.1 Purpose of the Peripheral.................................................................................... 1320
31.1.2 Features........................................................................................................ 1320
31.1.3 Functional Block Diagram.................................................................................... 1320
31.1.4 Industry Standard(s) Compliance Statement.............................................................. 1321
31.2 Architecture .............................................................................................................. 1321
31.2.1 Clock Control .................................................................................................. 1321
31.2.2 Signal Descriptions............................................................................................ 1323
31.2.3 Indexed and Non-Indexed Registers ....................................................................... 1323
31.2.4 USB PHY Initialization........................................................................................ 1324
31.2.5 VBUS Voltage Sourcing Control ............................................................................ 1324
31.2.6 Dynamic FIFO Sizing......................................................................................... 1324
31.2.7 USB Controller Host and Peripheral Modes Operation .................................................. 1325
31.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ............................ 1361
31.2.9 Test Modes..................................................................................................... 1385
31.2.10 Reset Considerations ....................................................................................... 1387
31.2.11 Interrupt Support............................................................................................. 1387
31.2.12 DMA Event Support ......................................................................................... 1387
31.2.13 Power Management......................................................................................... 1387
31.3 Use Cases................................................................................................................ 1388
31.3.1 User Case 1: Example of How to Initialize the USB Controller ......................................... 1388
31.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode................. 1392
31.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode........................ 1393
31.3.4 User Case 4: Example of How to Program the USB DMA Controller.................................. 1395
31.4 Registers ................................................................................................................. 1400
31.4.1 Revision Identification Register (REVID)................................................................... 1407
31.4.2 Control Register (CTRLR).................................................................................... 1407
31.4.3 Status Register (STATR)..................................................................................... 1408
31.4.4 Emulation Register (EMUR) ................................................................................. 1408
31.4.5 Mode Register (MODE) ...................................................................................... 1409
31.4.6 Auto Request Register (AUTOREQ) ....................................................................... 1411
31.4.7 SRP Fix Time Register (SRPFIXTIME) .................................................................... 1412
31.4.8 Teardown Register (TEARDOWN).......................................................................... 1412
31.4.9 USB Interrupt Source Register (INTSRCR) ............................................................... 1413
31.4.10 USB Interrupt Source Set Register (INTSETR).......................................................... 1414
31.4.11 USB Interrupt Source Clear Register (INTCLRR)....................................................... 1415
31.4.12 USB Interrupt Mask Register (INTMSKR)................................................................ 1416

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31.4.13 USB Interrupt Mask Set Register (INTMSKSETR)...................................................... 1417
31.4.14 USB Interrupt Mask Clear Register (INTMSKCLRR) ................................................... 1418
31.4.15 USB Interrupt Source Masked Register (INTMASKEDR).............................................. 1419
31.4.16 USB End of Interrupt Register (EOIR).................................................................... 1420
31.4.17 Generic RNDIS EP1 Size Register (GENRNDISSZ1) ................................................. 1420
31.4.18 Generic RNDIS EP2 Size Register (GENRNDISSZ2) ................................................. 1421
31.4.19 Generic RNDIS EP3 Size Register (GENRNDISSZ3) ................................................. 1421
31.4.20 Generic RNDIS EP4 Size Register (GENRNDISSZ4) ................................................. 1422
31.4.21 Function Address Register (FADDR) ..................................................................... 1422
31.4.22 Power Management Register (POWER) ................................................................. 1423
31.4.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................ 1424
31.4.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)............................................. 1425
31.4.25 Interrupt Enable Register for INTRTX (INTRTXE) ...................................................... 1426
31.4.26 Interrupt Enable Register for INTRRX (INTRRXE)...................................................... 1426
31.4.27 Interrupt Register for Common USB Interrupts (INTRUSB)............................................ 1427
31.4.28 Interrupt Enable Register for INTRUSB (INTRUSBE) .................................................. 1428
31.4.29 Frame Number Register (FRAME) ........................................................................ 1428
31.4.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX).................. 1429
31.4.31 Register to Enable the USB 2.0 Test Modes (TESTMODE)........................................... 1429
31.4.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)........................... 1430
31.4.33 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) .......................... 1431
31.4.34 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ............................... 1432
31.4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR).......................... 1433
31.4.36 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ............................... 1434
31.4.37 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)........................... 1435
31.4.38 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) .......................... 1436
31.4.39 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ............................... 1437
31.4.40 Count 0 Register (COUNT0) ............................................................................... 1438
31.4.41 Receive Count Register (RXCOUNT)..................................................................... 1438
31.4.42 Type Register (Host mode only) (HOST_TYPE0) ...................................................... 1439
31.4.43 Transmit Type Register (Host mode only) (HOST_TXTYPE) ......................................... 1439
31.4.44 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .......................................... 1440
31.4.45 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................ 1440
31.4.46 Receive Type Register (Host mode only) (HOST_RXTYPE) ......................................... 1441
31.4.47 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................ 1442
31.4.48 Configuration Data Register (CONFIGDATA) ........................................................... 1443
31.4.49 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)......................................... 1444
31.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)......................................... 1444
31.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)......................................... 1445
31.4.52 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)......................................... 1445
31.4.53 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)......................................... 1446
31.4.54 Device Control Register (DEVCTL) ....................................................................... 1446
31.4.55 Transmit Endpoint FIFO Size (TXFIFOSZ)............................................................... 1447
31.4.56 Receive Endpoint FIFO Size (RXFIFOSZ)............................................................... 1447
31.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR)...................................................... 1448
31.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) ...................................................... 1448
31.4.59 Hardware Version Register (HWVERS) .................................................................. 1449
31.4.60 Transmit Function Address (TXFUNCADDR)............................................................ 1450
31.4.61 Transmit Hub Address (TXHUBADDR)................................................................... 1450
31.4.62 Transmit Hub Port (TXHUBPORT)........................................................................ 1450
31.4.63 Receive Function Address (RXFUNCADDR) ............................................................ 1451
31.4.64 Receive Hub Address (RXHUBADDR) ................................................................... 1451
31.4.65 Receive Hub Port (RXHUBPORT) ........................................................................ 1451

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31.4.66 CDMA Revision Identification Register (DMAREVID) .................................................. 1452
31.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)................................ 1452
31.4.68 CDMA Emulation Control Register (DMAEMU) ......................................................... 1453
31.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3])............... 1453
31.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3])............... 1454
31.4.71 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]-
RXHPCRA[3])................................................................................................... 1455
31.4.72 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]-
RXHPCRB[3])................................................................................................... 1456
31.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL)............................................ 1457
31.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63])................................... 1457
31.4.75 Queue Manager Revision Identification Register (QMGRREVID) .................................... 1459
31.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................ 1459
31.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0)................... 1460
31.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1)................... 1461
31.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2)................... 1462
31.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3)................... 1463
31.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) .................. 1463
31.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .............................. 1464
31.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) .................. 1464
31.4.84 Queue Manager Queue Pending Register 0 (PEND0) ................................................. 1465
31.4.85 Queue Manager Queue Pending Register 1 (PEND1) ................................................. 1465
31.4.86 Queue Manager Memory Region RBase Address Registers (QMEMRBASE[0]-
QMEMRBASE[15])............................................................................................. 1466
31.4.87 Queue Manager Memory Region RControl Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ... 1467
31.4.88 Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]).............................. 1468
31.4.89 Queue Manager Queue NStatus Register A (QSTATA[0]-QSTATA[63]) ........................... 1469
31.4.90 Queue Manager Queue NStatus Register B (QSTATB[0]-QSTATB[63]) ........................... 1469
31.4.91 Queue Manager Queue NStatus Register C (QSTATC[0]-QSTATC[63])........................... 1470
Revision History ...................................................................................................................... 1471