Texas Instruments ADS528 Series User manual

ADS528x EVM User's Guide
User's Guide
January 2008
SLAU205

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Contents
1 Overview .................................................................................................................... 51.1 Purpose............................................................................................................ 51.2 EVM Basic Functions ............................................................................................ 61.3 ADS528x EVM Quick Start Procedure ........................................................................ 72 Circuit Description ...................................................................................................... 82.1 Schematic Diagram .............................................................................................. 82.2 Circuit Function ................................................................................................... 83 TI ADC SPI Control Interface ....................................................................................... 103.1 Installing the ADC SPI Control Software .................................................................... 103.2 Using the TI ADC SPI Interface Software ................................................................... 104 ADC Evaluation ......................................................................................................... 134.1 Hardware Selection ............................................................................................ 134.2 Coherent Input Frequency Selection ......................................................................... 145 Errata ....................................................................................................................... 155.1 Silkscreen Errata ............................................................................................... 156 Physical Description .................................................................................................. 166.1 PCB Layout ...................................................................................................... 166.2 Bill of Materials .................................................................................................. 206.3 PCB Schematics ................................................................................................ 23
Important Notices ............................................................................................................... 28
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List of Figures
1 ADS5281 EVM ............................................................................................................... 62 TI ADC SPC Interface Screen ........................................................................................... 103 Top Silkscreen .............................................................................................................. 164 Ground Plane ............................................................................................................... 175 Power Plane ................................................................................................................ 186 Bottom Silkscreen .......................................................................................................... 197 EVM Schematics (Sheet 1 of 5) .......................................................................................... 238 EVM Schematics (Sheet 2 of 5) .......................................................................................... 249 EVM Schematics (Sheet 3 of 5) .......................................................................................... 2510 EVM Schematics (Sheet 4 of 5) .......................................................................................... 2611 EVM Schematics (Sheet 5 of 5) .......................................................................................... 27
List of Tables
1 Three-Pin Jumper List ....................................................................................................... 72 EVM Power-Supply Options ................................................................................................ 83 ADS528X Frequently Used Registers ................................................................................... 124 Bill of Materials ............................................................................................................. 20
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1 Overview
1.1 Purpose
User's GuideSLAU205 – January 2008
This preliminary user's guide gives a general overview of the ADS5281/82/87 (ADS528X) QFN evaluationmodule (EVM) and provides a general description of the features and functions to be considered whileusing this module. The EVM is pictured in Figure 1 .
The EVM provides a platform for evaluating the eight-channel ADS528X analog-to-digital converter (ADC)under various signal, reference, and supply conditions. This document should be used in combination withthe EVM schematic diagram supplied. The ADS5281 and ADS5282 are 12-bit ADCs, whereas theADS5287 is a 10-bit ADC.
Windows is a trademark of Microsoft Corporation.On Semiconductor is a trademark of Semiconductor Components Industries, L.L.C.Xilinx is a trademark of Xilinx, Inc.
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1.2 EVM Basic Functions
Overview
Figure 1. ADS5281 EVM
Eight analog inputs to the ADC are provided via external SMA connectors.
The EVM provides an external SMA connector for input of the ADC clock. The ADC can be clocked usingeither a single-ended or differential clock. Provisions are made on the EVM to allow users to evaluate theADC using a single-ended PECL clock and a differential transformer-coupled clock.
Digital output from the EVM is via a high-speed, high-density Samtec output header. The digital outputconnector mates directly to the TSW1200 Rev B or through an adapter to the TI ADSDeSer-50EVM, bothof which deserialize the serial data stream into parallel CMOS data.
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADCanalog and ADC digital supplies and for the auxiliary circuits.
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1.3 ADS528x EVM Quick Start Procedure
Overview
The ADS528x EVM provides a flexible means of evaluating the ADS528x in a number of modes ofoperation. A basic setup procedure that can be used as a board confidence check is as follows:1. Verify all jumper settings against the schematic jumper list in Table 1 .
Table 1. Three-Pin Jumper List
JUMPER FUNCTION LOCATION: PINS 1–2 LOCATION: PINS 2–3 DEFAULT
JP2 ADC internal or external reference ADC internal reference ADC external reference 1–2selectionJP3 (SMT) EVM clock input selection Transformer coupled Single-ended PECL 1–2JP4 (SMT) ADC CLKP Transformer Single-ended PECL 1–2JP5 (SMT) ADC CLKM Transformer GND 1–2JP8 Selects power management ADC powered by LDO (3.3 V) ADC powered by J4 (3.3 V) 1–2configurationJP9 Selects power management ADC powered by LDO (1.8 V) ADC powered by J5 (1.8 V) 1–2configuration
2. Connect a 5-V supply to J1 and its return to J2.3. Switch power supplies on.4. Using a function generator with 50- Ωoutput, generate a 0-V offset, 1.5-Vpp sine-wave clock into J26.The frequency of the clock must be within the specification for the device speed grade.5. Use a frequency generator with a 50- Ωoutput to provide a 5-MHz, 0-V offset, –1-dBFS-amplitudesine-wave signal into J9. This provides a transformer-coupled differential input signal to the ADC.6. Connect the USB cable, open the PC software and provide a reset command. For first-time use, seeSection 3.1 for installation instructions.7. Connect J8 to the ADS5281DeSerAdapter+ADSDeser-50EVM or TSW1200 deserializer card toevaluate the ADC digital data using a logic analyzer.
Note: Software Operation: Users must use the accompanying software to issue a reset commandbefore taking measurements. In addition to providing the ADS528X with the initializationregister writes detailed in the data sheet, the accompanying software also sets the state ofADC pins ADCRESET and PD. Failure to do so can cause improper operation.
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2 Circuit Description
2.1 Schematic Diagram
2.2 Circuit Function
2.2.1 Power
2.2.2 Clock Input
2.2.3 External References
Circuit Description
The schematic diagram for the EVM is in Section 6.3 .
The following sections describe the function of individual circuits. Refer to the relevant data sheet fordevice operating characteristics.
Power is supplied to the EVM via banana jack sockets. By default, the EVM is configured to use a powermanagement solution to supply the ADC and analog and digital power supplies, allowing users to powerthe board with a single 5-V power supply. The ADC power management solution is based on TI'sTPS77533 and TPS73218, which supply 3.3 V and 1.8 V, respectively. In addition, the EVM offers thecapability to supply to the ADC independent 3.3-V analog and 1.8-V digital supplies. The circuit boarduses only one ground plane, and the heat slug is tied to ground with multiple vias to provide for thermaldissipation. Table 2 offers a snapshot of the power-supply options.
Table 2. EVM Power-Supply Options
EVM Banana Jack DESCRIPTION
J1 Auxiliary circuit 5-V digital supply: PECL driver and USB circuitryJ2 Single ground planeJ4 ADS528x 3.3-V analog supply (only active when JP8 = 2–3)J5 ADS528x 1.8-V digital supply (only active when JP9 = 2–3)
A single-ended square or sinusoidal clock input should be applied to J26. The clock frequency should notexceed the maximum speed rating found in the data sheet. Several different clocking options exist to allowflexible evaluation of the ADC.
In the default case, a single-ended clock is converted to a differential clock using a Mini-Circuits TC1-1Ttransformer. When using this option, the ADC should be configured in differential clock mode by writing0x8001 to ADC register address 0x42. By default, after a software reset this option is asserted to coincidewith the EVM default.
A second EVM option allows the ADC to be configured in single-ended mode. This is provided to the ADCusing an On Semiconductor™ MC100EPT21 amplifier, which provides for sine-wave to square-waveconversion. This configuration can be used for both ADS528X and ADS527X devices. To use this mode,use the surface-mount jumpers JP3, JP4, and JP5, and configure each one of them to have positions 2–3shorted.
The EVM offers the ability to force external references to the ADC. By default, the ADC is configured touse the references generated internal to the ADC. To force the ADC to use external references, usersmust short JP2 pads 2–3, which in turn grounds the INT/EXT pin of the ADC. Users can then use J6 pin 1to force a REFB and pin 3 to force a REFT voltage. GND should be connected to J6 pin 2.
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2.2.4 Analog Inputs
2.2.5 Digital Outputs
Circuit Description
The EVM provides eight analog inputs, using an SMA connector for each of the eight channels of theADC. SMA channel inputs are J9, J10, J13, J14, J17, J18, J21, and J22. By default, the ADC accepts asingle-ended input and translates it to a differential signal using a Mini Circuits TC1-1T transformer. TheADC inputs are dc-biased by feeding the ADC VCM voltage to the transformer center tap on thesecondary windings. Provisions have also been made on the EVM to allow for differential inputs using twoSMAs per input channel.
The serial LVDS digital outputs can be accessed through the J8 output connector. The EVM is designedto be interfaced to the TI TSW1200 Rev B deserializer card, which plugs into J8. In addition, the EVM canbe interfaced to the ADSDeSer-50EVM using a translation card, the ADS5281DeSerAdapter. Both theTSW1200 Rev B and the ADSDeSer-50EVM contain the required parallel 100- Ωtermination resistor thatmust be placed at the receiver to terminate each LVDS data pair properly.
Note: TSW1200 Rev B: Users wishing to use the TSW1200 for deserialization should note that theminimium ADC sampling frequency this can be operated at is 32 MHz. The TSW1200 uses adigital clock manager (DCM) with a minimium operational frequency of 32 MHz.
Full documentation on the TI ADSDeSer-50EVM deserializer is found in the ADSDeSer-50EVM EvaluationModule User's Guide (SBAU091 ) and Connecting Xilinx FPGAs to Texas Instruments ADS527x SeriesADCs, Xilinx™ application report XAPP774 . The VHDL deserializer source code can be found on theXilinx Web site.
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3 TI ADC SPI Control Interface
3.1 Installing the ADC SPI Control Software
3.2 Using the TI ADC SPI Interface Software
TI ADC SPI Control Interface
This section describes the software designed to communicate with the ADC three-wire SPI interface. Theinformation is to be used in conjunction with the device data sheet, which explains the valid registers ofthe device.
The ADC SPI control software can be installed on a personal computer by running the setup.exe filelocated on the CD. This file installs the graphical user interface (GUI) along with the USB drivers neededto communicate to the USB port that resides on the EVM. After the software is installed and the USBcable has been plugged in for the first time, the user is prompted to complete the installation of the USBdrivers. When prompted, users should allow the Windows™ operating system to search for device drivers,and it should automatically find the TI ADC SPI interface drivers. See Figure 2 .
Note: First-time operation: For proper installation of the necessary USB drivers, users shouldinstall the accompanying software before connecting the USB cable to the EVM for the firsttime. Not doing so could cause problems in communicating to the EVM.
Figure 2. TI ADC SPC Interface Screen
Once the software is installed and the USB cable is connected, three primary modes of operating thesoftware are available: SPI register write, SPI register write using a script file, and ADS528X frequentlyused registers.
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3.2.1 SPI Register Write
3.2.2 SPI Register Write Using a Script File
3.2.2.1 ADS528X Frequently Used Registers
TI ADC SPI Control Interface
The most basic mode of operation allows full control of writing to individual register addresses. In the topleft corner of the interface screen (Figure 2 ), select the ADS528X ADC from the ADC SPI Protocoldrop-down list. Next, type the hexadecimal (hex) Address Bytes(s) in and Data Byte(s), which can befound in the device data sheet. When you are ready to send this command to the ADC, press Enter onyour keyboard or click the Send Data button. The graph indicator is updated with the patterns sent to theADC. The default inputs to both the Address Byte(s) and Data Byte(s) fields are hex inputs as designatedby the small xin the control. Users can change the default input style by clicking on the xto binary,decimal, octal, or hex. Multiple register writes can be written simply by changing the contents of theAddress Byte(s) and Data Byte(s) fields and pressing "Enter" or "Send Data" again.
For situations where the same multiple registers must be written on a frequent basis, users can easilysave a script file representing all of the register writes they have performed after a Reset has been issuedby simply clicking on the Save Script button. This can easily be loaded at a later time by using the LoadScript button. When ready to write the contents of the script file to the ADC, users can press the LoadScript button and be prompted for the file location of their script file. The commands are sent to the ADCwhen the user acknowledges the selection of the file. Please note that the graph indicator and thefrequently used register buttons are not updated when a script file is used.
Conversely, users can by using a text editor easily create a script file containing all ADC register writes.An example script file is located in the \\Install Directory\ADC SPI Control\ScriptFiles\ADS5281_Init.reg_ADS528X. Users who wish to take advantage of writing their own script filesshould start by using the ADS5281_Init.reg_ADS528X as a template file. When editing script filesmanually, make sure there is no carriage return following the last register write.
For ease of use, several buttons have been added that allow one-click register writes of commonly usedfeatures found in Table 3 . These buttons represent a subset of the available features found on theADS528X. The buttons are found in the ADS528X tab, as these commands are specific to the ADS528XADC only. The software writes to the ADC both the contents of the associated address and data when thebutton is clicked. When the ADS528X Reset button is pressed, it issues a software reset to the ADC, andit resets the button values to match the contents inside of the ADC. The graph indicator plots the SPIcommands written to the ADC when a button has been pressed.
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TI ADC SPI Control Interface
Table 3. ADS528X Frequently Used Registers
Default Value Alternate Value Description
ADS528X Reset Issues a software reset and also sends the initializationroutine outlined in the data sheet. Furthermore, the clock isset to differential, which matches the default EVMconfiguration. A Reset should take place before anyevaluation is done.Standby: Off Standby: On Toggles the ADC standby.Powerdown: Off Powerdown: On Toggles the ADC power down.PD: Powerdown PD: Standby Assigns the ADS528X PD pin either a power-down orstandby function.Clock: Standby Clock: Differential Sets the ADC to accept either a single-ended or adifferential clock. By defualt the ADS528X EVM isconfigured for a differential clock.LSB first MSB first Toggles the ADC output format.Testmode: None Output = Ramp, Output = Deskew, Sets the ADC to ignore the analog input and to apply a testOutput = Synch pattern on the digital output.Duty Cycle Correction: Off Duty Cycle Correction: On Toggles the duty-cycle correction feature.Termination: Off Termination: On Enables the ability to provide a series source terminationon the output signals.ADCLK: None ADCLK: 260, 150, 94, 125, 80, 66, Changes the value of the source termination on ADCLK.55 ΩNote that Termination must be On for values to take effect.LCLK: None LCLK: 260, 150, 94, 125, 80, 66, Changes the value of the source termination on LCLK.55 ΩNote that Termination must be On for values to take effect.OUT: None OUT: 260, 150, 94, 125, 80, 66, Changes the value of the source termination on the outputs55 ΩNote that Termination must be On for values to take effect.ADCLK: 3.5 mA ADCLK: 0.5–7.5 mA Changes the output source current on ADCLK.LCLK: 3.5 mA LCLK: 0.5–7.5 mA Changes the output source current on LCLK.OUT: 3.5 mA OUT: 0.5–7.5 mA Changes the output source current on OUT.Power Down: Off (per channel Power Down: On (per channel On an individual-channel basis, allows the user to togglecontrol) control) power down.Swap Inputs: Off (per channel Swap Inputs: On (per channel On an individual-channel basis, allows the user to togglecontrol) control) power down.Low-Frequency Noise Low-Frequency Noise Suppression: On an individual-channel basis, allows the user to toggleSuppression: Off (per channel On (per channel control) the low-frequency noise-suppression mode.control)
Gain = 0 db–12 dB (per Gain = 0 db–12 dB (per channel On an individual-channel basis, allows the user to applychannel control) control) gain.
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4 ADC Evaluation
4.1 Hardware Selection
4.1.1 Analog Input Signal Generator
4.1.2 Clock Signal Generator
ADC Evaluation
This section describes how to set up a typical ADC evaluation system that is similar to what TI uses toperform testing for data-sheet generation. Consequently, the information in this section is generic in natureand is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal toneanalysis, which yields ADC data-sheet figures of merit such as signal-to-noise ratio (SNR) and spuriousfree dynamic range (SFDR).
To reveal the true performance of the ADC under evaluation, great care should be taken in selecting boththe ADC signal source and ADC clocking source.
When choosing the quality of the ADC analog input source, consider both harmonic distortion performanceof the signal generator and the noise performance of the source.
In many cases, the harmonic distortion performance of the signal generator is inferior to that of the ADC,and additional filtering is needed if users expect to reproduce the ADC SFDR numbers found in the datasheet. Users can easily evaluate the harmonic distortion of their signal generator by hooking it directly to aspectrum analyzer and measuring the power of the output signal and comparing that to the power of theinteger multiples of the output-signal frequency. If the harmonic distortion is worse than the ADC underevaluation, the ADC digitizes the performance of the signal generator and the true ADC SFDR is masked.To alleviate this, it is recommended that users provide additional LC filtering after the signal generatoroutput.
Another important metric when deciding on a signal generator is its noise performance. As with thedistortion performance, if the noise performance is worse than that of the ADC under evaluation, the ADCdigitizes the performance of the source. Noise can be broken into two components, broadband noise andclose-in phase noise. Broadband noise can be improved by the LC filter added to improve distortionperformance; however, the close-in phase noise typically cannot be improved by additional filtering.Therefore, when selecting an analog signal source, it is important to review the manufacturer'sphase-noise plots and take care to choose a signal generator with the best phase-noise performance.
Equally important in the high-performance ADC evaluation setup is the selection of the clocking source.Most modern ADCs, the ADS61xx included, accept either a sinusoidal or a square-wave clock input. Thekey metric in selecting a clocking source is selecting a source with the lowest jitter. This becomesincreasingly important as the ADC input frequency (f
in
) increases, because the ADC SNR evaluationsetups can become jitter-limited (t
j
) as shown by the following equation.
SNR (dBc) = 20 log (2 π×f
in
×t
j
(rms))
In theory, a square-wave source with femtosecond jitter would be ideal for an ADC evaluation setup.However, in practical terms, most commercially available square-wave generators offer jitter measured inpicoseconds, which is too great for high-resolution ADC evaluation setups. Therefore, most evaluationsetups rely on the ADC internal clock buffer to convert a sinusoidal input signal into an ultralow-jittersquare wave. When selecting a sinusoidal clocking source, it has been shown that phase noise has adirect impact on jitter performance. Consequently, great scrutiny should be applied to the phase-noiseperformance of the clocking signal generator. TI has found that high-Q monolithic crystal filters canimprove the phase noise of the signal generator, and these filters become essential elements of theevaluation setup when high ADC input frequencies are being evaluated.
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4.2 Coherent Input Frequency Selection
ADC Evaluation
Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fouriertransform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that thesignal must be continuous-time; however, this is impractical when looking at a finite set of ADC samples,usually collected from a logic analyzer. Consequently, users typically apply a window function to minimizethe time-domain discontinuities that arise when analyzing a finite set of samples. For ADC analysis,window functions have their own frequency signatures or lobes that distort both SNR and SFDRmeasurements of the ADC.
TI uses the concept of coherent sampling to work around the use of a window function. The centralpremise of coherent sampling entails that the input signal into the ADC is carefully chosen such that whena continuous-time signal is reconstructed from a finite sample set, no time-domain discontinuities exist. Toachieve this, the input frequency must be an integer multiple of the ratio of the ADC sample rate (f
s
) andthe number of samples collected from the logic analyzer (N
s
). The ratio of f
s
to N
s
is typically referred to asthe fundamental frequency (f
f
). Determining the ADC input frequency is a two-step process. First, theusers select the frequency of interest for evaluating the ADC; then, they divide this by the fundamentalfrequency. This typically yields a non-integer value, which should be rounded to the nearest odd,preferably prime, integer. Once that integer, or frequency bin (f
bin
), has been determined, users multiplythis with the fundamental frequency to obtain a coherent frequency to program into their ADC input signalgenerator. The procedure is summarized as follows.
f
f
= f
s
/N
s
f
bin
= Odd_round(f
desired
/f
f
)
Coherent frequency = f
f
×f
bin
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5 Errata
5.1 Silkscreen Errata
Errata
This section describes the known issues with Rev B of the EVM.
The JP2 silkscreen incorrectly identifies the internal (INT) and external (EXT) reference selection. TheADC internal reference is selected by shorting pins 1–2 on JP2, which corresponds to the silkscreendesignators of HI or EXT. This will be amended in Rev. C of the EVM.
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6 Physical Description
6.1 PCB Layout
K001
Physical Description
This section describes the physical characteristics and PCB layout of the EVM.
The EVM is constructed on a 4-layer, 0.062-inch (1.58-mm) thick PCB using FR-4 material. The individuallayers are shown in Figure 3 through Figure 6 . The layout features a common ground plane; however,similar performance can be had with careful layout using a split ground plane.
Figure 3. Top Silkscreen
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K002
Physical Description
Figure 4. Ground Plane
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K003
Physical Description
Figure 5. Power Plane
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K004
Physical Description
Figure 6. Bottom Silkscreen
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6.2 Bill of MaterialsPhysical Description
Table 4. Bill of Materials
Reference Not Installed Part Footprint Part Number Manufacturer Tolerance
C1, C3, C23, 33 µF TANT_B B45196H1336K2 Kemet 10%C25 09C2, C4, C24, 1 µF 603 ECJ-1VB0J105K Panasonic 10%C34
C7, C11 22 µF TANT_A B45196H1226K1 Kemet 10%09C8, C9, C10, 0.1 µF 603 ECJ- Panasonic 10%C12, C13, C14, 1VB1C104KC18, C20, C26,C27, C28, C30,C36, C37, C41,C43, C47, C49,C53, C55, C59,C60, C61, C72C15, C16, C17, 0.01 µF 603 06035C103KAT2 AVX 10%C22 AC29 10 µF 1206 ECJ- Panasonic 10%3YB1C106KC33 2.2 µF 603 ECJ-1VB0J225K Panasonic 10%C35, C38, C42, 10 pF 603 ECJ- Panasonic 0.5 pFC44, C48, C50, 1VC1H100DC54, C56C40, C39, C45 0.1 µF 402 ECJ-0EB1A104K Panasonic 10%C46, C51, C74, 0.1 µF SMD_0603 GRM188R71H10 Murata 10%C75 4KA93DC52 0.01 µF SMD_0603 C0603C103K1R Kemet 10%ACTUC57, C58 27 pF SMD_0603 GRM1885C2A27 Murata 5%0JA01DC73 10 µF TANT_A TAJA106K016R AVX 10%JP2, JP8, JP9 HEADER 3POS Short pins 1–2.1 CTR with shunt
connectors
DigiKey #S9000-NDCONN JUMPER S9000-ND DigiKeySHORTINGJP3, JP4, JP5 NO PART SMD_BRIDGE_ Short pins 1–20603 using 0- ΩresistorsJ1, J4, J5 RED ST-351A ALLIED
ELECTRONICSJ2 BLK ST-351B ALLIED
ELECTRONICSJ6 HEADER 4 JUMPER4J8 QTH-060-02-F- QTH-040-01-F- SamtecD-A D-DP-AJ9, J10, J13, SMA 142-0701-201 JohmsonJ14, J17, J18, ComponentsJ21, J22, J26J11, J12, J15, NOT SMA 142-0701-201 JohmsonJ16, J19, J20, INSTALLED ComponentsJ23, J24J25 CONN USB TYP 897-43-004-90- MilmaxB FEM 000000
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