Texas Instruments TPS65265 User manual

User’s Guide
TPS65265 Buck Converter Evaluation Module User's
Guide
ABSTRACT
This document presents the information required to operate the TPS65265 PMIC as well as the support
documentation including schematic, printed-circuit board (PCB) layout, hardware setup, and bill of materials.
Table of Contents
1 Background.............................................................................................................................................................................2
2 Schematic................................................................................................................................................................................3
3 Board Layout...........................................................................................................................................................................4
4 Bench Test Setup Conditions................................................................................................................................................ 7
4.1 Header Description and Jumper Placement...................................................................................................................... 7
5 Power-Up Procedure.............................................................................................................................................................. 9
6 Bill of Materials..................................................................................................................................................................... 10
7 Revision History................................................................................................................................................................... 10
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www.ti.com Table of Contents
SLVUAK9A – DECEMBER 2015 – REVISED MAY 2021
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1 Background
The TPS65265 PMIC is a triple 5-A/3-A/2-A output current, synchronous step-down (buck) converter with
an operational range of 4.5 to 17 V. The feedback voltage reference for each buck is 0.6 V. Each buck is
independent with dedicated enable and loop compensation. The TPS65265 supports PSM mode and FCC
mode.
As there are many possible options to set the converters, Table 1-1 presents the performance specification
summary for the EVM.
Table 1-1. Summary of Performance
Test Conditions Performance
VIN = 4.5 to 17 V
spa
fsw = 610 kHz
spa
(25°C ambient)
Buck1, 1.2 V, up to 5 A
spa
Buck2, 1.5 V, up to 3 A
spa
Buck3, 1.8 V, up to 2 A
The evaluation module is designed to provide access to the features of the TPS65265. Some modifications
can be made to this module to test performance at different input and output voltages, current and switching
frequency. Please contact the TI Field Applications Group for advice on these matters.
Background www.ti.com
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2 Schematic
Figure 2-1 illustrates the TPS65265EVM-705 EVM schematic.
0.047uF
C15
0.01uF
C26
0
R6
1
2
3
J6
22uF
C17
GND
GND
GND
0
R7
DNI
TP8
0.047uF
C22
0
R11
22uF
C23
GND
0
R12
DNI
TP11
GND
22uF
C3
22uF
C2
GND
0.047uF
C1
0
R1
J3
GND
TP9
TP10
J2
GND
TP6
TP7
J1
GND
TP1
TP3
EN1
GND
J5
GND
TP2
TP4
VIN
10.0k
R9
VOUT1 1.2V 5A
VOUT2 1.5V 3A
VOUT3 1.8V 2A
VIN 12V
VFB1
22uF
C18
GND
VFB2
VFB2
VFB3
22uF
C24
GND
VFB3
GND
0.01uF
C27
GND
1
2
3
J7
GND EN2
GND
1
2
3
J8
GND EN3
GND
10.0k
R16
20.0k
R17
EN1
EN2
EN3
GND
VIN
GND
15.0k
R10
DNI
R13
0
R22
V7V
1uF
C16
22uF
C8
1uF
C10
1uF
C11
82.5k
R15
PGOOD
82pF
C13
22pF
C12
22pF
C21
GND
22pF
C29
DNI
TP5
10.0k
R4
10.0k
R5
GND
VFB1
22pF
C19
GND
22pF
C25
GND
4.7uH
L2
4.7uH
L3
22uF
C5
DNI
C4
GND GND
DNI
C7
22uF
C6
GND GND
0
R2
1
2
3
J9
MODE
GND
V7V
DNI
C32
DNI
C34
DNI
C33
MODE
PG_DLY
PG_DLY
4
7,8 1,2,3
5,6, DNI
Q1
DNI
L4
DNI
L5
DNI
L6
DNI
C30
DNI
C31
GND
GND
PGOOD
VOUT1
VOUT2
VOUT1
VOUT2
SYNC
SYNC
DNI
J4
GND
DNI
TP12
DNI
TP14
VOUT4 1.8V 2AVo
Vo
GND
PGOOD
GND
GND
2.2uH
L1
V7V
1
PGOOD
2
EN1
3
EN2
4
EN3
5
FB2 6
COMP2 7
MODE
8
BST2 9
PGND2 10
LX2 11
PVIN2
12
PVIN3
13
LX3 14
PGND3 15
BST3 16
SQE_DLY
17
COMP3 18
FB3 19
ROSC
20
AGND 21
FB1 22
COMP1 23
PG_DLY
24
BST1 25
PGND1 26
PGND1 27
LX1 28
LX1 29
PVIN1
30
PVIN1
31
PSM
32
PAD
33
U1
TPS65265RHBR
10.0k
R27
DNI
TP15
DNI
TP16
TP13
22uF
C9
100k
R21
100k
R18
100k
R19
100k
R20
10.0k
R3
2700pF
C14
2700pF
C20
2700pF
C28
6.8k
R14
6.8k
R8
33k
R23
33k
R24
33k
R25
33k
R26
Figure 2-1. TPS65265EVM-705 Schematic
www.ti.com Schematic
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3 Board Layout
Figure 3-1 through Figure 3-5 illustrate the TPS65265EVM-705 PCB layout.
Figure 3-1. Component Placement (Top Layer)
Figure 3-2. Board Layout (Top Layer)
Board Layout www.ti.com
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Figure 3-3. Board Layout (Second Layer)
Figure 3-4. Board Layout (Third Layer)
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Figure 3-5. Board Layout (Bottom Layer)
Board Layout www.ti.com
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4 Bench Test Setup Conditions
4.1 Header Description and Jumper Placement
Figure 4-1 shows the jumper and pin placement on the TPS65265EVM-705 board.
Figure 4-1. TPS65265EVM-705 Header Description and Jumper Placement
Test points:
1. LX of VOUT1
2. LX of VOUT2
3. LX of VOUT3
VOUT1, VOUT2, VOUT3, VIN, PGOOD, PG_DLY, SYNC
Table 4-1. Input/Output Connection
# Function Description
J1 Buck1 Connector Output of Buck1
J2 Buck2 Connector Output of Buck2
J3 Buck3 Connector Output of Buck3
J5 VIN Connector Apply power supply to this connector
Table 4-2. Jumpers
# Function Placement Comment
J6 Buck1 enable (EN1) Connect EN1 to GND to disable VOUT1
spa
Connect EN1 to HIGH or leave open to enable VOUT1
J7 Buck2 enable (EN2) Connect EN2 to GND to disable VOUT2
spa
Connect EN2 to HIGH or leave open to enable VOUT2
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Table 4-2. Jumpers (continued)
# Function Placement Comment
J8 Buck3 enable (EN3) Connect EN3 to GND to disable VOUT3
spa
Connect EN3 to HIGH or leave open to enable VOUT3
J9 MODE Power sequencing mode control pin.
spa
Connect MODE pin to GND or HIGH, set the power sequence with
pre-defined power up and power down sequence.
spa
Leave open to set power up and down with dedicated enable pin.
Bench Test Setup Conditions www.ti.com
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5 Power-Up Procedure
Power-up with dedicated enable pin:
1. Apply 4.5 V–17 V to J5
2. Toggle J6 , J7, or J8 to enable VOUT1, VOUT2, and VOUT3, respectively
3. Apply loads to the output connectors
Six bucks power sequence schemes with the pre-defined power up and power down sequence, shown in Table
5-1.
1. Connect J9 to GND or high
2. Connect J6 to High(or Low), J7 to High(or Low)
3. Apply 4.5 V–18 V to J5
4. Toggle J8 to enable VOUT1, VOUT2, and VOUT3 (power up sequence shown in Table 5-1)
5. Apply loads to the output connectors
Table 5-1. Power Sequencing
Mode EN1 EN2 EN3 Start Sequencing Shutdown Sequencing
Low High High Used to start/stop bucks in
sequence
buck1→buck2→buck3 Buck3→buck2→buck1
Low Low High Buck2→buck1→buck3 Buck3→buck1→buck2
Low High Low Buck2→buck3→buck1 Buck1→buck3→buck2
High High High Buck1→buck3→buck2 Buck2→buck3→buck1
High Low High Buck3→buck1→buck2 Buck2→buck1→buck3
High High Low Buck3→buck2→buck1 Buck1→buck2→buck3
High/Low Low Low Reserved Reserved Reserved
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6 Bill of Materials
Table 6-1 lists the TPS65265EVM-705 BOM.
Table 6-1. TPS65265EVM-705 Bill of Materials
# Value Qty Designator Footprint Manufacturer Manufacturer Part Number Description
1 47nF 3 C8, C9, C17 0603 Generic CAP 47nF 50V CERAMIC X7R 0603
2 10nF 1 C7 0603 Generic CAP 10nF 50V CERAMIC X7R 0603
3 3.3nF 1 C4 0603 Generic CAP 3.3nF 50V CERAMIC X7R 0603
4 22uF 4 C10, C11, C12, C18 1206 Generic CAP 22uF 16V CERAMIC X5R 1206
5 22pF 3 C2, C3, C5 0603 Generic CAP 22pF 16V CERAMIC X7R 0603
6 82pF 1 C1 0603 Generic CAP 82pF 50V CERAMIC X7R 0603
7 4.7uF 2 C19, C20 0603 Generic CAP 4.7uF 50V CERAMIC X7R 0603
8 10uF 3 C13, C14, C15 1206 Generic CAP 10uF 16V CERAMIC X5R 1206
9 1uF 3 C6, C16, C21 0603 Generic CAP 1uF 50V CERAMIC X7R 0603
10 4.99K 1 R52 0603 Generic RES 4.99k OHM 1/10W 1% 0603 SMD
11 36.5K 1 R51 0603 Generic RES 36.5k OHM 1/10W 1% 0603 SMD
12 10K 1 R42 0603 Generic RES 10k OHM 1/10W 1% 0603 SMD
13 31.6K 1 R41 0603 Generic RES 31.6k OHM 1/10W 1% 0603 SMD
14 8.67K 1 R32 0603 Generic RES 8.67 OHM 1/10W 1% 0603 SMD
15 19.6K 1 R22 0603 Generic RES 19.6k OHM 1/10W 1% 0603 SMD
16 39K 2 R21, R31 0603 Generic RES 39k OHM 1/10W 1% 0603 SMD
17 51K 1 R10 0603 Generic RES 51k OHM 1/10W 1% 0603 SMD
18 100K 2 R8, R9 0603 Generic RES 100k OHM 1/10W 1% 0603 SMD
19 0 6 R2, R3, R4, R5, R6,
R7
0603 Generic RES 0k OHM 1/10W 1% 0603 SMD
20 20K 3 R1, R11, R12 0603 Generic RES 20k OHM 1/10W 1% 0603 SMD
21 4.7uH 3 L1, L2, L3 IND_744311470 Wurth Electronics
Inc
744311470 SMT power inductor
22(1) HEADER
3 PIN
6 JP1, JP2, JP3, JP4,
JP5, JP6
JMP0.3 Mil-Max 800-10-064-10-001000 Three Pin Header, Break SIPs into groups of 3
23 ED500/2
DS
8 J1, J2, J3, J4, J5, J6,
J7, J8
TB_2X5.0MM OnShore
Technology Inc
ED500/2DS Terminal Block, 2-pin, 15-A, 5.0mm
24 Test
Point
White
9 TP1, TP2, TP3, TP4,
TP5, TP6, TP8, TP9
TP Keystone 5002 TEST POINT PC MINI .040"D WHITE
25 Test
Point
Black
6 TP10, TP11, TP12,
TP13, TP14, TP15
TP Keystone 5001 TEST POINT PC MINI .040"D BLACK
26 6 Jumper, 2.54mm, open top, Applied on item 22
27(2) 4 3M SJ-5303 (CLEAR) BUMPON HEMISPHERE .44X.20 CLEAR
28 1 U1 RHB Texas
Instruments
TPS65262RHBR
(1) Item 22: split into 3 pins
(2) Install item 27 on bottom at corners
7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2015) to Revision A (May 2021) Page
• Updated user's guide title................................................................................................................................... 2
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
Bill of Materials www.ti.com
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