Texas Instruments MSP53C691 User manual

MSP53C691 Speech
Synthesizer
December 2000 MSDS Speech
User’s Guide
SPSU020

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TIdeemsnecessarytosupport thiswarranty. Specifictestingofallparameters ofeachdevice isnotnecessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated

How to Use This Manual
iii
Read This First
Preface
Read This First
About This Manual
This user’s guide provides information on the MSP53C691 mixed signal pro-
cessor. This information includes architecture overview, detailed architecture
description, assembly language instruction set, code development tools, and
customer information.
How to Use This Manual
This document contains the following chapters:
- Chapter 1—Introduction
- Chapter 2—MSP53C691 Hardware Description
- Chapter 3—MSP53C691 Software Description
- Chapter 4—MSP53C691 Timing Considerations
- Appendix A—Designing the Master Microcontroller Software
- Appendix B—FM Synthesis
- Appendix C—Editing Tools and Data Preparation
- Appendix D—Pitch and Speech Shifting for 6xx MELP
- Appendix E—Guidelines for Optimal TI Speech

Related Documentation From Texas Instruments
iv
Information About Cautions
This book contains cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
The information in a caution is provided for your protection. Please read each
caution carefully.
Related Documentation From Texas Instruments
SPSS023B Data sheet, MSP50C614
SPSU014 User’s guide, MSP50C614
SPSS028A Data sheet, MSP50C604
SPSU014 User’s guide, MSP50C604

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 MSP53C691 Device 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Pin Assignments and Description 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 DAC Information 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Algorithms Supported 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 MSP53C691 Hardware Description 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 MSP53C691 Interface Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Microprocessor Interface Description 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 4-Bit Mode 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 8-Bit Mode 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Read Operation by the Master 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Write Operation by the Master 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 MSP53C691 Device Initialization 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Microprocessor Interface Timing 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 MSP53C691 Software Description 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Software Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Commands and Data Streams 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Sequence of Command Codes and Data Streams 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Command Header 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Parameters 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Return Values 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Command Codes 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Description of the Command Codes 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Command Header 1—Configure Internal Registers 3-8. . . . . . . . . . . . . . . . . . . . . .
3.5.2 Command Header 2—Set/Clear I/O Ports, PD4 Through PD7 3-10. . . . . . . . . . . .
3.5.3 Command Header 3—Read Contents of I/O Ports 3-11. . . . . . . . . . . . . . . . . . . . . .
3.5.4 Command Header 4—Start Speaking 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Command Header 5—Stop Speaking 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Command Header 6—Adjust the Volume 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 Command Header 7—Return Buffer Status 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.8 Command Header 8—Initiate Sleep 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.9 Command Header 9—Receive FM Data 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.10 Command Header A—Perform Speed Shift or Pitch Shift 3-33. . . . . . . . . . . . . . . .
4 MSP53C691 Timing Considerations 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 General Constraints 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
4.2 MSP53C391 Timing Waveforms 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 CELP/MELP 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 MIX Mode 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Designing the Master Microcontroller Software A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B FM Synthesis B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Editing Tools and Data Preparation C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Pitch and Speed Shifting for 6xx MELP D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E Guidelines for Optimal TI Speech E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1–1 MSP53C691 Pin Assignments 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 MSP53C691 Interfacing Diagram—4-Bit Mode 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 MSP53C691 Interfacing Diagram—8-Bit Mode 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Data Transfer—Read 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Data Transfer—Write 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 MSP53C691 RESET Diagram 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Device Initialization 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Oscillator and PLL Connection 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 MSP53C691 Hardware Interface Connection 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 Program Flow for the Master Main Routine A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 Program Flow for an ISR Tied to the Falling Edge of OUTRDY A-4. . . . . . . . . . . . . . . . . . . . . .
A–3 Program Flow for an ISR Tied to the Falling Edge of INRDY to Play Mixed Mode A-5. . . . . .
A–4 Routine for Sending Data or Commands to the Slave A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Program Flow for ISR Tied to the Falling Edge of INRDY to Play CELP/MELP Only A-7. . . .
B–1 FM Conversion Process B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 MSP53C691 Signal Description 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Command Codes 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 Command Summary B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–1 Pitch Control D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–2 Speed Shifting Summary D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Introduction
This chapter briefly describes the features, hardware, and software of the
MSP53C691 speech synthesizer.
Topic Page
1.1 Description 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 MSP53C691 Device 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Pin Assignments and Description 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 D/A Information 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Algorithms Supported 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Description
1-2
1.1 Description
TheMSP53C691isa standard slave synthesizer fromTexasInstrumentsthat
accepts compressed speech data from other microprocessors/microcontrol-
lers and converts it to speech. This allows the TI MSP53C691 to be used with
a master microprocessor/microcontroller in various speech products, includ-
ing electronic learning aids, games, and toys. (When referring to the
MSP53C691 device in this guide, the terms slave and MSP53C691 are used
interchangeably, and the terms master and microcontroller are used inter-
changeably.)
The MSP53C691 supports several speech synthesis algorithms to permit
tradeoffs that meet the price performance requirements of different markets.
It also incorporates a single-channel FM synthesis routine for music genera-
tioncombinedwithcodebook-exitedlinear-predictive(CELP)codingormixed-
excitation linear prediction (MELP) coding.
The MSP53C691 is a special program that runs on the MSP50C604 device.
FormoreinformationabouttheMSP50C604,please refertothelatest version
of the MSP50C604 data sheet (literature number SPSS28A) and to the
M
SP50x6x User’s Guide (literature number: SPSU014).
1.2 Features
- The device incorporates a wide range of algorithms on one chip. This
rangeallowsusersto choose fromlowbitratetohigh-quality synthesizing
routines for their application. The following algorithms are included:
J MELP v 3.4 1.0 kbps—3.5 kbps (at 8 Khz sampling rate)
J CELP v3.4 3.0 kbps, 3.7 kbps, 4.5 kbps, 6.2 kbps, 7.7 kbps, and
11.2 kbps (at 8 kHz sampling rate)
J ADPCM
J Single-channel FM synthesis
J Single-channel FM with CELP or MELP (mixed mode)
- Six-level digital gain control
- Interrupt-driven data transfer for speech or command
- Four customer-configurable I/Os
- Option for four- or eight-bit data bus
J Eight-bit data bus with four control lines
J Four-bit data-bus with five control lines
- Low power (less than 10 µA) sleep mode for long battery life
J Three different sleep modes

MSP53C691 Device
1-3
Introduction
- A choice of oscillator control
J Theinternaloscillatorcanbecontrolledwitha1%resistorforlowcost,
or a standard 32.768-kHz crystal for higher precision.
- Speed and pitch shifting in MELP
- Stops speaking at any time (only in 4-bit mode)
- Supports sending commands to perform certain tasks while speaking
(only in 4-bit mode)
- Operating voltage 3 V–5.2 V
- Direct speaker drive, 32 Ω
- Available in die form or 64-pin LQFP package option
1.3 MSP53C691 Device
TheMSP53C691isoptimizedtosupportafour-bit-widedatatransferprotocol.
The MSP53C691 has two status bits and three control bits which control the
communication protocol between the master and the slave. The MSP53C691
also has one bit (data/command) which differentiates between command or
speech data feeding into the slave.
The MSP53C691 also supports the 8-bit wide data transfer but support for
commands is disabled. Switching between 4-bit mode or 8-bit mode is per-
mitted between speech data files.
MSP53C691
(4-bit mode) MSP53C691 (8-bit mode)
Number of data lines 4 8
Number of control lines 3 (strobe, R/W, data/command) 2 (strobe, R/W)
Number of status lines 2 (INRDY, OUTRDY) 2 (INRDY, OUTRDY)
Number of general-purpose I/O lines 4 4
Support for commands (while speaking) Yes No

Pin Assignments and Description
1-4
1.4 Pin Assignments and Description
Figure 1–1 shows the pin assignments for the MSP53C691. Table 1–1 pro-
vides pin functional descriptions.
Figure 1–1.MSP53C691 Pin Assignments
1718 19
VSS
DACP
VDD
DACM
VDD
PD4
PD5
PD6
PD7
DATA0
DATA1
DATA2
DATA3
DATA/COMMAND (DATA4)
DATA5
DATA6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
VDD
R/W
STROBE
OUTRDY
INRDY
TEST
SCANOUT
SYNC
SCANCLK
SCANIN
RESET
PLL
OSCIN
OSCOUT
VSS 21 22 23 24
NC NC
63 62 61 60 5964 58
NC NC NC NC NC NC NC
NC NC NC NC NC
NC NC NC NC NC NC
56 55 5457
25 26 27 28 29
53 52
NC
NC NC
51 50 49
30 31 32
NC
DATA7
NC NC NC
NC
MSP53C691
PM PACKAGE
(TOP VIEW)
VDD
VSS VSS
NC – No internal connection
NOTE: Pin 35 is DATA4 in 8-bit mode, or DATA/COMMAND in 4-bit mode.
Table 1–1.MSP53C691 Signal Description
NAME PIN
NO. PAD NO. I/O DESCRIPTION
INRDY 6 6 O An output signal from the slave to the microcontroller. A low signal
indicates that the MSP53C691 is ready to accept data or
command. A high signal indicates that the MSP53C691 is busy
and the microcontroller must not write any data or command to it.
OUTRDY 5 5 O An output signal from the slave to the microcontroller. A low signal
indicates that the MSP53C691 is ready to send data or command
to the microcontroller.
STROBE 4 4 I An input signal to the slave from the microcontroller. STROBE
sequences read or write operations in conjunction with the R/W
signal. This signal is pulsed high-low-high for read or write
operations sequencing.
R/W 3 3 I An input signal to the slave from the microcontroller. Read/write
select signal which is set high for read operations or set low for
write operations by the microcontroller.

Pin Assignments and Description
1-5
Introduction
Table 1–1. MSP53C691 Signal Description (Continued)
NAME PIN
NO. PAD NO. I/O DESCRIPTION
DATA0–DATA3 39–36 25–22 I/O Data bits 0 through 3 (in 4-bit or 8-bit mode)
DATA4 or
DATA/COMMAND 35 21 I/O Data bit 4 (in 8-bit mode) Data/command control bit (in 4-bit mode). Low signal indicates
command and high signal indicates data.
DATA5–DATA7 34–32 20–18 I/O Data bits 5 through 7 (8-bit mode only)
Not used (4-bit mode only)
PD4–PD7 43–40 29–26 I/O General-purpose I/O bus
Oscillator Reference Signals
OSCOUT 15 15 OOutput of resistor/crystal oscillator
OSCIN 14 14 IInput to resistor/crystal oscillator
PLL 13 13 OOutput of phase-lock-loop filter
Scan Port Control Signals‡
SCANIN 11 11 IScan port data input
SCANOUT 8 8 O Scan port data output
SCANCLK 10 10 IScan port clock
SYNC 9 9 I Scan port synchronization
TEST 7 7 I C604: test modes
‡NOTE: All these pins must be N.C.
DAC Sound Output
DACP 47 33 ODigital-to-analogoutput1(+) thatprovidesdirect speakerdrive
capability
DACM 45 31 ODigital-to-analogoutput 2(–) that providesdirectspeaker drive
capability
Initialization
RESET 12 12 IDevice initialization
Power Signals†
VDD 1, 2, 31,
44, 46†1, 2, 17, 30, 32†—Processor power, +5 V nominal supply voltage
VSS 16, 48,
49†, 64 16, 34†, 35, 36 —Ground pin
†Marked pins are VDD and VSS connections which service the DAC circuitry. These pins tend to sustain a higher current draw.
A dedicated decoupling capacitor across these pins is therefore required.

DAC Information
1-6
1.5 DAC Information
A two-pin push pull that can directly drive a 32-Ωspeaker is used in the
MSP53C691. Refer to the MSP50x6x Mixed Signal Processor Users Guide ,
literature number SPSU014, for more information on the D/A and amplifier
circuit.
1.6 Algorithms Supported
- MELP:Dataratesrangefrom1kbpsto~3.5kbpsatan8-kHzsamplerate.
- CELP: Data rates can be selected from 3 kbps to 11.2 kbps at an 8-kHz
sample rate.
- ADPCM
- FM: frequency modulation for one-channel musical instrument synthesis
- Mix mode: one channel FM synthesis with MELP or CELP

2-1
MSP53C691 Hardware Description
MSP53C691 Hardware Description
This chapter describes the MSP53C691 hardware, including interface, initial-
ization, and timing.
Topic Page
2.1 MSP53C691 Interface Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Microprocessor Interface Description 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Read Operation by the Master 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Write Operation by the Master 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 MSP53C691 Device Initialization 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Microprocessor Interface Timing 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

MSP53C691 Interface Overview
2-2
2.1 MSP53C691 Interface Overview
The MSP53C691 interfaces with the master microcontroller either in 4-bit or
in 8-bit mode.
The MSP53C691 and the master microcontroller transfer data across four
(DATA0–DATA3) or eight (DATA0–DATA7) data lines, depending upon which
mode the slave is in.
In either mode the transfer of data is controlled by the two control lines: R/W
and STROBE. When the MSP53C691 is ready to receive data from the
microcontroller, it sets INRDY low. The microcontroller sends data to the
MSP53C691bysettingR/WlowandthenpulsingSTROBEhigh-low-high.The
MSP53C691 latches the data at the rising edge of the STROBE pulse. The
MSP53C691 also sets INRDY high at the rising edge of the STROBE pulse.
SettingINRDYhighindicatesthattheMSP53C691isnot ready to receive any
more data.
When the MSP53C691 is ready to send data to the microcontroller, the
MSP53C691setsOUTRDYlow.Themicrocontrollerrespondsby settingR/W
high and then pulsing STROBE high-low-high. (The microcontroller latches
the data while STROBE is low.) This informs the slave that the data has been
written to the microcontroller. The MSP53C691 sets OUTRDY high at the ris-
ing edge of the STROBE pulse. Setting OUTRDY high indicates that the
MSP53C691 does not have data ready to send.
Both 4-bit and 8-bit modes are controlled by commands sent to the slave. A
separatebit(DATA4)isusedin4-bitmodetodifferentiatebetweenthespeech
data or command sent to the slave. This line is referred to as data/command
line. This is discussed in detail in the software overview section.

Microprocessor Interface Description
2-3
MSP53C691 Hardware Description
2.2 Microprocessor Interface Description
As mentioned in section 2.1, the MSP53C691 interfaces with the master mi-
crocontroller either in 4-bit or in 8-bit mode.
2.2.1 4-Bit Mode
The interface between the microcontroller and the MSP53C691 consists of
four control lines, two status lines, and four data lines.
The control lines are:
- STROBE
- R/W
- DATA/COMMAND
- RESET
The status lines are:
- INRDY
- OUTRDY
The speech data or command is transferred on lines:
- DATA0 through DATA3
Figure 2–1 shows the interfacing diagram.
Figure 2–1.MSP53C691 Interfacing Diagram—4-Bit Mode
Master MSP53C691
INRDY
OUTRDY
DATA(0–3) DATA(0–3)
4
4.7 kΩ
4.7 kΩ4.7 kΩ
VDD
100 kΩ
each
VDD
RESET
DATA/COMMAND
100 kΩ
R/W
STROBE
Note: STROBE: Active low strobe signal from microcontroller
R/W Read/write signal from microcontroller
RESET Active low reset signal from microcontroller
DATA0–DATA3 Data bits 0 through 3
PD4–PD7 General-purpose I/O bus
DACP Output to speaker/amplifier
DACM Output to speaker/amplifier
DATA/COMMAND This bit determines if the data sent by the
microcontroller is data or command.

Microprocessor Interface Description
2-4
2.2.2 8-Bit Mode
The interface between the microcontroller and the MSP53C691 consists of
three control lines, two status lines, and eight data lines.
The control lines are:
- STROBE
- R/W
- RESET
The status lines are:
- INRDY
- OUTRDY
The data/command lines are:
- DATA0 through DATA7
Figure 2–2 shows the interfacing diagram.
Figure 2–2.MSP53C691 Interfacing Diagram—8-Bit Mode
Master MSP53C691
INRDY
OUTRDY
DATA (0–7) DATA (0–7)
8
4.7 kΩ
4.7 kΩ4.7 kΩ
VDD
100 kΩ
each
VDD
RESET
R/W
STROBE
Note: STROBE: Active low strobe signal from microcontroller
R/W: Read/write signal from microcontroller
RESET Active low reset signal from microcontroller
INRDY: Active low indicates that the MSP53C691 is ready to accept data.
OUTRDY: Active low indicates that the MSP53C691 is ready to send data.
DATA0–DATA7 Data bits 0 through 7
PD4–PD7 General-purpose I/O bus
DACP Output to speaker/amplifier
DACM Output to speaker/amplifier

Read Operation by the Master
2-5
MSP53C691 Hardware Description
2.3 Read Operation by the Master
Theprocess for the read operation by the master is the samein 4-bit and 8-bit
modes. The read operation by the master happens when the slave wants to
send something to the master. The slave initiates the read process by pulling
OUTRDY low when the slave is ready.
The following events take place during the read operation:
1) TheMSP53C691putsthedatatobesenttothemasterontheinternalbus.
2) TheMSP53C691setsOUTRDYlowtoindicatethatitisreadytosenddata
to the microcontroller.
3) The microcontroller sets R/W high to indicate a read operation.
4) The microcontroller sets STROBE low. The data is available on the exter-
nal data-bus at this point.
5) The microcontroller reads the data from the bus.
6) The microcontroller sets STROBE high. The MSP53C691 also pulls
OUTRDY high at the rising edge of STROBE.
7) Thedata is takenofffromthe external data-busafterSTROBEgoeshigh.
Themicrocontrollermust latchorreadinthedatawhileSTROBEislow.When
the microcontroller sets STROBE high, the MSP53C691 sets OUTRDY high
to indicate that the data has been successfully transferred.
Figure 2–3 shows the sequence of events of the read operation.
Figure 2–3.Data Transfer—Read
b) Read—Two speech data transfer sequences:
a) Sequence of events for a single read operation:
DATA
COMMAND/DATA
DATA
COMMAND/DATA
R/W
R/W
OUTRDY
STROBE
OUTRDY
STROBE

Write Operation by the Master
2-6
2.4 Write Operation by the Master
Theprocessforthewriteoperation by the master is the samein4-bitand8-bit
modes. The write operation by the master happens when the slave is ready
torequest data or command from the master. Theslave initiates the write pro-
cess by pulling INRDY low when the slave is ready to receive data.
The following events take place during the write operation:
1) TheMSP53C691setsINRDYlowtoindicatethatitisreadytoreceivedata
from the microcontroller.
2) The microcontroller sets R/W low to indicate a write operation.
3) The microcontroller puts the data in the external data-bus.
4) The microcontroller sets STROBE low after the data is valid.
5) The microcontroller sets STROBE high after a minimum of 300 ns. The
MSP53C691 also pulls INRDY high at the rising edge of STROBE.
6) The data is latched in the MSP53C691 at the rising edge of STROBE.
When the microcontroller sets STROBE high, the MSP53C691 sets INRDY
high to indicate that the MSP53C691 is not ready to receive any more data.
Figure 2–4.Data Transfer—Write
R/W
a) Sequence of events for a single write operation
b) Write—Two speech data transfer sequences
INRDY
DATA
COMMAND/DATA
INRDY
DATA
COMMAND/DATA
R/W
STROBE
STROBE

MSP53C691 Device Initialization
2-7
MSP53C691 Hardware Description
2.5 MSP53C691 Device Initialization
The RESET pin is configured as an external interrupt (see Figure 2–5). It
providesthemeans forhardwareinitializationofthedevice.WhentheRESET
pin is held low, the device assumes a deep sleep state and various registers
areinitialized.AftertheRESETpinistakenhigh,thedevicegetsinitializedand
pulls INRDY low when the slave is ready to receive the oscillator selection
command (see the
Software Description chapter for a description of the
oscillatorselectioncommand).Theoscillatorselectioncommand(0xB)issent
through the DATA0–3 line while setting the DATA4 line low (indicating that it
is a command). When the slave receives the oscillator selection command
(0xB), it pulls INRDY low again to request the parameter (0x1 or 0x2) for the
command.Aftertheparameterisreceivedbytheslave,itgoesthroughtherest
of the initialization process and pulls INRDY low when the oscillator is
stabilized and the slave is ready to receive data/command.
Note:
If the slave does not receive the oscillator selection command as the first
command when INRDY goes low for the first time, or if the slave does not
receive the subsequent parameters for the oscillator control command (0x1
or 0x2), the slave resets itself again.
Figure 2–5.MSP53C691 RESET Diagram
MSP53C691
RESET 1 kΩ
100 kΩ
1 µF
VDD
The MSP53C691 is considered to be properly initialized after the following
events take place:
1) The microcontroller sets RESET low.
2) The microcontroller sets STROBE high throughout the initialization pro-
cess.
3) The microcontroller sets RESET high.
4) The microcontroller waits for INRDY to go low.
5) The microcontroller sets R/W low.
6) Themicrocontrollerputs0xB(oscillatorcontrolcommand)onthedata-bus
(DATA0–3) and sets the DATA4 (DATA/COMMAND) line low.
7) The microcontroller pulls STROBE low, waits for a minimum of 300 ns,
then pulls STROBE high again.

Microprocessor Interface Timing
2-8
8) The slave latches the command on the rising edge of STROBE.
9) TheslavepullsINRDYlowagaintorequesttheparameterfortheoscillator
control command.
10) The master sets R/W low.
11) The master puts the command parameter for the oscillator control com-
mand (0x1 or 0x2, see Table 3–1 for details) on the data-bus
(DATA0–DATA3) and sets the DATA4 (DATA/COMMAND) line low.
12) The microcontroller pulls STROBE low, waits for a minimum of 300 ns,
then pulls STROBE high again.
13) TheslavelatchesthecommandparameterontherisingedgeofSTROBE.
14) Theslave completes therest of theinitialization process andpulls INRDY
lowwhenreadytoreceivenewcommand.SeeFigure2–6foratimingdia-
gram of the initialization process.
Figure 2–6.Device Initialization
R/W
DATA(0–3)
DATA4
B0×1 or 0×2
RESET
INRDY
STROBE
2.6 Microprocessor Interface Timing
The MSP53C691 has a self-contained clock generation system. This flexible
clock generation system enables the software to control the clock over a wide
frequency range. The implementation uses a phase-locked-loop (PLL) circuit
that drives the processor clock to a selectable frequency between the
minimum and maximum ranges. Selectable frequencies for the processor
clock are spaced by 65.536 kHz. The PLL clock-reference is also selectable.
between a resistor-trimmed oscillator or a crystal-referenced oscillator, see
Figure 2–2. Internal and periphery clock sources are controlled separately to
provide different levels of power management. Figures 2–3 and 2–4 illustrate
the timing diagram for write and read operations.