THine THCS252 User manual

THCS252_Rev.2.01_E
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THCS252
20-bits GPIO or high speed Bus signal Transceiver
General description
The THCS252 integrates Serializer and Deserializer
onto a single chip, which supports general purpose
input and output (GPIO) signals through two pairs of
differential signal.
GPIO sampling clock is selectable from external
reference clock or internal oscillator clock.
The 8B10B encoding and decoding adopted by
THCS252 is easy to connect to optical / wireless
communication devices with high robustness and DC
balanced signal.
The built-in adaptive equalizer enables flexible cable
selection.
Application
The THCS252 can applicable to any systems which
have many control signals between PCBs, for
example Multi-function printers, Amusement
machines, Factory Automation and TVs.
Features
Support up to 20-bits GPIO
Not required to input GPIO sampling clock in
internal oscillator clock mode
Full duplex communication by two pairs of
differential signal
Output buffer open-drain or push-pull selectable
Support up to 8-bits low speed GPIO in low
power Standby mode
Integrated adaptive equalizer for long or lossy
media
8B10B encoding and decoding
Configurable digital noise filter
Error detection and indication
External reference clock frequency:
15-100MHz
Spread Spectrum Clock Generator to reduce EMI
Operating single power supply voltage: 1.7 V -
3.6 V
Wide range IO voltage: 1.7V - 3.6V
Operating ambient temperature: -40°C to 85°C
Block diagram
LDO
GPIO
D0/D19
...
D19/D0
REFOUT
TXP
TXN RXP RXN
RXN
RXP TXN
TXP
GPIO
D19/D0
...
D0/D19
THCS252 (Master mode) THCS252 (Slave mode)
LVCMOS I/O
LDO
OSC SSCG PLL
Tx
(Serializer)
Formatter
Rx
(Deserializer)
LVCMOS I/O
OSCSSCG
PLL
Tx
(Serializer)
Formatter
Rx
(Deserializer)
REFIN
REFEN

THCS252_Rev.2.01_E
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Contents page
General description..................................................................................................................................................1
Application..............................................................................................................................................................1
Features ...................................................................................................................................................................1
Block diagram.........................................................................................................................................................1
1. Pin configuration.............................................................................................................................................3
2. Pin description.................................................................................................................................................4
3. Absolute maximum ratings..............................................................................................................................7
4. Recommended operating conditions ...............................................................................................................7
5. Electrical characteristics..................................................................................................................................8
5.1. Current consumption...............................................................................................................................8
5.2. LVCMOS/Analog input DC specifications .............................................................................................9
5.3. LVCMOS AC characteristics.................................................................................................................10
5.4. CML DC characteristics........................................................................................................................13
5.5. CMLAC characteristics ........................................................................................................................13
6. CML Line Eye diagrams ...............................................................................................................................18
6.1. CML output Eye diagrams.....................................................................................................................18
6.2. CML input Eye diagrams ......................................................................................................................19
7. Function.........................................................................................................................................................20
7.1. Functional overview..............................................................................................................................20
7.2. Power supply.........................................................................................................................................20
7.2.1. Internal regulator output/input function (CAPOUT, CAPINA, CAPINP) ....................................20
7.3. Operating mode.....................................................................................................................................20
7.4. Transmission mode................................................................................................................................21
7.4.1. Full duplex Bi-directional transmission mode...............................................................................21
7.4.2. Unidirectional transmission mode.................................................................................................22
7.5. IO configuration ....................................................................................................................................23
7.5.1. Input and Output digital noise filter ..............................................................................................23
7.5.2. LVCMOS output buffer type configuration...................................................................................23
7.5.3. 5V tolerant I/O...............................................................................................................................23
7.6. Sampling clock configuration................................................................................................................24
7.6.1. Sampling clock selection...............................................................................................................24
7.6.2. Spread Spectrum Clock Generator (SSCG) and REFIN frequency...............................................26
7.7. Error detection and indication...............................................................................................................27
7.8. Standby mode........................................................................................................................................28
8. Package..........................................................................................................................................................29
Notices and Requests.............................................................................................................................................30

THCS252_Rev.2.01_E
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1. Pin configuration
OBUF FILTSEL1 D17 / D2 D16 / D3 D15 / D4 VDD STANDBY DIRSEL1 DIRSEL0 REFEN D19 / D0 D18 / D1
28 27 26 25
TEST2
34 33 32 31 30 2936 35
37 QFN-48 24 D14 / D5
AVDD 38 23 D13 / D6
CAPOUT 39 22 D12 / D7
21 D11 / D8
RXN 41 20 REFIN / REFOUT/ OSCSEL1
RXP 40
19 VDD
TXN 43 18 D10 / D9
CAPINA 42
17 D9 / D10
CAPINP 45 16 D8 / D11
TXP 44
15 D7 / D12
TEST1 47 14 D6 / D13
INT / LOCKN 46
13 D5 / D14
1 2 3 4
RESETN 48
11 12
RESERVED MSSEL RF / OSCSEL0 READY
5 6 7 8 9 10
D4 / D15 VDD SSEN FILTSEL0 D0 / D19 D1 / D18 D2 / D17 D3 / D16
(TOP VIEW)
49EXPGND

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2. Pin description
P
in
Name
P
in
No.
Type
Description
Refere
nce
TXP 44 CO High-speed CML signal output -
TXN 43 CO High-speed CML signal output -
RXP 40 CI High-speed CML signal input -
RXN 41 CI High-speed CML signal input -
RESETN 48 IL Chip reset 0: Chip reset
1: Chip operation
-
STANDBY 34 IL Standby mode entry 0:Normal mode operation
1:Standby mode operation
-
MSSEL 2 IL Master/Slave mode select 0: Master mode
1: Slave mode
-
FILTSEL1 35 IL digital noise filter select Table 5
DIRSEL0 32 IL DIRSEL0: GPIO direction select Table 2
Table 4
DIRSEL1 33 IL DIRSEL1: GPIO direction select Table 2
Table 4
OBUF 36 IL Output buffer type select 0: open-drain
1: push-pull
-
REFEN 31 IL
Data sampling clock select (Master mode)
0: Internal oscillator clock
1: External reference clock
-
CDR clock output enable (Slave mode)
0: REFOUT pin is Hi-Z state
1: CDR clock output from REFOUT pin
-
REFIN/
REFOUT/
OSCSEL1 20 B
REFIN: (Master mode) External Reference
clock input -
REFOUT: (Slave mode) CDR clock output -
OSCSEL1: (Master mode) Oscillator clock
frequency select Table 9
OSCSEL1: (Slave mode) Hi-Z -
RF/
OSCSEL0 3 IL
RF:(Master mode) input clock edge select Table 10
Figure 14
RF: (Slave mode) output clock edge select
OSCSEL0:(Master mode) Oscillator clock
frequency select Table 9
OSCSEL0: (Slave mode) Set to Low
D0/
D19 7 BT D0(Master mode): Data input -
D19(Slave mode): Data output -

THCS252_Rev.2.01_E
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P
in
Name
P
in
No.
Type
Description
Refere
nce
D1/
D18 8 BT D1(Master mode): Data input -
D18(Slave mode): Data output -
D2/
D17 9 BT D2(Master mode): Data input -
D17(Slave mode): Data output -
D3/
D16 10 BT D3(Master mode): Data input -
D16(Slave mode): Data output -
D4/
D15 11 B D4(Master mode): Data input -
D15(Slave mode): Data output -
D5/
D14 13 B D5(Master mode): Data input -
D14(Slave mode): Data output -
D6/
D13 14 B D6(Master mode): Data input -
D13(Slave mode): Data output -
D7/
D12 15 B D7(Master mode): Data input -
D12(Slave mode): Data output -
D8/
D11 16 B D8(Master mode): Data input -
D11(Slave mode): Data output -
D9/
D10 17 B D9(Master mode): Data input -
D10(Slave mode): Data output -
D10/
D9 18 B D10(Master mode): Data input/output -
D9(Slave mode): Data input/output -
D11/
D8 21 B D11(Master mode): Data input/output -
D8(Slave mode): Data input/output -
D12/
D7 22 B D12(Master mode): Data input/output -
D7(Slave mode): Data input/output -
D13/
D6 23 B D13(Master mode): Data input/output -
D6(Slave mode): Data input/output -
D14/
D5 24 B D14(Master mode): Data input/output -
D5(Slave mode): Data input/output -
D15/
D4 26 B D15(Master mode): Data input/output -
D4(Slave mode): Data input/output -
D16/
D3 27 BT D16(Master mode): Data input/output -
D3(Slave mode): Data input/output -
D17/
D2 28 BT D17(Master mode): Data input/output -
D2(Slave mode): Data output -
D18/
D1 29 BT D18(Master mode): Data output -
D1(Slave mode): Data input -
D19/
D0 30 BT D19(Master mode): Data input/output -
D0(Slave mode): Data input/output -
SSEN 5 BL
SSEN(Master mode): SSCG PLL enable
0: SSCG PLL is disabled
1: SSCG PLL is enabled
-
SSEN(Slave mode): Set to Low
FILTSEL0 6 BL FILTSEL0: digital noise filter select Table 5
INT/
LOCKN 46 BO INT: Interrupt output when READY=1
0: Error occurred
1(pull-up): No Error
-

THCS252_Rev.2.01_E
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P
in
Name
P
in
No.
Type
Description
Refere
nce
LOCKN(Master mode): Lock detect input
0: Lock state
1(pull-up): Unlock state
-
LOCKN(Slave mode): Lock detect output
0: Lock state
1(pull-up): Unlock state
-
READY 4 B CML Link communication status 0: Unlock state
1: Lock state
-
TEST1 47 IL TEST1 shall be tied to Ground. -
TEST2 37 AI TEST2 shall be tied to Ground. -
CAPOUT 39 PWR Decoupling capacitor Pin, 1.2V output. Figure 9
CAPINA 42 PWR 1.2V Analog power supply input. Figure 9
CAPINP 45 PWR 1.2V Analog power supply input. Figure 9
VDD 12 19
25 PWR 1.7-3.6V Digital power supply input for
LVCMOS I/O. -
AVDD 38 PWR 1.7-3.6V Analog power supply input for on-
chip regulator. Figure 9
EXPGND 49 GND Exposed Pad Ground. Must be tied to the PCB
ground plane through an array of vias. -
Pin Type definition
Analog Buffer
CO : CML Output buffer
CI : CML Input buffer
AI : Analog Input buffer
LVCMOS buffer
IL : Low speed schmitt trigger LVCMOS Input buffer
B : LVCMOS Bi-directional buffer
BO : Open-drain LVCMOS Bi-directional buffer
BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT : Low speed 5V tolerant LVCMOS Bi-directional buffer
Power/Ground
PWR : Power supply
GND : Ground

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3. Absolute maximum ratings
Parameter
Min
Typ
Max
Unit
Supply voltage(VDD,AVDD) -0.3 - 4.0 V
LVCMOS input voltage -0.3 - VDD+0.3 V
LVCMOS output voltage -0.3 - VDD+0.3 V
5V tolerant Bi-directional buffer input voltage -0.3 - VDD+2.5 V
5V tolerant Bi-directional buffer output voltage -0.3 - VDD+2.5 V
Open-drain output voltage -0.3 - 4.0 V
CML receiver input voltage -0.3 - CAPINA+0.3 V
CML transmitter output voltage -0.3 - CAPINP+0.3 V
Output current -50 - 50 mA
Storage temperature -55 - 125 °C
Junction temperature - - 125 °C
Reflow peak temperature/time - - 260/10 °C/sec
Theta-ja (Junction-to-Ambient) 30.8 [*1] °C/W
Psi-jt (Junction-to-Top of Package) 2.8 [*1] °C/W
Maximum power dissipation @+25°C 3.2 [*1] W
“Absolute maximum ratings” are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
*1: Thermal parameters are not guaranteed value. This value assists board and system level designers
4. Recommended operating conditions
Parameter
Min
Typ
Max
Unit
Supply voltage(VDD,AVDD) 1.7 - 3.6 V
Operating ambient temperature -40 - 85 °C
VDD andAVDD supply voltage shall be the same voltage.

THCS252_Rev.2.01_E
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5. Electrical characteristics
5.1. Current consumption
Symbol
Parameter
Pin
Type
Condition
Min
Typ
Max
Unit
Idd_w1 Normal mode current
Low current use case [*1] PWR AVDD=3.3V
VDD=3.3V - 80 - mA
Idd_w2 Normal mode current
High current use case [*2] PWR AVDD=3.3V
VDD=3.3V - 300 - mA
Idda_stby Standby mode current PWR AVDD=3.3V
VDD=3.3V - 4 - mA
Idda_slp Sleep mode current PWR AVDD=3.3V
VDD=3.3V - 3 - mA
Idda_rst Reset mode current PWR AVDD=3.3V
VDD=3.3V - 3 - mA
PWR : Power supply
*1: Master mode of Unidirectional transmission mode, 20-bits GPIO input, 100MHz of REFIN clock
*2: Slave mode of Unidirectional transmission mode, 20-bits GPIO output, 100MHz of REFOUT clock

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5.2. LVCMOS/Analog input DC specifications
Symbol
Parameter
Pin
Type
Condition
Min
Typ
Max
Unit
VIH High level input voltage B,BT,
BO
1.7V≦VDD<2.0V 0.65 VDD - VDD V
2.0V≦VDD<3.0V 0.70 VDD - VDD V
3.0V≦VDD≦3.6V 2.0 - VDD V
IL,BL 1.7V≦VDD≦3.6V 0.70 VDD - VDD V
VIL Low level input voltage
B,BT,
BO
1.7V≦VDD<2.0V 0 - 0.35 VDD V
2.0V≦VDD<3.0V 0 - 0.30 VDD V
3.0V≦VDD≦3.6V 0 - 0.8 V
IL,BL 1.7V≦VDD≦3.6V 0 - 0.30 VDD V
AI 1.7V≦VDD≦3.6V 0 - 0.15 VDD V
VOH High level output voltage B,BT,
BL
1.7V≦VDD<2.0V
IOH=-2mA VDD -
0.30 - VDD V
2.0V≦VDD≦3.6V
IOH=-4mA VDD -
0.45 - VDD V
VOL Low level output voltage [*1]
B,BT,
BL
1.7V≦VDD<2.0V
IOL=2mA 0 - 0.30 V
2.0V≦VDD≦3.6V
IOL=4mA 0 - 0.45 V
BO 1.7V≦VDD≦3.6V
IOL=2mA 0 - 0.27 V
IIH Input leak current high IL VIN=VDD -10 - 10 uA
IIL Input leak current low IL VIN=0V -10 - 10 uA
IOZH Output leak current high in
Hi-Z state B,BT, BL,BO VIN=VDD -10 - 10 uA
IOZL Output leak current low in
Hi-Z state B,BT, BL,BO VIN=0V -10 - 10 uA
AI : Analog Input buffer
IL : Low speed schmitt trigger LVCMOS Input buffer
B : LVCMOS Bi-directional buffer
BO : Open-drain LVCMOS Bi-directional buffer
BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer
BT : Low speed 5V tolerant LVCMOS Bi-directional buffer

THCS252_Rev.2.01_E
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5.3. LVCMOSAC characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tRSN RESETN low time - 3 - - us
tTCIP REFIN period - 10 - 66.6 ns
tTCH REFIN high time - 0.35 tTCIP 0.5 tTCIP 0.65 tTCIP ns
tTCL REFIN low time - 0.35 tTCIP 0.5 tTCIP 0.65 tTCIP ns
tTS Data input setup to REFIN
Pin type:
B 1.7V≦VDD≦3.6V 2.0 - - ns
Pin type:
BT
1.7V≦VDD<2.25V 25 - - ns
2.25V≦VDD≦2.75V 2.5 - - ns
2.75V<VDD≦3.6V 2.0 - - ns
tTH Data input hold to REFIN - 1.0 - - ns
tTPD Power on to RESETN high
delay - 0 - - ns
tOSC Internal oscillator clock
period
OSCSEL1=0
OSCSEL0=0 41.67 50 62.5 ns
OSCSEL1=1
OSCSEL0=0 20.84 25 31.25 ns
OSCSEL1=1
OSCSEL0=1 10.42 12.5 15.62 ns
tDCP Data sampling clock period REFEN=0 - tOSC - ns
REFEN=1 - tTCIP - ns
tFLTCK Noise filter clock period REFEN=0 10.42 12.5 15.62 ns
REFEN=1 - tTCIP - ns
tTCD Input data to output data delay (Master mode to
Slave mode)
SSEN=0
FILTSEL1=0
FILTSEL0=0 12 tDCP - 25 tDCP ns
FILTSEL1=0
FILTSEL0=1 19 tDCP - 35 tDCP ns
FILTSEL1=1
FILTSEL0=0 24 tDCP - 43 tDCP ns
FILTSEL1=1
FILTSEL0=1 34 tDCP - 59 tDCP ns
SSEN=1
FILTSEL1=0
FILTSEL0=0 57 tDCP - 110 tDCP ns
FILTSEL1=0
FILTSEL0=1 64 tDCP - 120 tDCP ns
FILTSEL1=1
FILTSEL0=0 69 tDCP - 128 tDCP ns
FILTSEL1=1
FILTSEL0=1 79 tDCP - 144 tDCP ns
tRCP REFOUT period - - tDCP - ns
tRCH REFOUT high time - - 0.5 tDCP - ns
tRCL REFOUT low time - - 0.5 tDCP - ns
tDOUT Data output period - - tDCP - ns
tRS Data output setup to
REFOUT - 0.45 tDCP
- 0.675 - - ns
tRH Data output hold to
REFOUT - 0.45 tDCP
- 2.175 - - ns
tRCD Input data to output data delay (Slave mode to
Master mode)
FILTSEL1=0
FILTSEL0=0 12 tDCP - 25 tDCP ns
FILTSEL1=0
FILTSEL0=1 19 tDCP - 35 tDCP ns
FILTSEL1=1
FILTSEL0=0 24 tDCP - 43 tDCP ns
FILTSEL1=1
FILTSEL0=1 34 tDCP - 59 tDCP ns
tRRDY RESETN high to READY
high delay - 0 - 10 ms

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Symbol
Parameter
Condition
Min
Typ
Max
Unit
tNRDY STANDBY low to READY
high delay - 0 - 10 ms
tSRDY STANDBY high to READY
high delay - 0 - 10 ms
tSSKW STANDBY high of Master mode and Slave mode
skew margin - -400 - +400 us
tTLH Clock and Data output low
to high transition time
Clock - - 2.1 ns
Data(Pin type=B) - - 4.2 ns
Data(Pin type=BT) - - 5.9 ns
tTHL Clock and data output high
to low transition time
Clock - - 2.1 ns
Data(Pin type=B) - - 4.3 ns
Data(Pin type=BT) - - 6.1 ns
Figure 1 LVCMOS input timing diagram
VDD/2
VDD/2VDD/2
VDD/2 VDD/2
tTCIP
tTS tTH
tTCH(RF=0)
tTCL(RF=1)
RF=0
RF=1
D0-D19
REFIN
tTCL(RF=0)
tTCH(RF=1)

THCS252_Rev.2.01_E
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Figure 2 LVCMOS output timing diagram
Figure 3 GPIO Input to Output delay timing diagram
20%
80%
CL= 8pF
RD = 10Ω
Test Point
20%
80%
tTLH tTHL
VDD/2
VDD/2VDD/2
VDD/2 VDD/2
tRCP
tRS tRH
tRCH(RF=0)
tRCL(RF=1)
RF=0
RF=1
D19-D0
REFOUT
tRCL(RF=0)
tRCH(RF=1)
tDOUT
tTCD
Chip Master
mode Inputs
D0-D19 DATA1 DATA2 DATA3
DATA1 DATA2 DATA3
Chip Slave
mode Outputs
D19-D0
tRCD
DATA1 DATA2 DATA3
DATA1 DATA2 DATA3
Chip Slave
mode Inputs
D19-D0
Chip Master
mode Outputs
D0-D19

THCS252_Rev.2.01_E
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5.4. CMLDC characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VTOD CML differential output peak
to peak signal - 600 800 1000 mVpp
VTOC CML common mode output
voltage - - 1200 - 0.5 VTOD - mV
ITOH CML output leak current
high RESETN=0 TXP/N=CAPINA -30 - 30 uA
ITOS CML output short current RESETN=0
TXP/N=0V -80 - - mA
VRTH CML differential input high
threshold - - - 50 mV
VRTL CML differential input low
threshold - -50 - - mV
IRIH CML input leak current high RESETN=0
RXP/N=CAPINA -10 - 10 uA
IRIL CML input leak current low RESETN=0
RXP/N=0V -10 - 10 uA
IRRIH CML input current high RXP/N=CAPINA - - 2 mA
IRRIL CML input current low RXP/N=0V -6 - - mA
RRIN CML differential input
resistance - 80 100 120 Ω
5.5. CMLAC characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tTRF CML output rise and fall time (20%-
80%) - 50 - 150 ps
tTPLL0 RESETN=1 to CML output delay - - - 10 ms
tTPLL1 RESETN=0 to CML output high fix
delay - - - 500 ns
tTNP0 READY low to training pattern output
delay - - - 100 us
tTBIT Output unit interval - - tDCP÷30 - ns
tRBIT Input unit interval - 250 - 2222 ps
tRPLL0 Training pattern input to LOCKN low
delay Unidirectional mode - - 10 ms
tRPLL1 RESETN low to LOCKN High delay Unidirectional mode - - 10 us
tRLCK0 LOCKN low to data output delay Unidirectional mode - - 5 ms

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Figure 4 CML outputAC characteristics diagram
Figure 5 CML buffer equivalent circuit
TXP
TXN
75～200nF
< 5mm
Vdiff = (TXP) - (TXN)
50Ω
50Ω
75～200nF
20%
80%
20%
80%
tTRF tTRF
TXP RXP
TXN RXN
Vbias
Zdiff=100ohm
C=75～
200nF
GND
THCS252 THCS252
CML Transmitter
CML Receiver
50Ω
CAPINP
C=75～
200nF
50Ω 50Ω
50Ω

THCS252_Rev.2.01_E
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Figure 6 GPIO/CMLBi-directional mode Power on & Reset timing diagram
THCS252 (Master mode)
Tx
(Master side)
Rx
(Master side)
REFIN
RESETNm
READYm
D0/D19m
D9/D10m
D10/D9m
D
19
/D0m
THCS252 (Slave mode)
Rx
(Slave side)
Tx
(Slave side)
R
EFOUT
RESETNs
READY
s
D19/D0s
D10/D9s
D9/D10s
D0/D19s
TXm
TXs
DATA_WIDTH=0, DIRSEL1/0=00
tTPD
VDD
RESETNs
D9/D10s
D
19
/D0s
Valid Input
Invalid Input Invalid Input Valid Invalid Input
REFIN
tTPLL0
RESETNm
D10/D9m
D
19
/D0m
Valid Output Valid Invalid Output Invalid
TXs
Training Normal
READYs
tRRDY
READYm
tTNP0
tTPLL1
TXm
Training Normal Training
Invalid Input
D0/D19m
D9/D10m Invalid Input Valid Input Valid Input Invalid Input
D19/D0s
D1
0
/D
9
s
Invalid Output Valid Output Valid
REFOUT
Hi-Z
Invalid clock
Invalid clock
Invalid clock
Invalid
Solid line : RF=0
Dashed line : RF=1
Hi-Z
Hi-Z
Hi
-
Z
Hi
-
Z
Hi
-
Z

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Figure 7 GPIO/CMLUnidirectional mode lock & unlock timing diagram
DIRSEL1/0=11
THCS252 (Master mode)
Tx
(Master side)
Rx
(Master side)
REFIN
RESETNm
D0/D19m
THCS252 (Slave mode)
Rx
(Slave side)
Tx
(Slave side)
R
EFOUT
RESETNs
D19/D0s
LOCKN
TXm
REFIN
tTPLL0
RESETNm
LOCKN
tRPLL1 tRPLL1
tRPLL0
RESETNs
tRLCK0
TXm
Training
Training
Normal
Invalid InputD0/D19m Valid Input Valid Input Invalid InputInvalid Input
D19/D0s Invalid
Output
Invalid Output Valid Output Valid
REFOUT
Hi-Z
Invalid Clock
Invalid Clock
Invalid Clock
tTPD
VDD
Solid line : RF=0
Dashed line : RF=1
Hi-Z
Hi
-
Z

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Figure 8 Standby mode timing diagram

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6. CML Line Eye diagrams
6.1. CML output Eye diagrams
Y=0mV
X=0 UI X=1 UI
1UI=1/(serial data rate)
Y
X
A
B C D
E
H G F
X[UI] Y[mV]
A 0.15 0
B 0.355 140
C 0.5 175
D 0.645 175
E 0.85 0
F 0.645 -175
G 0.5 -175
H 0.355 -140

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6.2. CML input Eye diagrams
Y=0mV
X=0 UI X=1 UI
1UI=1/(serial data rate)
Y
X
A
B C
D
F E
X[UI] Y[mV]
A 0.25 0
B 0.3 50
C 0.7 50
D 0.75 0
E 0.7 -50
F 0.3 -50

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7. Function
7.1. Functional overview
With high speed CML Serializer and Deserializer integrated onto a single chip, THCS252 enables
Aggregation/Deaggregation up to 20-bits parallel General-Purpose I/O (GPIO) signal through full-duplex
communication by two pairs of differential signal with minimal external components. THCS252 supports up to 8-
bits low speed GPIO signal in low power Standby mode. It does not require any external clock generators e.g. a
crystal oscillator. A pair of THCS252 enables to monitor and control peripheral devices via GPIOs. In case
communication errors occur, they keep the GPIO signals and report by an interrupt signal.
7.2. Power supply
7.2.1. Internal regulator output/input function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces 1.2V (CAPOUT) only for internal use. It shall not be used for any other external
loads. Bypass CAPOUT to GND with 10uF as a power supply pin. BypassAVDD to GND with >10uF.
CAPINP and CAPINA supply reference voltage for internal analog circuits. Bypass CAPINP/CAPINA to GND
with 0.1uF as power supply pins to reduce high frequency noise. CAPOUT, CAPINA and CAPINP must be tied
together as Figure 9.
It is recommended to place ferrite bead forAVDD pins to reduce noise as Figure 9.
Figure 9 Connection of CAPOUT, CAPINA, CAPINPand decoupling capacitor
7.3. Operating mode
Table 1 shows operating mode setting.
Table 1 Operating mode setting
Operating
mode
Setting
description
RESETN
STANDBY
Reset 0 - Chip reset
All outputs are Hi-Z
Normal 1 0 Normal operating mode
Standby 1 1 Low power and low frequency sampling rate transmission
through up to 8-bits GPIO.
CAPOUT
CAPINA
CAPINP
THCS252
10uF
0.1uF
0.1uF
AVDD
Power
Supply
VDD
>10uF