UQDevices Logic16 User manual
Logic16
Time Tag Unit
User Manual
Version 3.0
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Table of contents
SECTION 1 INTRODUCTION 4
1.1 SUPPORT 6
SECTION 2 QUICK START GUIDE 7
SECTION 3 HARDWARE SPECIFICATIONS 8
3.1 TECHNICAL SPECIFICATIONS 8
3.2 SAFETY OF OPERATION 9
3.3 DEVICE FEATURES 11
3.3.1 ACTIVE EDGE AND THRESHOLD DETECTION 11
3.3.2 TIME TAGGER MODE 11
3.3.3 LOGIC MODE 15
3.3.4 DELAY 17
3.3.5 FUNCTION GENERATOR 17
3.3.6 EXTERNAL CLOCK INPUT 17
3.4 FIRMWARE UPDATE/CHANGE 18
SECTION 4 SOFTWARE INTERFACE 20
4.1 DRIVERS INSTALLATION 20
4.1.1 WINDOWS 8OR HIGHER 20
4.1.2 PRE WINDOWS 8 20
4.1.3 LINUX 20
4.2 GRAPHICAL USER INTERFACE 21
4.2.1 TIMETAG EXPLORER 21
4.2.2 UQD LOGIC16 CORRELATION VIEWER 31
4.3 APPLICATION PROGRAMMING INTERFACE (API) 34
4.3.1 .NET SETUP 34
4.3.2 C++ SETUP 37
4.3.3 API METHODS 39
4.3.4 SAMPLE CODES 53
SECTION 5 FAQ 58
SECTION 6 REVISION HISTORY 60
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Section 1
Introduction
Logic16 is a versatile time tagger and logic correlation unit made especially for analyzing photon detection
signals in multi-photon correlation counting and time-resolved signal analysis.
Logic16 operates in two distinct modes for measurement flexibility: Logic Mode and Time Tagger Mode.
Logic Mode performs on-board coincidence (pattern) counting and can internally process all possible
patterns for the 16 inputs, simultaneously. The patterns to be counted are defined by indicating for each
input whether or not an active signal edge should appear, or if the input should be ignored. In Logic Mode,
the unit can also output TTL pulses triggered by detections of user-selected coincidence patterns. Output
channels are distinct from input channels. Coincidence counting can be performed alongside the use of
the pattern-triggered outputs. Since all time-correlation processing is performed internally, it can be used
even with small, low-power computers.
Time Tagger Mode time tags photon events –in other words, it records the input channel and event time
when signals are detected. In Time Tagger Mode it is possible to perform:
continuous time tagging
- time tag each event detected
gated time tagging
- condition time tagging to occur only when signals appear on a specific input
time tag filter
- time tag events only when they appear in groups
- use for time-of-flight1measurements with respect to a fast pump signal2
- use to reduce data file size for long3measurements
By employing the time tag filter it is possible for users to measure with sustained
4
data rates up to 190
MHz. However, keep in mind that time tags can be processed on-board Logic16 faster than they can be
sent across the USB interface to the host PC. The time Tag Filter is thus useful for high rate signals when
only select events are of interest.
1
Or “time-of-arrival” (TOA)
2
For example, a 76 MHz Ti-Sapphire laser
3
For example, on the order of days
4
In contrast to burst
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Figure 1-I Summary of Logic16 hardware operations
Configurations
Logic16 has two different configurations. Configuration A has 16 input channels with a resolution of
156.25 ps time bin width while Configuration B has 8 operational input channels with a resolution of
78.125 ps time bin width. Unless requested, Configuration A is shipped as a default. It is easy to switch
between the two configurations using a user-supplied JTAG cable. See Section 3.3 for details.
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1.1 Support
To improve user experience, Universal Quantum Devices (UQD) provides a variety of support to help you
get started with Logic16. Included in this manual you will find a quick start guide, software installation tips
and detailed information about Logic16 operation. Programming examples are included on the Logic16
CD, which is available at www.uqdevices.com. On the website you will also find video tutorials.
The success of UQD and DotFAST consulting is based on tight interaction with our customers. In the case
you experience any problems, need clarifications or simply have an idea for improvement, contact us by
Disclaimer: This product is subject to constant development and improvement. For latest drivers and
documentation please visit the website.
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Section 2
Quick Start Guide
This guide outlines basic steps to get started with Logic16. Refer to section 3.1 to identify ports and
connectors on the unit. Videos are available on the website for additional getting started support.
iPower the device
Connect Logic16 to a DC power supply (12 V @ ≥1.5 A) or a NIM crate (12 V @ 1.0 A
and -12V @0.4 A). The “Power” LED should turn blue.
ii Set up a connection
Connect Logic16 to your computer using the USB 2 cable supplied with your device.
iii Establish communication
Ensure software and program libraries are available on your host PC.
5
Open the Time
Tag Explorer software and click connect. The “USB” LED should turn blue.
This quick start guide references the use of Time Tag Explorer. See section 4 to learn
about Logic16 Correlation Viewer or custom programming.
iv Connect to a signal
Connect one of the input channels to a photon detector using an SMA Cable.
Alternatively, simulate your signal using output 4 - a basic function generator
6
.
vRead tags or count patterns
Check the Read Tags box on the Time Tag Explorer Time Tag Tab and verify that time
tag differences appear in the GUI window. OR go to the Logic tab, check Use Logic
box and verify that counts appear in the GUI window under singles for the connected
input.
If you cannot see these signals, please check that your input thresholds on the input
tab are set appropriately for your signal.
5
Available at www.uqdevices.com/documentations or on the CD included with Logic16
6
Control the function generator on the “FG” tab of Time Tag Explorer – click the box beside “FG” to turn on
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Section 3
Hardware Specifications
3.1 Technical specifications
Front-View
①Inputs
SMA, 50Ωtermination
②Outputs
SMA, 50Ωtermination
③ Power LED
Blue when unit is connected to a power supply
④ USB LED
Blue when unit has established a successful connection to host PC
⑤Error LED
Red when an error occurs during operation of the device
Note: All three LEDs light up briefly upon connection to the power supply. This indicates that the
power is on and the unit is booting.
⑥USB port
Connection for USB 2.0 cable provided.
Note: We recommend that you do not use a USB Hub in order to connect multiple units to your PC.
This will limit the data transfer rate of the device.
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Rear-View
⑦DC power supply port
+12 V @ 1.5 A
⑧NIM power supply connector
+12 V @ 1.0 A & -12 V @ 0.4 A
Note: Logic16 can be operated using either a DC power supply OR a NIM Crate.
⑨External Clock Input
10 MHz external clock BNC input
⑩JTAG Connector
JTAG link cable (e.g. JTAG-cable Xilinx, Xilinx parallel cable, HS2 Digilent)
3.2 Safety of Operation
Ensure the module is operated vertically, and that the air is free to flow through the cooling vents
in the top and bottom sides of the unit.
Never operate the module horizontally, or with covered air vents - this could lead to overheating
and cause damage.
NIM crate power supply
The modules are designed for operation within a NIM crate that is powered with a properly rated
and installed power supply. In particular, in order to ensure safe operation of the logic module
and any connected instruments or computers, it is critical that the NIM crate and its power supply
are connected to electric ground through the power connector, as required by the local safety
standards.
DC power supply
Only use DC regulated power supply which meets the safety standards in your respective
country and/or legal jurisdiction.
We also strongly recommend that the DC power supply is grounded when in use.
Disclaimer:
Neither Universal Quantum Devices nor DotFAST Consulting are responsible for any harm or damage
caused to or by Logic16 or any connected devices or instruments, in the case that (a) the unit is operated
outside of a NIM crate or DC power supply and/or (b) is powered by an incorrectly installed NIM crate or
DC power supply.
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SPECIFICATIONS
Note: Users can switch between configuration A and B with a firmware update
TIMING
Configuration A
Configuration B
Time bin, digital
156.25 ps
78.125 ps
Time jitter (RMS)
71.6 ps
58.5ps
Dead time
5 ns†
5 ns†
Time tag filter window
156.25 ps
78.125 ps
Max. input delay
0 to + 40 μs†† (218 –1 units)
0 to + 20 μs†† (218 –1 units)
Input delay adjustment step
156.25 ps
78.125 ps
Coincidence window
0.156 ns –2.6 ms
(224 -1 units)
0.078ns –1.3 ms
(224 -1 units)
SYSTEM PERFORMANCE
Time tag rate burst rate
200 Mtags/s for up to 1024 events/channel
Sustained data rate (time tagger mode)
~ 11 M tags/s (USB 2.0)
Time tag processing rate, time tag filter mode †††
190 M events/s
Max. on-board coincidence count rate
100 MHz (summed across all channels)
Input channel settings (for coincidence pattern definition)
Tri-state: Active, Inactive, Ignore
Maximum number of simultaneously processed patterns
> 43 million (316)
> 6 thousand (38)
INPUTS
Number of inputs
16
8
Input definition
SMA, 50Ω termination, DC coupled
I/P discriminator
Threshold range
-2 V to +2 V , steps of 15 mV
Min. pulse amplitude
50 mV typical
Edge Detection
Rising or Falling
Min. pulse duration
(above threshold)
300 ps
Max I/P level
-2.5 V to + 5.0V
Counters
32-bit
GENERAL
Power
NIM standard from crate: + 12V @ 1.0 A & -12V @ 0.5 A
OR
DC power supply: 12V @ 1.5A
Interface
USB 2.0
OTHER I/O
External time base input *
BNC, 10 MHz sine, 1KΩ, AC-coupled 1VPP
Outputs
Output definition
SMA, 50Ω termination
Output signal
TTL pulse, >2.5 V high, 100ns duration
Type: Pattern-detection triggered –No. of outputs
3
1
Type: Pulse generator –No. of outputs
1
†Double pulse time difference to guarantee capture of all consecutive pulses. Shorter double pulse time
differences will be capture probabilistically
†† The maximum detection rate without loss of data is 25 MHz (50 MHz) with a delay of 40 μs (20 μs) due
to the buffer of 1024 events / channel. Higher detection rates possible for shorter delays.
††† In filtering mode Logic-16 can process up to 190 Mtag/s internally to allow time of flight
measurements with respect to fast laser pulses.
* Note: Use of external time base makes channel 16 (8) inactive.
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3.3 Device Features
3.3.1 Active Edge and Threshold Detection
A detection event occurs when the active edge of an input signal reaches the user-defined threshold
voltage. The threshold level and the active edge (rising or falling) can be adjusted for each input,
individually. Logic16 uses detection events to determine when to tag time or take a count.
3.3.2 Time Tagger Mode
In this mode, Logic16 outputs a time tag when a detection event occurs on an input channel. This feature
is useful in time correlated single photon counting especially where absolute time tags are required. This
mode can be used for g2 (cross and auto correlation measurements), timing histograms, time of arrival/
time of flight, also for coincidence counting post processing. This mode could be applied in quantum
communication, quantum cryptology, quantum key distribution (QKD) as well as LiDAR and other time
correlation experiments.
Time is stored in the device as multiples of its internal timing resolution 156.25 ps or 78.125 ps for
Configuration A or B, respectively. Note that in Logic16 there is no designated “start” channel - the
reference time is that of the first tag, regardless of which input it was detected on. In other words, the
first signal detected will be recorded as occurring at time = 0.
In Time Tagger Mode, Logic16 offers modifiable filtering and gating. Employing these features will improve
maximum event rate, which is the rate at which assigning time tags to detection events can occur. Data
transfer rate, the rate at which time tags can be sent across the USB interface, is limited to the USB
connection. As a result, maximum data transfer rate is always 11 MHz.
Table 3-I summarizes the use and rates of relevant for each filtering option.
Max. event
rate
Max. data
transfer rate
Use when…
(MHz, across all inputs)
Continuous
11
11
-All time tags must be recorded
Time Tag
Filter
190
11
-Pump or trigger rate > 10 MHz, but only relevant
TOF tags are needed (trigger and signal)
-Measuring for long periods of time (e.g., days)
and only multi-photon events are needed
Edge Gate
190
11
-Heralding events by a <= 10 MHz source
Level Gate
190
11
-Adjustable gate open with specific times
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Continuous
Logic16 streams absolute time tags from ALL detected signals directly to the host PC without any
filtering or gating.
Figure 3-I Continuous time tagging: Three different signals, S1 (rising edge;
V1), S2 (falling edge; V2) and S3 (falling edge; - V3) are time tagged
concurrently. All pulses are being tagged.
Time Tag Filter
The Time Tag Filter can be used to effectively reduce the bandwidth required to perform certain
measurements. For example, it can enable time of flight (TOF) measurements with respect to fast
trigger signals (up to 190 MHz), which is too high rate to be recorded in continuous time tag mode.
This is possible so long as the photon detections of interest do not exceed the data transfer rate
(11 MHz). The Time Tag Filter can also be used to reduce data file size when recording photon
events for long periods of time (e.g., days), in cases where only multi-photon events are of
interest.
The filter transmits tags only when signals appear in groups. The user must define the minimum
number of tags required within a group and the maximum time that can separate adjacent time
tags. A group may contain an arbitrary number of tags greater than or equal to the minimum
number, as long as the time gap between any two tags is less than the defined maximum time. It
is therefore important to be mindful that the maximum time must be less than the period of any
periodic signal input. If the maximum time exceeds the period of a signal, all events will be tagged,
as in continuous time tag mode.
Inputs can be excluded from the filter using an exception mask. In this case, the time tags on the
masked channel will always be transmitted, and not included in the filter. With the time tag filter
in use, Logic16 can time tag events at 190 MHz, distributed across all channels. Data transfer will
still occur at up to 11 MHz.
Caution: Using filter exceptions can cause time tags not to be transmitted in correct order. (e.g.
Time differences can be negative)
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Figure 3-II Time Tag Filtering: Signals S1, S2 and S3 are input on
Logic16. With Time Tag Filter minimum group number set to 2 and
maximum time as shown, only pulses with their active edge within the
filter are tagged.
Gating
Edge Gating
The Edge Gate trigger is located on input 8. This gate opens for a user-specified time, after there
is an active edge on input 8. The gate width should be less than the period of the trigger signal or
the results will be unreliable. The position of the gate can be adjusted to compensate for cable
delays and similar effects. This can be a negative and positive time interval.
7
7
In configuration B, Logic16 input 8 does not time tag when using the external clock input (10
MHz). The edge gate can still be triggered on/off in this case with an input signal, however will
NOT time tag.
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Figure 3-III Edge Gating: Signal S1 on input 8 triggers the edge gate
to open, when an active edge is detected. Only pulses with their
active edge within the gate are being tagged
Level Gating
The Level Gate trigger is located on input 9. When the signal on input 9 is higher than the specified
threshold voltage, tags are processed normally. When it is lower, the input signals are ignored.
Please note that the level gate signal has in internal jitter of 5 ns.
Disclaimer: Level gate starts 25ns before the trigger signal.
Figure 3-IV Level Gating: When Signal S1 on input 9 is higher than the
threshold voltage, it triggers the level gate open. Gate width is the same
as the high time of S1. Only pulses with their active edge within the gate
are being tagged. Note: there is an offset of
∼
25 ns between when the
level gate starts and when trigger input is tagged.
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3.3.3 Logic mode
This mode allows users to count the occurrence of detection patterns and to output pattern-triggered
TTL pulses. Coincidence counting is used for bell tests and other entanglement experiments. Pattern
triggered outputs are useful with gated photon detection and telecom inGaAs detectors.
Logic Patterns (Coincidence Counting)
Logic Pattern Detection events are counted when input pattern conditions are met within the
coincidence window.
The Patterns are defined by choosing each input condition to be one of:
+active: true if the input has an active edge within the coincidence window
inactive: true if the input does NOT have an active edge within the coincidence window
while there is at least one active edge on another input
Øignore: true regardless of whether the input has an active edge or not
Each pattern must have a (+) on at least one input, otherwise it is ill-defined. Multiple patterns
can be counted concurrently on-board the unit.
The coincidence window is the maximum time from the first (+) detection to the last
8
(+) in the
pattern detection event. When all logically selected conditions (+,−,Ø) are met within that
time window, the event is counted. Otherwise the event is not counted.
The user can modify the coincidence window (see specifications). Ideally there will not be more
than one (+) on a single input, within one coincidence window. If this occurs, a “DoubleError” flag
will be thrown.
Examples
In the descriptions below, M is the number of effective input channels 16 (8) for configuration A (B).
An example singles event (+1, Ø2…ØM)is shown in Figure 3-V.a: the pattern event is counted every time
there is an active edge (+) on input 1, while all other inputs are ignored.
An example coincidence event (+1, +2, Ø3 …ØM)is shown in Figure 3-V.b: the pattern event is counted
when both inputs 1 and 2 have an active edge within the same coincidence window.
An example anticoincidence event (+1, −2,Ø3 …ØM)is shown in Figure 3-V.c: the pattern event is counted
when there is an active edge on input 1 but not input 2, within the coincidence window.
8
If it is a singles event, the first and last detection are one and the same
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Figure 3-V Pattern Processed Coincidence Counting: For the same two signal (on input 1 and 2), three pattern events are counted.
Here it is assumed that channels 3 to M are all set to
Ø
.
Pattern-Triggered Outputs
In Logic mode, the user can generate up to 3 (1) pattern-triggered outputs in Configuration A (B)
9
.
The output channels are accessible on the front panel of the unit (Output 1 –3). These outputs
are triggered by detection events as defined in the Logic Pattern section, however, instead of
counting these patterns when they occur, registration of an event will trigger the output of a TTL
pulse. Each output can be set to its own, distinct pattern trigger.
Note that these patterns are also set independent from coincidence counting patterns. In other
words, the user can set any pattern to be counted and any other pattern to trigger an output.
Counting and pattern-triggered outputs can be used simultaneously.
For each event, Logic16 outputs 2.5 V high TTL pulses with a default delay of 350 ns from the first
detection within the coincidence window. The pulse width is adjustable.
9
In configuration B, Outputs 2 and 3 are not operational
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3.3.4 Delay
Logic16 enables user to define individual delays for each input channel. This feature is very useful in the
logic mode, where the delays of individual channels can be fine-tuned to maximize coincidence signals.
3.3.5 Function Generator
Logic16 has its own simple function generator located on Output 4. Frequency and duty cycle can be
adjusted. The cycle time and high time can be adjusted in 5 ns increments, from 10 ns to 1.3 sec.
Note: The function generator always uses the internal frequency reference and not the external 10 MHz
signal.
3.3.6 External Clock Input
The external clock 10MHz input can be used for local synchronization to access more change for even
larger multi-photon experiments as well as long distance synchronization, e.g. in quantum communication
(including Quantum cryptography and quantum key distribution).
The 10 MHz input is located on the rear side of the device. It can be used to increase the stability of long-
term measurements by connecting a stable clock source. The input is AC coupled. For this reason it can
be driven by a variety of digital signals. As long as the corresponding 10 MHz error flags do not raise, the
time base can be considered as valid. When using digital signals the rise and fall time should be greater
than 5 ns to avoid ringing.
Levels: There are two possibilities to drive the 10 MHz input:
Note: Use of external time base makes channel 16 inactive in configuration A and channel 8 inactive in
configuration B.
Level
Termination
Sinus
1 Vpp nominal
1 kΩinternal
Digital
Minimum level 500 mVpp
External 50 Ω termination required
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3.4 Firmware Update/Change
The following section outlines how to perform firmware updates and changes. For best results it is
important that the Logic16 Unit is running the latest FPGA firmware. The same procedure for updates is
used to switch from Configuration A to B, or vice versa. Tip: You can check the firmware version quickly
using Timetag Explorer
10
.
You need the following items:
Logic16 Unit
Small Phillips or flathead screw driver
JTAG link cable (e.g. JTAG-cable Xilinx, Xilinx parallel cable, HS2 Digilent)
Xilinx Lab Tools –iMPACT (Free download from http://www.xilinx.com/downloads)
oFind and download latest ISE Design Tools available for your PC under Vivado
(HW Developer) in ISE Archive.
oFollow setup instructions given by Xilinx and ensure Xilinx iMPACT is
accessible.
Firmware PROM files provided by UQD (found in the CD drive provided)
Time Tag Explorer (optional)
Perform the following procedures to update/change the Firmware:
iConnect Logic16 to PC with a JTAG Cable
Modules manufactured after January 2015: connect JTAG Cable to the designated
JTAG connector found on the rear of the device.
Modules manufactured before January 2015: remove the right-hand side panel
(unscrew). Connect the JTAG Cable to the FPGA board and then to your computer.
ii Connect device to a power supply.
Connect Logic16 to a DC power supply (12 V @ ≥1.5 A) or a NIM crate (12 V @ 1.0 A
and -12V @0.4 A). The ports are found on the rear side of the device.
10
Upon connection, it will appear in the window on the Time Tag Explorer’s TimeTag tab
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iii Run the program “Xilinx iMPACT” and connect iMPACT to device
Once the program is running, a prompt will appear to create a new project. Click
“yes”. Select “Configure devices using Boundary-Scan (JTAG)” and then click “OK”.
Once connection has been established with Logic16, another prompt will appear to
Auto Assign the configuration files. Click “No”. Choose “Cancel” if a further window
appears.
Note: An error may pop up if Logic16 is not powered on. Make sure power LED is on
when trying to connect to the device.
iv Assign new configuration file
iMPACT will display two devices. Only the first will have its firmware updated. Right
click on the first device (xcf08p) and choose “Assign new configuration file”. Choose
the desired file .mcs file under “Firmware” from the CD drive provided with the
device. i.e. “Timetag_230_06_highres.mcs”. Once selected, right click again on this
device and choose “Program”. The device programming properties will open. Select
the checkmark beside "Verify" and click "OK". Once done, iMPACT will display
“Program Succeeded”.
vClose iMPACT and disconnect Logic16
Close iMPACT, power down the device, and disconnect the Xilinx Parallel Cable. If
the side panel had been detached for this process, secure it back on the device. The
firmware update is complete.
vi Reboot and confirm firmware update was correct
Reconnect power to the Logic Unit to reboot the device, then check firmware
version with Time Tag Explorer (or your own program).
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Section 4
Software Interface
4.1 Drivers Installation
Logic16 comes with .NET drivers for Windows and C++ drivers for Windows and Linux.
4.1.1 Windows 8 or higher
Devices with FPGA version greater than 2.17 do not need a driver installed on Windows 8.
Plug in the device and the driver loads automatically.
Caution: Do not connect a device with firmware version below 2.17 to a computer
running Windows 8. Windows stores the presence of an automatic driver in the
registry. When it doesn’t find a driver on the first attempt, it will never ask the device
again.
4.1.2 Pre Windows 8
i. Extract the Zip file with the USB driver
ii. Plug the unit into the NIM crate or DC power supply
iii. Connect the unit to the computer using a USB cable
iv. Power on the NIM crate
v. When prompted, choose manual driver selection
vi. Navigate to the folder with the extracted files and open the sub folder “USB Driver“
vii. The driver is installed and the device is ready for use.
4.1.3 Linux
Linux C++ drivers for Intel processor 32 and 64 bit are provided. Linux 32 bit on ARM is provided for test
purposes and is not guaranteed to run on all ARM environments.
On Linux, copy libtimetag32.so or libtimetag64.so to your lib directory. If you have not already done so,
get the g++ compiler and libusb development version.
sudo apt-get install g++-4.6-multilib
sudo apt-get install libusb-1.0-0-dev
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