Variscite VAR-320SBC User manual

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Table of Contents

1.Revision History...................................................................................................................................................4
2.Overview.................................................................................................................................................................5
2.1.Basic................................................................................................................................................................5
2.2.Features Summary.......................................................................................................................................6
2.3.Block Diagram...............................................................................................................................................8
3.Components..........................................................................................................................................................9
3.1.MONAHANS-P CPU......................................................................................................................................9
3.1.1.Overview.................................................................................................................................................9
3.1.2.Monahans-P Block Diagram............................................................................................................10
3.1.3.Multimedia co-processor.................................................................................................................11
3.1.4.Power Management...........................................................................................................................11
3.2.Memory.........................................................................................................................................................12
3.2.1.266MHZ 32bit DDR SDRAM.............................................................................................................12
3.2.2.NAND flash...........................................................................................................................................12
3.3.Power Management IC, National LP3972.............................................................................................12
3.4.Wi2Wi WS2W0001 WIFI module.............................................................................................................12
3.5.Davicom® DM9000BEthernet controller..............................................................................................12
3.6.Connectors to base board.......................................................................................................................13
4.Interfaces..............................................................................................................................................................13
4.1.TouchScreen...............................................................................................................................................13
4.2.SSP Interface...............................................................................................................................................15
4.3.UART Ports..................................................................................................................................................16
4.4.SD/MMC Ports.............................................................................................................................................17
4.5.LCD Interface...............................................................................................................................................17
4.6.JTAG Port.....................................................................................................................................................19
4.7.AC 97 Interface..............................................................................................Error!Bookmarknotdefined.
4.8.1-Wire............................................................................................................................................................20

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4.9.Camera Interface........................................................................................................................................21
4.10.PWM...........................................................................................................................................................23
4.11.Ethernet port...........................................................................................................................................23
4.12.USB............................................................................................................................................................24
4.12.1.USB 1.1 Full speed OTG and Client Controller......................................................................24
4.12.2.Universal Serial Bus Host Controller........................................................................................24
Static Memory interface (Compact Flash, Nand flash, host-bus, SRAM, VLIO)................................25
4.13.Power.........................................................................................................................................................27
4.14.Audio.........................................................................................................................................................28
4.15.I2C Bus......................................................................................................................................................29
5.Power supply and management.....................................................................................................................30
5.1.Power Supply..............................................................................................................................................30
5.2.Power consumption..................................................................................................................................30
6.Connectors..........................................................................................................................................................31
6.1.P1....................................................................................................................................................................31
6.2.P2....................................................................................................................................................................34
7.Operational Characteristics............................................................................................................................38
7.1.Absolute Maximum Rating.........................................................................Error!Bookmarknotdefined.
8.Mechanical drawing...........................................................................................................................................39
•SBC Height including BaseBoard connectors: 9mm......................................................................................39
•.......................................................................................................................................................................................40
9.Legal notice.........................................................................................................................................................40
10.Contact information.......................................................................................................................................42

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1. Revision History
Revision No. Draft Date Remarks
1.0 31/Aug/2007 Initial draft
1.1 20/Sept/2007 Ethernet controller revised
2.0 11/Feb/2008
Mechanical change. Smaller form
factor, 6x4cm

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2. Overview
2.1.Basic
The VAR-320SBC is a rich feature set, Single-Board-Computer, ideal for cost and size effective
embedded solutions where high-cpu performance and low power consumption are critical factors.
The VAR-320SBC serves as a building block and easily integrates into any embedded solution. It
includes all vital peripherals/interfaces and is ready to run any embedded operating system such
as Linux, WinCE ™ and Windows Mobile™.
Supporting products:
•Windows CE 5.0 / 6.0 BSP.Contact support for further information.
•VAR-3xxBASEBOARD – Evaluation board.
Package includes:
9Base board. Compatible with VAR-320SBC.
9Windows CE 5.0 / 6.0 run-time-image.
9Schematics
9Layout notes
9Gerber files
Contact support for further information. mailto:[email protected]

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2.2. Features Summary
•Marvell Monahans-P (PXA320) CPU
- Up to 806 MHZ
- 2-D graphic accelerator
- 32kb/32kb Inst/ Data L1 cache
- 256KB L2 cache
- Internal 768kb SRAM
•64-256MB 266MHZ DDR SDRAM
•128Mbytes - 1Gbytes Flash Disk
•802.11 b/g WIFI module Built-In
•CRT/LCD interface. Using 2-D graphic accelerator. Up to 800x600 resolution
supported
•2 SDcard/ SDIO/MMC card interfaces
•A/D - Up to 7 channels. 10KHZ, 10Bit resolution
•Power
- National LP3972 management IC. Supports SpeedStep™ technology to achieve
the most efficient power consumption
- Lowest power solution, down to 3mw in sleep mode
- Single 3.3 - 4.8V DC power supply
•Compact Flash interface
•Intel Quick Capture ™ Camera interface

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•3 UART ports to interfaces GSM/GPRS modem, Bluetooth, IRDA, Debug port
•10/ 100 Mbit Ethernet controller
•General purpose I/O lines.
•Audio
- HI - FI stereo decoder
- Voice CODEC
- Mono output for Speaker
- Microphone input
- Headphones output
•USB
- 1 x full USB host interface
- 1 x USB Client interface
- Connects to an external USB 2.0 host controller
•Touch Screen interface
•Serial controller
- 2 x SSP interfaces
- 1 – Wire
- I2C

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2.3.Block Diagram
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3. Components
3.1.MONAHANS-P CPU
3.1.1. Overview
The PXA320 processor is an integrated system-on-a-chip microprocessor for high-performance,
low-power portable handheld and handset devices. It incorporates the Intel XScale® micro
architecture with on-the-fly voltage and frequency scaling and sophisticated power management
to provide industry leading MIPS/mW performance across its wide range of operating frequencies.
The PXA320 processor complies with the ARM* Architecture V5TE instruction set (excluding
floating point instructions) and follows the ARM* programmer’s model. The PXA320 processor
Multimedia coprocessor provides enhanced Intel® Wireless MMX 2 instructions to accelerate
audio and video processing.

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3.1.2. Monahans-P Block Diagram
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3.1.3. Multimedia co-processor
The core integrates a Multimedia coprocessor to accelerate multimedia applications and 2-D
graphics operations.
This coprocessor provides a 64-bit single-instruction multiple-data (SIMD) architecture and
compatibility with the integer functionality of the Intel® Wireless MMX™ 2 technology and
streaming SIMD extensions (SSE) instruction sets. Key features of this coprocessor include:
• 14 new media processing instructions
• 64-bit architecture including SIMD (up to eight simultaneous eight-bit operations)
• 16 x 64-bit register file
• SIMD PSR flags with group conditional execution support
• SIMD instruction support for sum-of-absolute-differences (SAD) and multiply-accumulate
(MAC) operations
• Instruction support for alignment and video operations
• Intel® Wireless MMX™ 2 and SSE integer instruction compatibility
• Superset of existing core media processing instructions
3.1.4. Power Management
The PXA320 processor provides a rich set of flexible power-management controls for a wide
range of usage models while enabling very low-power operation.
•Programmable frequency-change capability, with turbo settings without requiring the PLL to re-
lock. Supported speeds are: 806 MHz, 624 MHz, 416 MHz, 312 MHz, 208 MHz, 104 MHz
•Five power modes to control power consumption

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3.2.Memory
3.2.1. 266MHZ 32bit DDR SDRAM
The VAR-320SBC supports up to 128MB of DDR SDRAM with clock rate of 266 MHz.
The DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.
3.2.2. NAND flash
The VAR-320SBC supports NAND flashes up to the size of 8Gbit.
The NAND flash is used for Flash Disk purposes, operating system’s run-time-image and the
Bootloader (Boot from NAND).
The NAND flash can be Write-Protected with a dedicated WP# line.
3.3.Power Management IC, National LP3972
The PMIC uses a single 3.3-4.8V DC directly from battery or a regulated source. The PMIC
provides stable, low-noise supplies for all core voltage domains, with additional regulators for
supplying peripheral ICs. All supplies are fed by high-performance, low-dropout (LDO) voltage
regulators and offering very low quiescent current consumption and high power supply rejection.
Three high-efficiency DC-DC buck converters provide high-current, low-voltage supplies to the
processor core and memory. The main converter features Dynamic Voltage Management (DVM),
with programmable voltage and slew rate control.
3.4.Wi2Wi WS2W0001 WIFI module
VAR-320SBC module includes a high-quality built-in 802.11 b/g WLAN module connected to the
SDIO interface.
Chipset: Marvell 88W8686-B1.
Drivers for WinCE™, Linux are available.
3.5.Davicom® DM9000BEthernet controller
High-Performance Single-Chip 10/100 Ethernet controller with HP auto-MDIX and industrial
temperature support

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3.6.Connectors to base board
The VAR-320SBC connects to a base board using 2 140 pin Board-to-Board connectors.
Connector on VAR-320SBC:
Manufacturer: Tyco Electronics
P/N: 1-353190-0
Description: 0.6mm pitch Board-to-Board connector. 140 pin. Free height type.
Mating part to be used on base board:
Manufacturer: Tyco Electronics
P/N: 1-353180-0
Description: 0.6mm pitch Board-to-Board connector. 140 pin Free height type.
4. Interfaces
4.1.TouchScreen
Features:
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•Compatible with 4-wire resistive Touch Screens
•Power is supplied by a dedicated LDO
•Pen-detection and nIRQ generation
•Supports several schemes of measurement averaging to filter noise
•Maximum X & Y sample rate (without averaging): 5 kHz
Signal Pin number Type Description
TSPX P2-88 Analog TSI interface X Plus
TSMY P2-90 Analog TSI interface Y Minus
TSMX P2-92 Analog TSI interface X Minus
TSPY P2-94 Analog TSI interface Y Plus
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4.2.SSP Interface
The VAR-320SBC outputs one SSP interface.
The SSP controllers support these protocols:
9Programmable serial protocol (PSP) with programmable frame sync and programmable
start and stop delays
9Texas Instruments Synchronous Serial Protocol* (SSP)
9Motorola Serial Peripheral Interface* (SPI) protocol
9Inter-IC Sound (I2S) protocol
•Up to 13-Mbps transfer rate with internal clock generation
•Packed mode to 1w double-depth FIFOs if sample less than 16 bits wide
•Sample data formats from 8, 16, 18, and 32 bits of serial data
•Network mode for operation on a time-slotted bus
•Master or slave operation for both clock- and frame-sync signals
•Receive-without-transmit operation
•Flexible clock source selection from the 13-MHz master clock, the network clock input, or
the dedicated SSP
•External clock input
•Audio clock control to provide a 4x or 8x output clock to support most standard audio
frequencies
Signal Pin
number Type Description GPIO
SSP4_SCLK P2-54 I/O Synchronous Serial Protocol Serial Clock 93
SSP4_SFRM P2-56 I/O Synchronous Serial Protocol Serial Frame Indicator 94
SSP4_TXD P2-58 O Synchronous Serial Protocol Transmit Data 95
SSP4_RXD P2-60 I Synchronous Serial Protocol Receive Data 96
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4.3.UART Ports
The VAR-320SBC outputs 3 UARTs
•Full function UART (FFUART)
•Bluetooth UART (BTUART)
•Standard UART (STUART)
Each serial port contains a UART and a slow serial infrared transmit encoder and receive decoder
that conform to the IrDA serial infrared specification.1
Each UART includes a programmable baud-rate generator. The supported baud rates are 9600,
19.2 K, 38.4 K, 57.6 K, 115.2 K, 230 K, 460 K, and 921 K.
Receive and transmit FIFO fill and drain operations can be done using programmed IO or DMA
transfers. To minimize CPU overhead for UART communications, device driver software can
setup interrupts and DMA for data transfers to/from memory.
All three UARTs support the 16550A and 167502 functions.
Full function UART (FFUART) signals:
Signal Pin number Type Description GPIO
FFRXD P1-27 I FFUART RXD 41
FFTXD P1-29 O FFUART TXD 42
FFDCD P1-33 I FFUART DCD 44
FFDTR P1-35 O FFUART DTR 47
FFDSR P1-37 I FFUART DSR 45
FFCTS P1-39 I FFUART CTS 43
FFRTS P1-41 O FFUART RTS 48
FFRI P1-45 I FFUART RI 46
Bluetooth UART (BTUART) signals:
Signal Pin number Type Description GPIO
BT_TXD P1-22 O BT UART TXD 111
BT_RXD P1-24 I BT UART RXD 110
BT_CTS P1-28 I BT UART CTS 112
BT_RTS P1-30 O BT UART RTS 109
Standard UART (STUART) signals:
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Signal Pin number Type Description GPIO
STD_TXD P1-42 O ST UART TXD 107
STD_RXD P1-44 I ST UART RXD 108
4.4.SD/MMC Ports
The VAR-320SBC outputs 2 SD/MMC ports.
The MultiMediaCard (MMC) and Secure Digital (SD/SDIO) controller (MMC/SD/SDIO controller)
provide a software-accessible hardware link between the PXA320 and the MMC stack (a set of
memory cards). The MMC/SD/SDIO controller supports Multimedia Card, Secure Digital, and
Secure Digital I/O communication protocols. The PXA320 contains two independent
MMC/SD/SDIO controllers.
•1-bit and 4-bit data transfers are supported for MMC, SD, and SDIO communication
protocols
•Data transfer clock of 19.5 MHz
•Support for all valid MMC and SD/SDIO protocol data-transfer modes
•Interrupt-based application interface to control software interaction
•Multiple MMC cards are supported when using the MMC communications protocol
•Only one SD or SDIO card is supported when using the SD or SDIO communications
protocol per controller.
•Up to two MMC or SD/SDIO cards are supported when using the SPI communications
protocol. Mixed card types are supported only by the SPI communications protocol per
controller.
Signal Pin number Type Description GPIO
MMC_CLK P1-102 O SD/MMC Bus clock 22
MMC_CMD_0 P1-104 O SD/MMC Command 23
MMC_DAT_0 P1-112 I SD/MMC Data 18
MMC_DAT_1 P1-114 I SD/MMC Data 19
MMC_DAT_2 P1-116 O SD/MMC Data 20
MMC_DAT_3 P1-118 O SD/MMC Data 21
MMC2_CLK P1-120 O SD/MMC 2 Bus clock 28
MMC2_CMD P1-124 O SD/MMC 2 Command 29
MMC2_DAT_0 P1-126 I SD/MMC 2 Data 24
MMC2_DAT_1 P1-128 I SD/MMC 2 Data 25
MMC2_DAT_2 P1-130 O SD/MMC 2 Data 26
MMC2_DAT_3 P1-132 O SD/MMC 2 Data 27
4.5.LCD Interface
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The LCD controller supports these key features:
•Support for active or passive single-panel displays of 8, 16, or 18 bpp
•Support for LCD panels with internal frame buffer; up to 24 bpp is supported
•Support display sizes up to 800x600 pixels.
Signal Pin number Type Description GPIO
L_PCLK P2-1 O LCD Pixel clock 16_2
L_FCLK P2-3 O LCD Frame clock 14_2
L_LCLK P2-5 O LCD Line clock 15_2
L_BIAS P2-9 O LCD AC bias/Data enable 17_2
L_DD_0 P2-11 O LCD Data line 6_2
L_DD_1 P2-13 O LCD Data line 7_2
L_DD_2 P2-15 O LCD Data line 8_2
L_DD_3 P2-17 O LCD Data line 9_2
L_DD_4 P2-21 O LCD Data line 10_2
L_DD_5 P2-23 O LCD Data line 11_2
L_DD_6 P2-25 O LCD Data line 12_2
L_DD_7 P2-27 O LCD Data line 13_2
L_DD_8 P2-29 O LCD Data line 63
L_DD_9 P2-33 O LCD Data line 64
L_DD_10 P2-35 O LCD Data line 65
L_DD_11 P2-37 O LCD Data line 66
L_DD_12 P2-39 O LCD Data line 67
L_DD_13 P2-41 O LCD Data line 68
L_DD_14 P2-45 O LCD Data line 69
L_DD_15 P2-47 O LCD Data line 70
L_DD_16 P2-16 O LCD Data line 71
L_DD_17 P2-18 O LCD Data line 72
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4.6.JTAG Port
JTAG provides a way of driving and sampling the external pins of the device regardless of the
core state, as well as a mechanism for device debug. JTAG logic includes a test-access port
(TAP) controller, TAP pins, an instruction register, and Test Data registers (TDRs). The JTAG
interface is controlled through five dedicated TAP pins that interface to the TAP controller: TDI,
TMS, TCK, nTRST, and TDO.
Signal Pin number Type Description
NTRST P2-128 I JTAG Test Reset
TDI P2-130 I JTAG Serial data input
TMS P2-132 I JTAG Test Mode Select
TDO P2-136 O JTAG Serial data output
TCK P2-138 I JTAG Test Clock
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4.7.1-Wire
The 1-Wire bus master interface controller is designed to receive and transmit 1-Wire bus data
and provides complete control of the 1-Wire bus through eight-bit commands.
The 1-Wire bus serial operation uses an open-drain, wired-AND bus structure that allows multiple
devices to drive the bus lines and to communicate status on events such as arbitration, wait
states, and error conditions.
Signal Pin
number Type Description GPI O
ONE_WIRE P1-64 I/O Open-drain 1-Wire bidirectional data bus. 0_2
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