ViewSonic VG181 User manual

VIDE-V27608
Service Manual
ViewSonic VG181
Model No. VLCDS21594-1
18” Color TFT LCD Display
VG181_SM_104 - Rev. 1 — September 2005)
ViewSonic® 381 Brea Canyon Road, Wainut, California 91789 USA - [phone]

Copyright
Copyright © 1998 by ViewSonic Corporation. Alf rights reserved. No part of this publication may be
reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or
computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical,
manual or otherwise, without the prior written permission of ViewSonic Corporation.
Disclaimer
ViewSonic makes no representations or warranties, either expressed or implied, with respect fo the
contents hereof and specifically disclaims any warranty of merchantability or fitness for any particular
purpose. Further, ViewSonic reserves the right to revise this publication and to make changes from time to
fime in the contents hereof without obligation of ViewSonic to notify any person of such revision or
changes.
Trademarks
ViewSonic is a registered trademark of ViewSonic Corporation.
All other trademarks used within this document are the property of their respective owners.
Revision History
Description Of Changes Approval
9/15/00 _| Initial Issue — DCN683 —_
if ; VG181 Service Manual

TABLE OF CONTENTS
PRECAUTIONS AND SARETY NOTICES ws. 03 .cssiccca Nts aie Bae ee a utes 2
BE ATURES siccicsesstis so etatuhe slg eiSena tue aca teuty iedgecscceaaesidecshsndlh Sach enc tb occ szaten decane uligesedlantvaatenandedeaeeNusdea slabs 3
SPECIFICATIONS icc cs Scnscipesestecectdtasatbuecsideed onxetareusdstec Satdecsaudsex'slWanloes dgvechestents ides dSecaithes Citta aczecducds sheteceadsaxds 4
ON SCREEN’ DISPICAY eccescitd is cag sesiceca,ccsedh stnstaaterSocxteet den Sects a he enh easiness 5
FACTORY PRESE P-TIMINGS fsesecjececertivaxssccassreceussosanstuceossbeeteardiessucclcleucasszesueceositeutgcetetvacceusleadinadaadeacdiveuy 6
PIN PASSIGNMEN TES vhs c.csjuescseessictesdbesvadsontesssdoededecsvincdeccentsceabevesed ise ccusdui esses visa wetter artorsa dodusbledeateiablsct 7~8
MAIN BOARD VO CONNECTIONS ou. ccecescesesececesenscnseevsssseasencesssscesesesneataneesesscsenesseneesensseeaesesseeessens 9
THEORY. OF ‘ORERA TION siccessiessccnssstsesastvasvenssseseasscondseos suaseseoats sacsauterstaeaiahae igacesveeses foivardesustedseceveries 10~32
WAVEFORMS 30 iascvcsscsads oud sisces cas dsedel secaseznrsusvessteczt agendas caste stas sade saukce sccbeesoedushleadenetecaavecdbansbahdactadeisxsy 33~39
TROUBLESHOOTING GUIDE wicccisie. cccectbeateccsectecescscbusaccedbuuecvesssdecsesuescenceccccdtestdacssdeaaducniaesdesacobesseers 40~44
SPARE PARTS LISD ssosccssse Si descss sca sadsvuncciassvissieivadeas dyes cscs decyag cuss belde en nace cas badcanyih scbtpacassennlgeeiaes SZccvad docks 45
COMPEETE PARTS: DIS Viivagucs. of. ccdedaccazsesseetacgasiocuectesutueds uu svetesesosodsecsentoal sdeus vabelappaceessstuvesss caiieereeed 46~62
SCHEMATIC DIAGRAMS | oic2c50. 8s scuba saviaartvannarsseseveurea satnede oSensanabetetlactetedbsrtermtezentusaseecaetiel alias 63~69
EXPLODED VIEW AND PARTS LIST. .......ccsccsssssssssssssssssatsssscsossnsersenscaceeacseseseerseseseessenseeneeasensecsensnem outs 70
PRIS TT ORDEAL OL LAD OE TI NE EOL NEY EL EEE LE EM IARI LEA NOVEL EI OE ADELA LEE T OIE IE LE LF I TEE EE ELE I GE CLIN EE
iii VG181 Service Manal

Service Manual ViewSonic
VG181 July 2000 - Version 1.0
Copyright © VIEWSONIC CORPORATION, 2000 All Rights Reserved.
IBM and IBM products are registered trademarks of International Business Machines Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
ViewPanel, ViewSonic, the three birds logo, OnView, ViewMatch, and ViewMeter are registered
trademarks of ViewSonic Corporation.
VESA is registered trademarks of Video Electronics Standards Association. DPMS and DDC are
trademarks of VESA.
Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).
Disclaimer : ViewSonic Corporation shall not be liable for technical or editorial errors or omissions
contained herein ; nor for incidenta! or consequential damages resulting from furnishing this
material, or the performance or use this product.
In the interest of continuing product improvement, ViewSonic Corporation reserves the right to
change product specification without notice. Information in this document may change without
notice.
No part of this document may be copied, reproduced or transmitted by any means for any purpose
without prior written permission from ViewSonic Corporation.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference in a residential installation. This equipment generates, uses and can
radiate radio frequency energy, and if not installed and used in accordance with the instructions,
may cause harmful interference to radio communications. However, there is no guarantee that the
interference will not occur in a particular installation. If this equipment does cause unacceptable
interference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following
measures -- reorient or relocate the receiving antenna; increase the separation between equipment
and receiver; or connect the into an outlet on a circuit different from that to which the receiver is
connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and the
provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized changes or
modifications to Amtrak products will void the user's authority to operate this device. Thus
ViewSonic Corporation will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows — USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance
Control Act); or an AC cord that meets the local safety standards.
Page 2
Confidential - Do Not Copy

ViewSonic Service Manual
July 2000 - Version 1.0 VG181
FEATURES
The VG181 is a world class TFT LCD display that includes the following features.
le
Digital On Screen Display Controls
User friendly buttons (71), Select (w/ 4) (2), Power] allowing for picture perfect
quality. Users can define display modes or reset to default settings. The main
menu contains : Contrast / Brightness ; Image Adjust ; Viewmach Color;
Advanced Menu ; Setup Menu ; Memory Recall and Exit.
Power Supply Support
The separate AC adapter accepts voltages from 90~264 Vac (Universal),
allowing for a full range of input AC sources.
Power Saving System
This environmental friendly product can reduce power consumption
by more than 95% in the Active Off mode.
Frequency Range
The display can support video standards from VGA to SXGA, with a Horizontal
frequency range from 30~82kHz and a Vertical frequency range from
50~75 Hz.
Page 3
Confidential - Do Not Copy

Service Manual
SPECIFICATIONS
LCD Pane!
Maximum Viewing
Angles
Signal Input
Connector
Maximum Resolution
Video Bandwidth
Display Area
Power Voltage
Power Consumption
Operating Conditions
Storage Conditions
Dimensions
ViewSonic
July 2000 - Version 1.0
18.1 inch diagonal viewable screen, Anti-glare TFT Active
Matrix Panel, 0.2805mm pixel pitch
Horizontal 160°CR>10
Vertical 160°CR>10
Video : RGB analog, 0.7/1.0 Vp-p, 75 ohms
Composite Sync, Separate Sync,
Sync On Green, fp: 30-82 kHz, fy. 50-75 Hz
Analog : 15 Pin Mini D-Sub
Digital: 24 Pin DVI_D
1280x1024
135 MHz nominal
359.00 mm (H) x 287.2 mm (V)
90~264Vac @ 50/60 Hz (auto switch), 12Vdc 6A
70 W max.
Temperature :32 to 104 (0 to 40 )
Humidity : 10% to 90% (no condensation)
Altitude : To 10,000 feet
Temperature :-4 to+140 (-20 to+60 )
Humidity : 10% to 90% (no condensation)
Altitude : To 40,000 feet
Physical : 460mm (W) x 458.8mm (H) x 240mm (D)
10.0 kgs
Page 4
Confidential - Do Not Copy

ViewSonic
July 2000 - Version 1.0
ON SCREEN DISPLAY
Service Manual
VG181
The OSD (On Screen Display) function is supported and controlled by four easy to
use buttons -{1], Select , Select ,
Conitrast/ Brightness
Image Adjust
Viewmaitch Color
Advanced Menu
Set Menu
[2], Power.
Contrast
Brightness
Auto Tune
H/V. Position
H. Size
Phase
Zoom
Color Temp Select
User Color
Scaling
Sharpness
ViewMeter
Input Select
Language Select
OSD Position
OSD Timeout
Page 5
Confidential - Do Not Copy

Service Manual ViewSonic
VG181
July
2000
-
Version
1.0
FACTORY PRESET TIMINGS
These timings are preset for the analog & digital me
Timing Horizontal | Horizontal | Vertical Vertical
________—|_Polarity {Frequency} Polarity | Frequency |
VGA 640x350 31.47 kHz 70.09 Hz
VGA 720x400 31.47 70.08
VGA 640x400 31.47 70.09
VGA 640x480 31.47 59.94
VESA 640x480 37.86 72.81
VESA 640x480 37.50 75.00
MAC 640x480 35.00 66.67
VESA 800x600 35.15 56.25
VESA 800x600 37.88 60.32
VESA 800x600 48.08 72.19
VESA 800x600 46.88 75.00
MAC 832x624 49.72 74.55
VESA 1024x768 48.36 60.00
VESA 1024x768 56.48 70.07
VESA 1024x768 58.04 71.92
VESA 1024x768 60.02 75.03
MAC 1024x768 60.24 74.92
VESA 1280x1024 68.981 60.02
VESA 1280x1024 79.98 75.03
VESA 1152x864 67.50 75.00
VESA 1280x960 60.00 60.00
Composite
+
+
+
+
Composite
Page 6
Confidential - De Not Copy

ViewSonic
July 2000 - Version 1.0
PIN ASSIGNMENT
Service Manual
VG181
The analog input uses a 15 Pin Mini D-Sub connector.
Green
Blue
Ground
Ground
R-Ground
G-Ground
B-Ground
No Connection
Ground
No Connection
(SDA)
H-Sync (Composite Sync)
V-Sync
(SCL)
Page 7
Confidential - Do Not Copy

Service Manual
VG181
PIN ASSIGNMENT
The digital input use a 24 Pin DVI_D connector.
Logic Ground
Reserved. No connection
Reserved. No connection
DDC2B Clock
DDC2B Data
Reserved. No connection
oO MAN OT FWD =
— ©
—_, oh
Logic Ground
_
np
Reserved. No connection
—_ ie)
Reserved. No connection
=_— f
Power
ay on
Logic Ground
SENSE Pin, Pull High
ces
Oo ON OD
Logic Ground
nN fo)
Reserved. No connection
N =~
Reserved. No connection
nN NO
Logic Ground
hm bh -& WwW
| Pin | Description
TMDS negative differential input, channel 2
TMDS positive differential input, channel 2
TMDS negative differential input, channel 1
TMDS positive differential input, channel 1
TMDS negative differential input, channel 0
TMDS positive differential input, channel 0
TMDS positive differential input, reference clock
TMDS negative differential input, reference clock
Page 8 ©
Confidential - Do Not Copy
ViewSonic
July 2000 - Version 1.0

ViewSonic
July 2000 - Version 1.0
Service Manual
VG181
MAIN BOARD I/O CONNECTIONS
. JP4 CONNECTION (TOP BOTTOM) "OSD CONTROL"
| in Description —_|
—)
oon om a & WO HY
JP5 CONNECTION (LEFT RIGHT)
au Key
” Function " Key
"+" Key
Auto
LED 1
LED 2
Ground
Power 1
Power 2
VCON
Ground
Ground
Ground
VDD
VDD
VDD
Page 9
Confidential - Do Not Copy

Service
Manual
ViewSonic
VG181
July
2000
-
Version
1.0
THEORY OF CIRCUIT OPERATION
The operation of keypad
The
OSD
is
controlled
through
five
pins
and
an
LED.
As
shown
on
the
previous
page,
they
are
Power,
Auto,
+,
Function,
and
—
keys,
and LED.
1.
The
power
key
through
POW1
and
POW2
is
used
to
control
ck
of
CD4013.
A
pulse
is
sent
to
control power
while
pressing
the
power
key.
2. After power on, the other four keys are in the high state due to the pull up
resistor. They will transition to a low state dependent on which key is
pressed. The state will be determined by the PW364 through PORTCO to
PORTCS to activate the corresponding function.
3.
The
LED
is
bi-colored
with
green
and
orange
selections.
The
PW364
controls
the
LED’s through
PORTC4
and
PORTCS.
During
normal
operation
the
POCTCS5
(LED2)
is
set to a
high state
and
PORTC4
(LED1)
is
set
to a
low
state. These
will
reverse
during
power
saving.
Operation of the clock
1CS501
is
used
to
generate
the
memory
system
clock
(MCKEXT)
and
display
clock (DCKEXT). The power of ICS501 is filtered through L10, L31 and L32.
1. During normal operation the PW364 sets PORTA7 (CLKEN) to a high state
and enables CLK to output 100MHz.
2. While in the power saving mode, the PW364 sets PORTA7 (CLKEN) to a
low state and disables the CLK output. In this mode the LED is orange and
the screen is blank.
Page 10
Confidential - Do Not Copy

ViewSonic Service Manual
July 2000 - Version 1.0 VG181
THEORY OF CIRCUIT OPERATION
The function block and parameters of ICS501 are as follows :
VDD GND
PLL
Clock Muitiplier
Circuitry
Crystal or
clock input
Output
Buffer
Crystal
Dscillatoy
Output Enable
a a <a
oo | oo | axinput
| M__| 5.3125x input
1
oso |
ae eae a
mM | of 625xinput
pm} Mf xin
pm | tf 8 t25X input
1 | od exinput
pa | sxinput
a eel
0 : direct connected to GND
1 : direct connected to VCC
M : leave unconnected (floating)
Page 11
Confidential - Do Not Copy

Service
Manual
ViewSonic
VG181
July
2000
-
Version
1.0
THEORY OF CIRCUIT OPERATION
THE OPERATION OF THE ANALOG PORT
The
analog
port
is
a
15
pin
mini
D-Sub
connector
for
receiving
the
video
signal
from
the
host
device.
It
features
an
EEPROM
which
complies
with
the
DDC1/DDC2B
protocol,
H-syne
and
V-sync
detecting
circuitry
which
regenerates
a
synchronous
signal
for
PW364
detection,
video
signal
matching
circuitry,
and
a
AD9884A
for
capturing
the
RGB
graphics
signal
and
digitizing
each
pixel.
The pin assignments of the 15 pin connector are shown below:
GGAl
15
The
RGB
graphics
signal
of
the
host
device
is
transmitted
to
the
analog
port
through
pins
1
to
3.
The
transmission
lines
should
be
75ohm
resistance
matched
at
R18,
R19
and
R20.
Over
voltage
protection
is
provided
by
D5,
D6
and
D7.
The
video
signal
should
be
coupled
to
RIN,
GIN,
BIN
and
SOGIN
of
AD9884A
through
C42,
C47,
C48
and
C49.
The
EDID
data
is
stored
in
EEPROM
(24LC21)
which
complies
with
the
DDC1/DDC2B
protocol
that
performs
a
plug
and
play
function.
When
in
DDC1
protocol,
the
host
device
accesses
the
EDID
data
through
RVSI
(pin14)
and
RGSA
(pin12)
while
RGSL
(pin15)
is
held
high.
However,
in
DDC2B
protocol
the
host
device
accesses
EDID
data
through
RGSA
(pin12)
and
RGSL
(pin15).
The
GSCL,
GSDA
and
GVSI
pins
should
be
pulled
up
through
R5,
R6
and
R7.
Over
voltage
protection
is
provided
by
D1,
D2,
D3
and
ZD4
with
a
clamping
limit
of
5
volts.
Page 12
Confidential - Do Not Copy

ViewSonic Service Manual
July 2000 - Version 1.0 VG181
THEORY OF CIRCUIT OPERATION
The PW364 sets PORTB3 (ASYOE) to a high state that will allow 74LCX125 (U10)
to output the GHS and GVS signals which are then detected at GHS! (pin 13) and
RVSI (pin 14). When GHS and GVS are detected, the PW364 will configure the
registers of AD9884A to satisfy the operation through SCL and SDA of I°C bus.
Conversely, when PW364 sets PORTB3 (ASYOE) to a low state, the analog port is
disabled and the display is in the digital interface mode or power saving mode.
The AD9884A is an 8-bit, 140 Msps, monolithic analog interface for capturing RGB
graphics signals from personal computers and workstations. It includes +1.25V
reference, PLL to generate a pixel clock from Hsync, and programmable gain,
offset , and clamp circuits .
The functional block diagram of AD9884A is shown below:
RoutA
RoutB
GoutaA
GoutB
BoutA
BoutB
HSYNC 2 DATACK
COAST HSOUT
CLAMP
Generator
CKINV
CKEXT
&
2
Oo
es z & a @ « Fi
qQ > m A
= H uv
q o 3 ae A a
hy Oo 9 ind io
L3 ,2) =
1} Aa
Page 13
Confidential - Do Not Copy

Service
Manual
ViewSonic
VG181
July
2000
-
Version
1.0
THEORY OF CIRCUIT OPERATION
If
the
user
changes
to
analog
mode
or
the
analog
port
is
reactivated
from
the
host
device,
then
the
PW364
will
set
PORTB3
(ASYOE)
and
PORTB2
(ADCOE)
to
high
states
to
enable
H-Sync,
V-Sync,
and
AD9884A.
The
PW364
will
change
the
PLL
division
ratio,
clock
phase,
VCO
range,
charge
pump
current,
etc.,
depending
on
the
timing
of
GHS
and
GVS.
The
action
should
be
fulfilled
through
SDA
and
SCL
of
the
I?C
bus
to
change
the
data
of
control
registers
of
AD9884A.
The
PLL
derives
a
master
clock
from
the
incoming
H-Sync
signal.
The
master
clock
frequency
is
then
divided
by
an
integer
value,
and
the
divider’s
output
is
phase-locked
to
H-
Sync.
The
PLL
characteristic
is
determined
by
the
loop
filter
design
which
is
controlled
by
PLL
charge
pump
current
(CURRENT)
and
VCO
range
setting
(VCORNGE).
The values of VCO range and charge pump current are shown below:
_Voornge
| oo | so |
| oo | 100
20-60
50-90
10 80-120
11 110-140
| 100 | so
| tor | 00
| ant | 1500
Whenever
the
contrast
or
brightness
of
the
analog
port
is
adjusted,
then
the
input
gain
or
input offset should
be
adjusted
through
the
IC
bus.
The
power
of
AD9884A
is
controlled
by
PORTB5
(PWAD)
of
Pw364
and
filtered
by
L22,
111,
L12
and
L13.
The
H-Syne
input
is
used
as
a
reference
to
generate
the
pixel
sampling
clock.
A
5-bit
value
(PHASE)
adjusts
the
sampling
phase
in
32
steps
across
one
pixel
time,
to
generate
a
stabie
timing
relationship
between
HSOUT
and
DATACK.
The
captured
analog
RGB
data
is
digitized
and
output
to
odd
and
even
data
channel
port
A
and
port
B.
The
output
data
is
aligned
to
the
leading
edge
of
HSOUT.
If
the
signal
of
sync
on
green
is
detected
by
SOGIN
then
the
SOGOUT
will
produce
a
digital
composite
sync.
Conversely,
if
the
analog
port
is
disabled,
then
PORTB3
(ASYOE)
and
PORTB2
(ADCOE)
of
PW364
will
be
in
the
low
state
setting
the
AD9884A
to
power
down
mode
and
all
outputs
of
AD9884<A
to
tristate
.
001
011
104
114
Page 14
Confidential - Do Not Copy

ViewSonic Service Manual
July 2000 - Version 1.0 VG181
THEORY OF CIRCUIT OPERATION
The operation of PW364
The PW364 is a highly integrated “System on a chip“ that interfaces computer
graphics and video inputs in virtually any format to a fixed frequency flat panel
display. An embedded DRAM frame buffer and memory controller perform frame
rate conversion. Computer images from VGA to SXGA resolution input to the chip
can be resized to fit on the target display device. The on-chip microprocessor
incorporates a frame buffer, resizing circuitry and peripheral circuit for frame rate
conversion, image scaling, automatic image optimization, picture in picture, on
screen display and user adjustment.
The intemal block diagram of PW364 is shown below:
PORTA{7: 0) NMI
» WR A{19:0} PORTB{7?:0) EXTINT TRRCVR
CS{3:0) D(15:0) CPUEN PORTC (7:0) WOTEN (1:0) RxD TxD (1:0)
Internal
Register
Interface
jemory 3
Interfac:
SDRAM
frame
buf far
Cle
Generator
REF HFBK CLKIN , MCKEXT
DCKEXT , UCSRC
The interface of PW364 is composed of a microprocessor interface, graphics port
and display port.
Microprocessor interface
When power is present and the power key is pressed, then the reset circuit sets
RESET to a high state and the PW364 to the initial state. After that, the RESET
will transition to a low state and the PW364 starts to work. The microprocessor
executes the programs and configures the internal registers. The execution speed
of the CPU is determined by MCKEXT. The normal frequency is 125 MHz, but is
40 MHz while in power saving. The D[15:0] , A[19:1] , RDN , ROMOEN and
ROMWEN are used to access external FLASH memory.
The GPiO block incorporates three 8-bit general purpose i/O ports. Each bit in
each port is individually controllable as either input or output.
Page 15
Confidential - Do Not Copy

Service Manual ViewSonic
VG181 July 2000 - Version 1.0
THEORY OF CIRCUIT OPERATION
The three ports are configured as shown below:
porta |x | |
PPORTAS. [xe |
PorTAS |LcDPWON | ouput
Portas |x |
PORTA7 | CLKEN Output
MCKEXT
Power on of digital port
Digital port output enable
Ipornta2 |ADCOE {Output Analog port output enable
Analog port sync. enable
lporTas [scot [input _| Digital sync. detect
Iporntss |PwaD {output Power on of analog port
pores |x |
ae i
input
Panel Enable
Voltage control of power saving
m
b>)
> S ro} Q Oo QO
g » 3
a =.
a
> >
©
Q
c 0)
=] °
<
Q Q } x
° So
Input Key detection
Key detection
Key detection
Key detection
PORTC4 | PORTC4 LED
LED
PORTC7 |X
Page 16
Confidentiat - Do Not Copy

ViewSonic Service Manual
July 2000 - Version 1.0 VG181
THEORY OF CIRCUIT OPERATION
Graphics port
The graphics port (Gport) is an input interface for high speed RGB data (up to
SXGA). It accepts incoming data at one or two pixels per clock. It also has a sync
separator circuit, timing signals for PLL control, clock buffering and conditioning
circuitry. The graphics port has two input sources from an analog port and a digital
port. Analog and digital data cannot be processed simultaneously. This is
controlled through ADCOE and TMDSOE.
The block diagram of graphics port is shown below:
Data Register
and
Multiplexer
Memory
Interface
GREF
GFBK
GBLKSPL
GCOAST
GHSFOUT
PLL
Control
Page 17
Confidential - Do Not Copy

Service Manual ViewSonic
VG181 July 2000 - Version 1.0
THEORY OF CIRCUIT OPERATION
The sync decoder detects and processes the horizontal sync (GHS), vertical syne
(GVS)
,
sync
on
green
(GSOG)
,
and
field
(GFIELD)
inputs
used
for
timing.
There
are
several
bits
to
indicate
the
status
of
the
inputs.
For
horizontal
sync,
HSOK=1
indicates
that
the
horizontal
line
rate
is
faster
than
10KHz.
For
vertical
sync,
VSOK=1 indicates that the vertical field or frame rate is faster than 10Hz. For sync
on green, SOGACT=1 indicates that transitions on GSOG are occurring faster than
10Hz.
The
PLL
control
block
generates
the
timing
signals
required
for
an
external
PLL.
GCOAST
is
an
output
used
to
tell
the
PLL
to
coast
during
vertical
blanking.
This
is
used
to
keep
the
PLL
from
making
spurious
change
due
to
extra
or
missing
HSYNC
pulses.
Output
GREF
is
a
polarity
corrected
delayed
version
of
the
active
horizontal
sync
signal
.
GREF
is
delayed
from
the
input
HSYNC
by
an
amount
specified
by
register
PHASE(7:0)
.
Changing
PHASE
will
change
the set
up
/hold
time relationship
between
the sample
clock
and the
data coming
into
the
external
ADC.
Output GHSFOUT is the field output signal used to tell an external ADC whether
even or odd pixels are being captured during half sample mode.
When EXTFCE=1 the external flow control is enabled, each new line is marked by
an
edge
on
the
GLAVIN
input
(pin
GFBK),
but
while
EXTFCE=0
the
GFBKINinput
(pin GFBK) is used as the input HSYNC signal for pixel counters.
Display port
The
display
port
processes
and
prepares
the
data
for
display.
The
output
data
is
sent
out
on
pins
DRE(7:0)
,
DGE(7:0)
,
DBE(7:0)
,
DRO(7:0)
,
DGO(7:0)
and
DBO(7:0)
that
is controlled
by
display
timing generator
.
The block diagram of display port is as follows :
Scaled
Display
Data
DRE[7: 0}
DGE[7:0}
DBE[7:0]
on
Screen
Display
Overlay
Ate DRO[7: 0}
ata
DGOI7:0}
DBO[7:0}
Display
Timing
Generator
DCKEXT
Page 18
Confidential - Do Not Copy
era A ae te RR