Waveshare 13.3 e-Paper (K) User manual

13.3in
ch e-Paper (K)
User Manual
www.waveshare.com/wiki
13.3inch e-Paper (K)
User Manual

13.3inch e-Paper (K)
User Manual
Revision History
Version
Content
Date
Producer
1.0
Revision 1.0
2023/07/03

13.3inch e-Paper (K)
User Manual
Contents
1. OVERVIEW .....................................................................................................................................1
2. FEATURES ..................................................................................................................................... 2
3. MECHANICAL SPECIFICATION ............................................................................................... 3
4. MECHANICAL DRAWING OF EPD MODULE ........................................................................ 4
5. INPUT/OUTPUT PIN ASSIGNMENT ........................................................................................ 5
6. COMMAND TABLE ....................................................................................................................... 7
7. ELECTRICAL CHARACTERISTICS ........................................................................................14
7.1 Absolute Maximum Rating ...............................................................................................14
7.2 Panel DC Characteristics ................................................................................................ 15
7.3 Panel DC Characteristics (Driver IC Internal Regulators) ...................................... 16
7.4 MCU Interface .................................................................................................................... 17
7.4.1 MCU Interface Selection .............................................................................................. 17
7.4.2 MCU Serial Interface (4-wire SPI) ................................................................................17
7.4.3 MCU Serial Interface (3-wire SPI) ................................................................................19
7.4.4 Interface Timing ............................................................................................................ 21
7.5 Reference Circuit ...............................................................................................................23
8. BLOCK DIAGRAM .......................................................................................................................24
9. MATCHED DEVELOPMENT KIT ............................................................................................. 25
10. TYPICAL OPERATING STATUS ...........................................................................................26
10.1 Reference Circuit ............................................................................................................ 26
10.2 Reference Circuit ............................................................................................................ 27
11. RELIABILITY TEST .................................................................................................................. 28
12. QUALITY ASSURANCE .......................................................................................................... 29
12.1 Environment ......................................................................................................................29
12.2 Illuminance ........................................................................................................................29
12.3 Inspect method ................................................................................................................ 29

13.3inch e-Paper (K)
User Manual
12.4 Display area ......................................................................................................................29
12.5 Ghosting test method ..................................................................................................... 29
12.6 Inspection standard ........................................................................................................ 31
12.6.1 Electric inspection standard ....................................................................................... 31
12.6.2 Appearance inspection standard ................................................................................32
13. HANDLING, SAFETY, AND ENVIRONMENT REQUIREMENTS ................................... 34
14. PRECAUTIONS ......................................................................................................................... 35

13.3inch e-Paper (K)
User Manual
1
1. OVERVIEW
13.3 e-Paper (K) is an Active Matrix Electrophoretic Display (AM EPD), with interface and a
reference system design. The display is capable to display image at 1-bit white and black full display
capabilities. The 13.3inch active area contains 960x680 pixels. The module is a TFT-array driving
electrophoresis display, with integrated circuits including gate driver, source driver, MCU interface,
timing controller, oscillator, DC-DC, SRAM, LUT, VCOM. Module can be used in portable electronic
devices, such as Electronic Shelf Label (ESL) System.

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User Manual
2
2. FEATURES
960×680 pixels display
High contrast High reflectance
Ultra wide viewing angle Ultra low power consumption
Pure reflective mode
Bi-stable display
Commercial temperature range
Landscape portrait modes
Hard-coat antiglare display surface
Ultra Low current deep sleep mode
On-chip display RAM
Waveform can stored in On-chip OTP or written by MCU
Serial peripheral interface available
On-chip oscillator
On-chip booster and regulator control for generating VCOM, Gate and Source driving voltage
I2C signal master interface to read external temperature sensor
Built-in temperature sensor

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User Manual
3
3. MECHANICAL SPECIFICATION
Parameter
Specification
Unit
Remark
Screen Size
13.3
Inch
Display Resolution
960(H) x 680(V)
Pixel
DPI:88
Active Area
275.52 x 195.16
mm
Pixel Pitch
0.287 x 0.287
mm
Pixel Configuration
Rectangle
Outline Dimension
286.32(H) x 212.26 (V) x 1.20(D)
mm
Weight
106.7±0.5
g
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Notes
KS
Back State L*value
-
18
20
3-1
Back Ghosting ∆L
-
1
-
3-1
WS
White state L*value
66
67
-
3-1
White Ghosting ∆L
-
1
-
3-1
R
White Reflectivity
White
30
34
-
%
3-1
CR
Contrast Ratio
Indoor
15:1
20:1
-
3-1
3-2
GN
2 Grey Level
-
-
-
-
Life
Temp:23±3℃
Humidity: 55±10%RH
5 years
-
3-3
Notes:
3-1. Luminance meter: Eye-One Pro Spectrophotometer.
3-2. CR=Surface Reflectance with all white pixel/Surface Reflectance with all black pixels.
3-3. When the product is stored. The display screen should be kept white and face up.

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User Manual
4
4. MECHANICAL DRAWING OF EPD MODULE
Confirmation:
MO D I F I C AT I ON
DA T E
RE V.
NOTE
1 DISPLAY MODULE 13.3" ARRAY FOR EPD 2
DRIVER IC:SSD1677
3 RESOLUTION：680gateX960source
4 PIXEL SIZE:0.287mmX0.287mm
TOLERANCE UNMARKED
TITLE
EPD
PROJECT
13.3” e-Paper (K)
UNIT:
mm
ANGLES±5º
.X=±0.4mm
.XX=±0.20mm
.XXX=±0.20mm
REV:
A
3RD ANGLE
DATE:
22.03.04
RoHS
WAVESHARE ELECTRONICS

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User Manual
5
5. INPUT/OUTPUT PIN ASSIGNMENT
I = Input Pin, O = Output Pin, I/O = Bidirectional Pin (Input/output), P = Power Pin, C = Capacitor Pin.
NO.
Name
I/O
Description
Remark
1
NC
Do not connect with other NPC pins
Keep Open
2
GDR
O
N-Channel MOSFET Gate Drive Control
3
RESE
I
Current Sense Input for the Control Loop
4
NC
NC
Do not connect with other NC pins
Keep Open
5
VSH
C
Positive Source driving voltage
6
TSCL
O
I2C Interface to digital temperature sensor Clock pin
Note 5-6
7
TSDA
I/O
I2C Interface to digital temperature sensor Data pin
Note 5-6
8
BS1
I
Bus Interface selection pin
Note 5-5
9
BUSY
O
Busy state output pin
Note 5-4
10
RES#
I
Reset signal input, Active Low
Note 5-3
11
D/C#
I
Data/Command control pin
Note 5-2
12
CS#
I
Chip select output pin
Note 5-1
13
SCL
I
Serial Clock pin (SPI)
14
SDA
I/O
Serial Data pin (SPI)
15
VDDIO
P
Power supply for interface logic pins.
It should be connected with VCI.
16
VCI
P
Power supply for the chip
17
VSS
P
Ground
18
VDD
C
Core logic power pin VDD can be regulated internally from
VCI. A capacitor should be connected between VDD and VSS.
19
VPP
P
FOR TEST
Keep Open
20
VSH1
C
Positive Source driving voltage
21
VGH
C
Power Supply pin for Positive Gate driving voltage and VSH1
22
VSL
C
Negative Source driving voltage
23
VGL
C
Power Supply pin for Negative Gate driving voltage VCOM
and VSL
24
VCOM
C
VCOM driving voltage
Note 5-1: This pin (CS#) is the chip select input connecting to the MCU. The chip is enabled for MCU
communication only when CS# is pulled LOW.
Note 5-2: This pin is (D/C#) Data/Command control pin connecting to the MCU in 4-wire SPI mode.
When the pin is pulled HIGH, the data at SDA will be interpreted as data. When the pin is
pulled LOW, the data at SDA will be interpreted as command.

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Note 5-3: This pin (RES#) is reset signal input. The Reset is active low.
Note 5-4: This pin is Busy state output pin. When Busy is High, the operation of chip should not be
interrupted, command should not be sent. The chip would put Busy pin High when
-Outputting display waveform-Communicating with digital temperature sensor.
Note 5-5: Bus interface selection pin.
Note 5-6: The pin connects to the VSS if there is no external temperature sensor.
BS1 State
MCU Interface
L
4-lines serial peripheral interface(SPI) - 8 bits SPI
H
3- lines serial peripheral interface(SPI) - 9 bits SPI

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User Manual
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6. COMMAND TABLE
R/W#
D/C#
Hex
D7
D6
D5
D4
D3
D2
D1
D0
Command
Description
0
0
01
0
0
0
0
0
0
0
1
Driver Output
Control
Gate setting
Set A[9:0]=2A7h[POR]
680MUX
Set B[2:0]=000[POR]
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
0
0
0
0
0
A8
0
1
0
0
0
0
0
B2
B1
B0
0
0
03
0
0
0
0
0
0
1
1
Gate Driving
voltage
control
Set Gate Driving voltage
A[4:0] = 17h[POR], VGH
at 20V[POR]
VGH setting from 12V to
20V
0
1
0
0
0
A4
A3
A2
A1
A0
0
0
04
0
0
0
0
0
1
0
0
Source
Driving
voltage
control
Set Source Driving voltage
A[7:0] = 41h[POR], VSH1
at 15V
B[7:0]=A8h[POR], VSH2
at 5.0V
C[7:0]=32h[POR], VSL1 at
-15V
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
B7
B6
B5
B4
B3
B2
B1
B0
0
1
C7
C6
C5
C4
C3
C2
C1
C0
0
0
10
0
0
0
1
0
0
0
0
Deep Sleep
mode
Deep Sleep mode Control
A[1:0]:
Description
00
Normal Mode
[POR]
11
Enter Deep
Sleep Mode
After this command
initiated, the chip will enter
Deep Sleep Mode, BUSY
pad will keep output high.
0
1
0
0
0
0
0
0
A1
A0
0
0
11
0
0
0
1
0
0
0
1
Data Entry
mode setting
Define data entry
sequence
A[1:0]=ID[1:0] Address
automatic increment /
decrement setting
The setting of
incrementing or
decrementing of the
address counter can be
made independently in
each upper and lower bit
of the address.
0
1
0
0
0
0
0
A2
A1
A0

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00 –Y decrement, X
decrement,
01 –Y decrement, X
increment,
10 –Y increment, X
decrement,
11 –Y increment, X
increment [POR] A[2] =
AM
Set the direction in which
the address
counter is updated
automatically after data
are written to the RAM.
AM=0, the address
counter is updated in the X
direction. [POR]
AM=1, the address
counter is updated in the Y
direction.
0
0
12
0
0
0
1
0
0
1
0
SWRESET
It resets the commands
and parameters to their
S/W Reset default values
except R10h-Deep Sleep
Mode.
During operation, BUSY
pad will output high.
Note: RAM are affected by
this command.
0
0
18
0
0
0
1
1
0
0
0
Temperature
Sensor
Control
Temperature Sensor
Selection
A[7:0]=48h [POR],
external temperature
sensor
A[7:0]=80h [POR],
internal temperature
sensor
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
0
1A
0
0
0
1
1
0
1
0
Temperature
Sensor
Control
(Write to
temperature
Write to temperature
register.
A[11:0]=7FFh[POR]
0
1
A11
A10
A9
A8
A7
A6
A5
A4
0
1
A3
A2
A1
A0
0
0
0
0

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User Manual
9
register)
0
0
20
0
0
1
0
0
0
0
0
Master
Activation
Active Display Update
Sequence
The Display Update
Sequence Option is
located at R22h.
User should not interrupt
this operation to avoid
corruption of panel images
0
0
21
0
0
1
0
0
0
0
1
Display
Update
Control 1
RAM content option for
Display Update
A[7:0]=00H[POR]
A[7:4] Red RAM option
0000
Normal
0100
Bypass RAM
content as 0
1000
Inverse RAM
content
A[3:0] BW RAM option
0000
Normal
0100
Bypass RAM
content as 0
1000
Inverse RAM
content
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
0
22
0
0
1
0
0
0
1
0
Display
Update
Control 2
Display Update Sequence
Option:
Enable the stage or
Master Activation
Setting for LUT from
MCU
Enable Clock
Signal,
Then Enable
Analog
Then PATTERN
DISPLAY
Then Disable
Analog
Then Disable
OSC
C7
Setting for LUT from
1
A7
A6
A5
A4
A3
A2
A1
A0

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OTP according to
external Temperature
Sensor operation
Then Enable
Analog
Then Load LUT
90
Enable Analog
Then PATTERN
DISPLAY
Then Disable
Analog
Then Disable
OSC
47
0
0
24
0
0
1
0
0
1
0
0
Write RAM
(BW)
After this command, data
entries will be written into
the 1RAM until another
command is written.
Address pointers will
advance accordingly.
For Write pixel:
Content of write
RAM(BW)=1
For Black pixel:
Content of write
RAM(BW)=0
0
0
26
0
0
1
0
0
1
1
0
Write RAM
(RED)
After this command, data
entries will be written into
the 2 RAM until another
command is written.
Address pointers will
advance accordingly.
For RED pixel:
Content of write
RAM(RED)=1
For White/Black pixel:
Content of write
RAM(RED)=0
0
0
2C
0
0
1
0
1
1
0
0
Write VCOM
register
Set A[7:0]=50h
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
0
2D
0
0
1
0
1
1
0
1
OTP
Register
Read
Read Register stored in
OTP:
1. A[7:0]~B[7:0]: VCOM
1
1
A7
A6
A5
A4
A3
A2
A1
A0
1
1
B7
B6
B5
B4
B3
B2
B1
B0

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11
Information
2. C[7:0]~G[7:0]: Display
mode
3. H[7:0]~K[7:0]:
Waveform Version
[4bytes]
1
1
C7
C6
C5
C4
C3
C2
C1
C0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
1
1
E7
E6
E5
E4
E3
E2
E1
E0
1
1
F7
F6
F5
F4
F3
F2
F1
F0
1
1
G7
G6
G5
G4
G3
G2
G1
G0
1
1
H7
H6
H5
H4
H3
H2
H1
H0
1
1
I7
I6
I5
I4
I3
I2
I1
I0
1
1
J7
J6
J5
J4
J3
J2
J1
J0
1
1
K7
K6
K5
K4
K3
K2
K1
K0
0
0
2F
0
0
1
0
1
1
1
1
Status Bit
Read
Read IC status Bit [POR
0x21]
A[5]: HV relay detection
flag [POR=1]
0: Ready
1: Not ready
A[4]: VCI detection flag
[POR=0]
0: Normal
1: VCI lower than the
Detect level
A[3]: [POR=0]
0: Normal
1: BUSY
A[1:0]: Chip ID [POR=0]
Remark:
A[5] and A[4] status are
not valid after RESET,
they need to be initiated
by command 0x14 and
command 0x15
respectively.
1
1
0
0
A5
A4
A3
A2
A1
A0
0
0
32
0
0
1
1
0
0
1
0
Write LUT
register
Write LUT register from
MCU interface [105 bytes]
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
B7
B6
B5
B4
B3
B2
B1
B0
0
1
:
:
:
:
:
:
:
:
0
1
:
:
:
:
:
:
:
:
0
1
:
:
:
:
:
:
:
:
0
0
3A
0
0
1
1
1
0
1
0
Reserved
Reserved
0
0
3B
0
0
1
1
1
0
1
1
Reserved
Reserved
0
0
3C
0
0
1
1
1
1
0
0
Border
Waveform
Control
Select boarder waveform
for VBD
A[7:0]=C0h [POR], set
0
1
A7
A6
A5
A4
0
0
A1
A0

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12
VBD as HIZ
A[7:6] Select VBD option
A[7:6]
Select
VBD as
00
GS
Transition
Define
A[1:0]
01
Fix Level
Define
A[5:4]
10
VCOM
11[POR]
HIZ
A[5:4] Fix Level Setting for
VBD
A[5:4]
VBD
level
00[POR]
VSS
01
VSH1
10
VSL
11
VSH2
A[1:0] BW Transition
setting for VBD
A[1:0]
VBD
Transition
00[POR]
LUT0
01
LUT1
10
LUT2
11
LUT3
0
0
44
0
1
0
0
0
1
0
0
Set RAM
X-address
Start/End
position
Specify the start/end
positions of the window
address in the X direction
by an address unit
A[9:0]: XSA[9:0], X Start,
POR=000h
B[9:0]: XEA[9:0], X End,
POR=3BFh
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
-
-
-
-
-
-
A9
A8
0
1
B7
B6
B5
B4
B3
B2
B1
B0
0
1
-
-
-
-
-
-
B9
B8
0
0
45
0
1
0
0
0
1
0
1
Set RAM
Y-address
Start/End
position
Specify the start/end
positions of the window
address in the Y direction
by an address unit
A[9:0]: YSA[9:0], Y Start,
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
-
-
-
-
-
-
A9
A8
0
1
B7
B6
B5
B4
B3
B2
B1
B0
0
1
-
-
-
-
-
-
-
B8

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13
POR=000h
B[9:0]: YEA[9:0], Y End,
POR=2A7h
0
0
4E
0
1
0
0
1
1
1
0
Set RAM
X-address
counter
Make initial settings for the
RAM X address in the
address counter (AC)
A[9:0]: 000h[POR]
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
-
-
-
-
-
-
A9
A8
0
0
4F
0
1
0
0
1
1
1
1
Set RAM
Y-address
counter
Make initial settings for the
RAM Y address in the
address counter (AC)
A[9:0]: 000h[POR]
0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
1
-
-
-
-
-
-
A9
A8
0
1
A7
A6
A5
A4
A3
A2
A1
A0

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14
7. ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATING
Parameter
Symbol
Rating
Unit
Logic supply voltage
VCI
-0.3 to +6.0
V
Logic Input voltage
VIN
-0.3 to VCI +0.3
V
Operating Temp range
TOPR
0 to +50
ºC
Storage Temp range
TSTG
-25 to+70
ºC
Optimal Storage Temp
TSTGo
23±3
ºC
Optimal Storage Humidity
HSTGo
55±10
%RH
Note: Maximum ratings are those values beyond which damages to the device may occur. Functional
operation should be restricted to the limits in the Panel DC Characteristics tables.

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15
7.2 PANEL DC CHARACTERISTICS
The following specifications apply for: VSS=0V, VCI=3.0V, TOPR =23ºC.
Parameter
Symbol
Condition
Applicable
pin
Min.
Typ.
Max.
Unit
Single ground
VSS
-
-
0
-
V
Logic supply
voltage
VCI
-
VCI
2.2
3.0
3.3
V
Core logic voltage
VDD
VDD
1.7
1.8
1.9
V
High level input
voltage
VIH
-
-
0.8VCI
-
-
V
Low level input
voltage
VIL
-
-
-
-
0.2VCI
V
High level output
voltage
VOH
IOH = - 100uA
-
0.9VCI
-
-
V
Low level output
voltage
VOL
IOL = 100uA
-
-
-
0.1VCI
V
Typical power
PTYP
VCI =3.0V
-
-
66
-
mW
Deep sleep mode
PSTPY
VCI =3.0V
-
-
0.009
-
mW
Typical operating
current
Iopr_VCI
VCI =3.0V
-
-
22
-
mA
Image update time
-
23 ºC
-
-
4
-
sec
Typical peak
current
Iopr_VCI
2.2~3.7v
100
160
mA
Sleep mode current
Islp_VCI
DC/DC off, No clock
No input load Ram data
retain
-
-
20
-
uA
Deep sleep mode
current
Idslp_VCI
DC/DC off, No clock
No input load Ram data
not retain
-
-
3
5
uA
Notes: 1. The typical power is measured with following transition from horizontal 2 scale pattern to
vertical.

13.3inch e-Paper (K)
User Manual
16
2. The deep sleep power is the consumed power when the panel controller is in deep sleep mode.
3. The listed electrical characteristics are only guaranteed under the controller & waveform
provided by Waveshare.
4. Electrical measurement: Tektronix oscilloscope - MDO3024, Tektronix current probe –TCP0030A.
7.3 PANEL DC CHARACTERISTICS (DRIVER IC INTERNAL REGULATORS)
The following specifications apply for: VSS=0V, VCI=3.0V, TOPR=23ºC.
Parameter
Symbol
Condition
Applicable
pin
Min.
Typ.
Max.
Unit
VCOM output voltage
VCOM
-
VCOM
-
TBD
-
V
Positive Source output
voltage
VSH
-
S0~S959
+14.8
+15
+15.2
V
Negative Source output
voltage
VSL
-
S0~S959
-15.2
-15
-14.8
V
Positive gate output
voltage
Vgh
-
G0~G679
+19.5
+20
+20.5
V
Negative gate output
voltage
Vgl
-
G0~G679
-20.5
-20
-19.5
V