WDC 65 Series User manual

November 09, 2018
W65C816S
8/16–bit Microprocessor
WDC reserves the right to make changes at any time without notice in order to improve design and supply
the best possible product. Information contained herein is provided gratuitously and without liability, to any
user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee
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Sales and Sales Policies, copies of which are available upon request.
Copyright (C) 1981-2018 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction in whole or in part in anyform.

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TABLE OF CONTENTS
1INTRODUCTION......................................................................................................5
1.1 Features of the W65C816S.........................................................................................................5
2W65C816S FUNCTIONAL DESCRIPTION.............................................................6
2.1 Instruction Register (IR) .............................................................................................................6
2.2 Timing Control Unit (TCU)..........................................................................................................6
2.3 Arithmetic and Logic Unit (ALU)................................................................................................6
2.4 Accumulator (A) ..........................................................................................................................6
2.5 Data Bank Register (DBR)..........................................................................................................6
2.6 Direct (D) ......................................................................................................................................7
2.7 Index (X and Y) ............................................................................................................................7
2.8 Processor Status Register (P) ...................................................................................................7
2.9 Program Bank Register (PBR) ...................................................................................................7
2.10 Program Counter (PC) ................................................................................................................7
2.11 Stack Pointer (S) .........................................................................................................................7
2.12 Pin Function Description..........................................................................................................10
2.13 Abort (ABORTB)........................................................................................................................12
2.14 Address Bus (A0-A15) ..............................................................................................................12
2.15 Bus Enable (BE) ........................................................................................................................12
2.16 Data/Bank Address Bus (D0-D7) .............................................................................................13
2.17 Emulation Status (E).................................................................................................................13
2.18 Interrupt Request (IRQB)..........................................................................................................13
2.19 Memory Lock (MLB)..................................................................................................................13
2.20 Memory/Index Select Status (MX) ...........................................................................................13
2.21 Non-Maskable Interrupt (NMIB) ...............................................................................................14
2.22 Phase 2 In (PHI2).......................................................................................................................14
2.23 Read/Write (RWB) .....................................................................................................................14
2.24 Ready (RDY)...............................................................................................................................14
2.25 Reset (RESB).............................................................................................................................15
2.26 Valid Data Address (VDA) and Valid Program Address (VPA).............................................15
2.27 VDD and VSS.............................................................................................................................15
2.28 Vector Pull (VPB).......................................................................................................................15
3ADDRESSING MODES.........................................................................................16
3.1 Reset and Interrupt Vectors.....................................................................................................16
3.2 Stack...........................................................................................................................................16
3.3 Direct ..........................................................................................................................................16
3.4 Program Address Space ..........................................................................................................16
3.5 Data Address Space .................................................................................................................16
3.5.1 Absolute-a .................................................................................................................................17
3.5.2 Absolute Indexed Indirect-(a,x) .................................................................................................17
3.5.3 Absolute Indexed with X-a,x......................................................................................................17
3.5.4 Absolute Indexed with Y-a,y......................................................................................................17
3.5.5 Absolute Indirect-(a)..................................................................................................................18
3.5.6 Absolute Long Indexed With X-al,x...........................................................................................18
3.5.7 Absolute Long-al........................................................................................................................18
3.5.8 Accumulator-A...........................................................................................................................18
3.5.9 Block Move-xyc .........................................................................................................................19
3.5.10 Direct Indexed Indirect-(d,x)....................................................................................................19
3.5.11 Direct Indexed with X-d,x ........................................................................................................20
3.5.12 Direct Indexed with Y-d,y ........................................................................................................20

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3.5.13 Direct Indirect Indexed-(d),y....................................................................................................20
3.5.14 Direct Indirect Long Indexed-[d],y ...........................................................................................21
3.5.15 Direct Indirect Long-[d]............................................................................................................21
3.5.16 Direct Indirect-(d).....................................................................................................................21
3.5.17 Direct-d....................................................................................................................................22
3.5.18 Immediate-#.............................................................................................................................22
3.5.19 Implied-i...................................................................................................................................22
3.5.20 Program Counter Relative Long-rl...........................................................................................22
3.5.21 Program Counter Relative-r ....................................................................................................22
3.5.22 Stack-s.....................................................................................................................................22
3.5.23 Stack Relative-d,s....................................................................................................................23
3.5.24 Stack Relative Indirect Indexed-(d,s),y....................................................................................23
4TIMING, AC AND DC CHARACTERISTICS .........................................................25
4.1 Absolute Maximum Ratings.....................................................................................................25
4.2 DC Characteristics TA = -40°C to +85°C................................................................................25
5OPERATION TABLES...........................................................................................29
6RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS.................45
6.1 Directives...................................................................................................................................45
6.2 Comments..................................................................................................................................45
6.3 The Source Line ........................................................................................................................45
6.3.1 The Label Field....................................................................................................................45
6.3.2 The Operation Code Field...................................................................................................45
6.3.3 The Operand Field ..............................................................................................................46
6.3.4 Comment Field....................................................................................................................48
7Caveats .................................................................................................................49
7.1 Stack Addressing......................................................................................................................50
7.2 Direct Addressing .....................................................................................................................50
7.3 Absolute Indexed Addressing .................................................................................................50
7.4 ABORTB Input...........................................................................................................................50
7.5 VDA and VPA Valid Memory Address Output Signals..........................................................50
7.6 DB/BA operation when RDY is Pulled Low ............................................................................51
7.7 MX Output..................................................................................................................................51
7.8 All Opcodes Function in All Modes of Operation ..................................................................51
7.9 Indirect Jumps...........................................................................................................................51
7.10 Switching Modes.......................................................................................................................51
7.11 How Interrupts Affect the Program Bank and the Data Bank Registers .............................51
7.12 Binary Mode...............................................................................................................................52
7.13 Wait for Interrupt (WAI) Instruction..........................................................................................52
7.14 Stop-the-Clock (STP) Instruction.............................................................................................52
7.15 Co-Processor (COP) Signatures ..............................................................................................52
7.16 WDM Opcode Use .....................................................................................................................52
7.17 RDY Pulled During Write ..........................................................................................................52
7.18 MVN and MVP Affects on the Data Bank Register.................................................................52
7.19 Interrupt Priorities.....................................................................................................................53
7.20 Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers...................................................53
7.21 Stack Transfers .........................................................................................................................53
7.22 BRK Instruction.........................................................................................................................53
7.23 Accumulator switching from 8-bit to 16-bit............................................................................53
8HARD CORE MODEL ...........................................................................................54
8.1 W65C816 Core Information ......................................................................................................54
9SOFT CORE RTL MODEL ....................................................................................54

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9.1 W65C816 Synthesizable RTL-Code in Verilog HDL...............................................................54
10 ORDERING INFORMATION...............................................................................55
Table of Tables
Table 2-1 W65C816S Microprocessor Programming Model ...............................................................................................9
Table 2-2 Pin Function Table .........................................................................................................................................12
Table 3-1 Addressing Mode Summary..........................................................................................................................24
Table 4-1 Absolute Maximum Ratings ..........................................................................................................................25
Table 4-2 W65C816S AC Characteristics......................................................................................................................27
Table 5-1 W65C816S Instruction Set-Alphabetical Sequence.........................................................................................29
Table 5-2 Emulation Mode Vector Locations (8-bit Mode) ...............................................................................................30
Table 5-3 Native Mode Vector Locations (16-bit Mode) ...................................................................................................30
Table 5-4 Opcode Matrix...................................................................................................................................................31
Table 5-5 Operation, Operation Codes, and Status Register............................................................................................32
Table 6-1 Alternate Mnemonics.........................................................................................................................................46
Table 6-2 Address Mode Formats ....................................................................................................................................47
Table 6-3 Byte Selection Operator ................................................................................................................................48
Table 7-1 Caveats............................................................................................................................................................49
Table of Figures
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram..............................................................................8
Figure 2-2 W65C816S 40 Pin DIP Pinout.........................................................................................................................10
Figure 2-3 W65C816S 44 Pin PLCC Pinout.....................................................................................................................10
Figure 2-4 W65C816S 44 PIN QFP Pinout.......................................................................................................................11
Figure 4-1 General Timing Diagram .................................................................................................................................28
Figure 5-1 Bank Address Latching Circuit......................................................................................................................44

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1 INTRODUCTION
The W65C816S is a low power cost sensitive 8/16-bit microprocessor. The variable length instruction set
and manually optimized core size makes the W65C816S an excellent choice for low power System-on-Chip
(SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor
Company, provides packaged chips for evaluation or volume production. To aid in system development,
WDC provides a Professional Software Development Kit (ProSDK) that is available for free download on a
trial basis, see www.westerndesigncenter.com for more information.
The WDC W65C816S is a fully static CMOS 16-bit microprocessor featuring software compatibility* with the
8-bit NMOS and CMOS 6500-series predecessors. The W65C816S extends addressing to a full 16
megabytes. These devices offer the many advantages of CMOS technology, including increased noise
immunity, higher reliability, and greatly reduced power requirements. A software switch determines whether
the processor is in the 8-bit "emulation" mode, or in the native mode, thus allowing existing systems to use
the expanded features.
As shown in the W65C816S Processor Programming Model, Table 2-1, the Accumulator, ALU, X and Y
Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page
register augments the Direct Page addressing mode (formerly Zero Page addressing). Separate Program
Bank and Data Bank registers provide 24-bit memoryaddressing with segmented or linear addressing.
Four new signals provide the system designer with many options. The ABORTB input can interrupt the
currently executing instruction without modifying internal register, thus allowing virtual memory system
design. Valid Data Address (VDA) and Valid Program Address (VPA) outputs facilitate dual cache memory
by indicating whether a data segment or program segment is accessed. Modifying a vector is made easy by
monitoring the Vector Pull (VPB) output.
1.1 Features of the W65C816S
Advanced fully static CMOS design for low power
consumption and increased noise immunity
Wide operating voltage range, 1.8+/- 5%, 2.5+/-
5%, 3.0+/- 5%, 3.3+/- 10%, 5.0+/- 5% specified for
use with advanced low voltage peripherals
Emulation mode allows complete hardware and
software compatibility with 65xx designs
24-bit address bus provides access to 16 MBytes
of memory space
Full 16-bit ALU, Accumulator, Stack Pointer and
Index Registers
Valid Data Address (VDA) and Valid Program
Address (VPA) output for dual cache and cycle steal
DMA implementation
Vector Pull (VPB) output indicates when interrupt
vectors are being addressed
Abort (ABORTB) input and associated vector
supports processor repairs of bus error conditions
Low power consumption (300uA@1MHz)
Separate program and data bank registers allow
program segmentation or full 16 MByte linear
addressing
New Direct Register and stack relative addressing
provides capability for re-entrant, re-cursive and re-
locatable programming
24 addressing modes - 13 original W65C02S
modes with 92 instructions using 256 opcodes
Wait for Interrupt (WAI) and Stop-the-Clock (STP)
instructions further reduce power consumption,
decrease interrupt latency and allows synchronization
with external events
Co-Processor (COP) instruction with associated
vector supports co-processor configurations, i.e.,
floating point processors
Block move ability
*Except for the BBRx, BBSx, RMBx, and SMBx bit manipulation instructions which do not exist for the
W65C816S

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2 W65C816S FUNCTIONAL DESCRIPTION
The W65C816S provides the design engineer with upward software compatibility from 8-bit W65C02S in
applications to 16-bit system application. In Emulation mode, the W65C816S offers many advantages,
including full software compatibility withW65C02S coding.
Internal organization of the W65C816S can be divided into two parts: 1) The Register Section and 2) The
Control Section. Instructions obtained from program memory are executed by implementing a series of data
transfers within the Register Section. Signals that cause data transfers to be executed are generated within
the Control Section. The W65C816S has a 16-bit internal bus architecture with an 8-bit external data bus
and 24-bit external address bus.
2.1 Instruction Register (IR)
An Operation Code enters the processor on the Data Bus, and is latched into the IR during the opcode fetch
cycle. This opcode is then decoded, along with timing and interrupt signals, to generate various IR control
signals for use during instruction operations.
2.2 Timing Control Unit (TCU)
The Timing Control Unit keeps track of each instruction cycle as it is executed. The TCU is set to zero each
time an instruction fetch is executed, and is advanced at the beginning of each cycle for as many cycles as
is required to complete the instruction. Each data transfer between registers depends upon decoding the
contents of both the Instruction Register and the Timing Control Unit.
2.3 Arithmetic and Logic Unit (ALU)
All Arithmetic and Logic Unit operations take place within the 16-bit ALU. In addition to data operations, the
ALU also calculates the effective address for relative and indexed addressing modes. The result of a data
operation is stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags may
be updated following the ALU data operation.
2.4 Accumulator (A)
The Accumulator is a general purpose register which contains one of the operands and the result of most
arithmetic and logical operations. In the Native mode (E=0), when the Accumulator Select Bit (M) equals
zero, the Accumulator is established as 16 bits wide (A, B=C). When the Accumulator Select Bit (M) equals
one, the Accumulator is 8 bits wide (A). In this case, the upper 8 bits (B) may be used for temporary storage
in conjunction with the Exchange Accumulator (XBA) instruction.
2.5 Data Bank Register (DBR)
During modes of operation, the 8-bit Data Bank Register holds the bank address for memory transfers. The
24-bit address is composed of the 16-bit instruction effective address and the 8-bit Data Bank address. The
register value is multiplexed with the data value and is present on the Data/Address lines during the first half
of a data transfer memory cycle for the W65C816S. The DBR is initialized to zero during Reset.

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2.6 Direct (D)
The 16-bit Direct Register provides an address offset for all instructions using direct addressing. The
effective Direct Address is formed by adding the 8-bit instruction Direct Address field to the Direct Register.
The Direct Register is initialized to zero during Reset. The bank address for Direct Addressing is always
zero
2.7 Index (X and Y)
There are two general purpose registers that are commonly referred to as Index Registers (X and Y) and
are frequently used as an index value for calculation of the effective address. When executing an
instruction with indexed addressing, the microprocessor fetches the opcode and the base address, and then
modifies the address by adding an Index Register contents to the address prior to performing the desired
operation. Pre-indexing or post-indexing of indirect addresses may be selected. In the Native mode (E=0),
both Index Registers are 16 bits wide where the Index Select Bit (X) of the Processor Status (P) register
equals zero. If the Index Select Bit (X) equals one, both registers will be 8 bits wide, and the high byte is
forced to zero.
2.8 Processor Status Register (P)
The 8-bit Processor Status Register contains status flags and mode select bits. The Carry (C), Negative
(N), Overflow (V), and Zero (Z) status flags serve to report the status of most ALU operations. These status
flags are tested by use of Conditional Branch instructions. The Decimal (D), IRQ Disable (I),
Memory/Accumulator (M), and Index (X) bits are used as mode select flags. These flags are set by the
program to change microprocessor operations.
The Emulation (E) select and the Break (B) flags are accessible only through the Processor Status Register.
The Emulation mode select flag is selected by the Exchange Carry and Emulation Bits (XCE) instruction.
Table 8-1, W65C816S Compatibility Information, illustrates the features of the Native (E=0) and Emulation
(E=1) modes. The M and X flags are always equal to one in Emulation mode. When an interrupt occurs
during Emulation mode, the Break flag is written to stack memory as bit 4 of the Processor Status Register.
2.9 Program Bank Register (PBR)
The 8-bit Program Bank Register holds the bank address for all instruction fetches. The 24-bit address
consists of the 16-bit instruction effective address and the 8-bit Program Bank address. The register value
is multiplexed with the data bus and presented on the Data bus lines during the first half of a program
memory cycle. The Program Bank Register is initialized to zero during Reset. The PHK instruction pushes
the PBR register onto the Stack.
2.10 Program Counter (PC)
The 16-bit Program Counter Register provides the addresses which are used to step the microprocessor
through sequential 8-bit program instruction fields. The PC is incremented for each 8-bit instruction field that
is fetched from program memory.
2.11 Stack Pointer (S)
The Stack Pointer is a 16-bit register which is used to indicate the next available location in the stack
memory area. It serves as the effective address in stack addressing modes as well as subroutine and
interrupt processing. The Stack Pointer provides simple implementation of nested subroutines and multiple-
level interrupts. During Emulation mode, the S High-order byte (SH) is always equal to one. The bank
address for all stack operations is Bank zero.

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INTERUPT
LOGIC VDD
VSS
ABORTB
IRQB
NMIB
RESB
TIMING
CONT. RDY
CLOCK
GEN-
ERATOR PHI2
INSTRUCTION DECODE
MINTERMS
INSTRUCTION DECODE SUM OF
MINTERMS
REGISTER TRANSFER LOGIC
STSTEM CONTROL
RWB
VPA
VDA
MLB
VPB
E
MX
PROCESSOR
STATUS (P)
(8 BITS)
INSTRUCTION REGISTER
(8 BITS)
INTERNAL DATA BUS (16 BITS)
DATA
LATCH/
PREDECODER
INTERNAL SPECIAL BUS (16 BITS)
DATA BANK (DBR)
(8 BITS)
PROG. BANK (PBR)
(8 BITS)
DIRECT (D)
(16 BITS)
PROG. COUNTER
(PC) (16 BITS)
ACCUMULATOR
(C) (16 BITS)
(A) (8 BITS)
(B) (8 BITS)
TRANSFER
SWITCHES
ALU
(16 BITS)
STACK POINTER
(S) (16 BITS)
INDEX Y
(16 BITS)
INDEX X
(16 BITS)
ADDRESS BUFFER (LOW)
ADRESS BUFFER (HIGH)
DATA BUS/BANK ADDRESS BUFFER
INTERNAL ADDRESS BUS (16 BITS)
A0-A7
A8-A15
D0-D7
BE
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram

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Table 2-1 W65C816S Microprocessor Programming Model
8 Bits 8 Bits 8 Bits
X Register (XL)
Y Register (YL)
Stack Register (SL)
Accumulator (A)
Counter (PCL)
X Register (XH)
Stack Register (SH)
Y Register (YH)
Accumulator (B)
Program (PCH)
Direct Register (DH) Direct Register (DL)
Data Bank Register (DBR)
Data Bank Register (DBR)
00
Program Bank Register (PBR)
00
Shaded Blocks = 6502 registers
N V M X D I Z C
1 B E
BRK Bit 1=BRK 0=IRQ
Carry 1=true
Zero 1=result zero
IRQ disable 1=disable
Decimal mode 1=true
Index Register Select 1=8-bit, 0=16-bit
Memory Select 1=8-bit, 0=16-bit
Overflow 1=true
Negative 1=negative
Emulation
1=W65C02 Emulation Mode
0=Native Mode

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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VPB
RDY
ABORT
IRQB
MLB
NMIB
VPA
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RESB
VDA
MX
PHI2
BE
E
RWB
D0
D1
D2
D3
D4
D5
D6
D7
A15
A14
A13
A12
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
W65C816S
2.12 Pin Function Description
Figure 2-2 W65C816S 40 Pin DIP Pinout
Figure 2-3 W65C816S 44 Pin PLCC Pinout
W65C816S
6 5 4 3 2 1
44 43 42 41 40
18 19
20 21 22 23 24 25 26 27
28
NMIB
VPA
VDD
A0
A1
NC
A2
A3
A4
A5
A6
MLB IRQB ABORTB RDY VPB VSS RESB VDA MX PHI2 BE
E
RWB
VDD
D0
D1
D2
D3
D4
D5
D6
D7
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
A7 A8 A9
A10 A11
VSS VSS
A12 A13 A14 A15

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W65C816S
44 43 42 41 40 39 38 37 36 35 34
12
13
14
15
16
17
18
19
20
21
22
NMIB
VPA
VDD
A0
A1
NC
A2
A3
A4
A5
A6
MLB IRQB ABORTB RDY VPB VSS RESB VDA MX PHI2 BE
E
RWB
VDD
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
A7 A8 A9
A10 A11
VSS VSS
A12 A13 A14 A15
Figure 2-4 W65C816S 44 PIN QFP Pinout

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Table 2-2 Pin Function Table
Pin
Description
A0-A15
Address Bus
ABORTB
Abort Input
BE
Bus Enable
PHI2
Phase 2 In Clock
D0-D7
Data Bus/Bank Address Bus
E
Emulation OR Native Mode Select
IRQB
Interrupt Request
MLB
Memory Lock
MX
Memory and Index Register Mode Select
NC
No Connect
NMIB
Non-Maskable Interrupt
RDY
Ready
RESB
Reset
RWB
Read/Write
VDA
Valid Data Address
VPB
Vector Pull
VPA
Valid Program Address
VDD
Positive Power Supply
VSS
Internal Logic Ground
2.13 Abort (ABORTB)
The Abort negative pulse active input is used to abort instructions (usually due to an Address Bus
condition). A negative transition will inhibit modification of any internal register during the current
instruction. Upon completion of this instruction, an interrupt sequence is initiated. The location of the
aborted opcode is stored as the return address in stack memory. The Abort vector address is 00FFF8,9
(Emulation mode) or 00FFE8,9 (Native mode). Note that ABORTB is a pulse sensitive signal; i.e., an
abort will occur whenever there is a negative pulse (or level) on the ABORTB pin during a PHI2 clock.
2.14 Address Bus (A0-A15)
The sixteen Address Bus output lines along with the bank address (multiplexed on the first half cycle of the
Data Bus (D0-D7) pins) form the 24-bit Address Bus for memory and I/O exchange on the Data Bus. When
using the W65C816S, the address lines may be set to the high impedance state by the Bus Enable (BE)
signal.
2.15 Bus Enable (BE)
The Bus Enable input signal allows external control of the Address and Data Buffers, as well as the RWB
signal. With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are
active during the first half of every cycle and the second half of a write cycle. When BE is low, these buffers
are disabled. Bus Enable is an asynchronous signal.

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2.16 Data/Bank Address Bus (D0-D7)
The Data/Bank Address Bus pins provide both the Bank Address and Data. The bank address is present
during the first half of a memory cycle, and the data value is read or written during the second half of the
memory cycle. Two memory cycles are required to transfer 16-bit values. These lines may be set to the
high impedance state by the Bus Enable (BE) signal.
2.17 Emulation Status (E)
The Emulation Status output reflects the state of the Emulation (E) mode flag in the Processor Status (P)
Register. This signal may be thought of as an opcode extension and used for memory and system
management.
2.18 Interrupt Request (IRQB)
The Interrupt Request negative level active input signal is used to request that an interrupt sequence be
initiated. When the IRQB Disable flag is cleared, a low input logic level initiates an interrupt sequence after
the current instruction is completed. The Wait for Interrupt (WAI) instruction may be executed to ensure the
interrupt will be recognized immediately. The Interrupt Request vector address is 00FFFE, F (Emulation
mode) or 00FFEE,F (Native mode). Since IRQB is a level sensitive input, an interrupt will occur if the
interrupt source was not cleared since the last interrupt. Also, no interrupt will occur if the interrupt source is
cleared prior to interrupt recognition. The IRQB signal going low causes 4 bytes of information to be pushed
onto the stack before jumping to the interrupt handler. The first byte is PBR followed by PCH, PCL and P
(Processor Status Register). These register values are used by the RTI instruction to return the processor
to its original state prior to handling the IRQ interrupt (see Table 6-1)
2.19 Memory Lock (MLB)
The Memory Lock active low output may be used to ensure the integrity of Read Modify Write instructions in
a multiprocessor system. Memory Lock indicates the need to defer arbitration of the next bus cycle.
Memory Lock is low during the last three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB
memoryreferencing instructions, depending on the state of the M flag.
2.20 Memory/Index Select Status (MX)
The Memory/Index Select Status multiplexed output reflects the state of the Accumulator (M) and Index (X)
elect flags (bits 5 and 4 of the Processor Status (P) Register. Flag M is valid during PHI2 negative transition
and Flag X is valid during PHI2 positive transition. These bits may be thought of as opcode extensions and
may be used for memory and system management.

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2.21 Non-Maskable Interrupt (NMIB)
A negative transition on the non-maskable Interrupt input initiates an interrupt sequence. A high to low
transition initiates an interrupt sequence after the current instruction is completed. The Wait for Interrupt
instruction may be executed to ensure that the interrupt will be recognized immediately. The non-maskable
Interrupt vector address is 00FFFA, B (Emulation mode) or 00FFEA, B (Native mode). Since NMIB is an
edge sensitive input, an interrupt will occur if there is a negative transition while servicing a previous
interrupt. No interrupt will occur if NMIB remains low after the negative transition was processed. The
NMIB signal going low causes 4 bytes of information to be pushed onto the stack before jumping to the
interrupt handler. The first byte on the stack is the PBR followed by the PCH, PCL and P, these register
values are used by the RTI instruction to return the processor to its original state prior to the NMI interrupt.
2.22 Phase 2 In (PHI2)
Phase 2 In is the system clock input to the microprocessor. PHI2 can be held in either state to preserve the
contents of internal registers and reduce power as a Standby mode.
2.23 Read/Write (RWB)
The Read/Write output signal is used to control whether the microprocessor is "Reading" or "Writing" to
memory. When the RWB is in the high state, the microprocessor is reading data from memory or I/O.
When RBW is low the Data Bus contains valid data from the microprocessor which is to written to the
addressed memory location. The RWB signal is set to the high impedance state when Bus Enable is low.
2.24 Ready (RDY)
The Ready is a bi-directional signal. When it is an output it indicates that a Wait for Interrupt instruction has
been executed halting operation of the microprocessor. A low input logic level will halt the microprocessor
in its current state. Returning RDY to the active high state releases the microprocessor to continue
processing following the next PHI2 negative transition. The RDY signal is internally pulled low following the
execution of a Wait for Interrupt instruction, and then returned to the high state when a RESB, ABORTB,
NMIB, or IRQB external interrupt is active. This feature may be used to reduce interrupt latency by
executing the WAI instruction and waiting for an interrupt to begin processing. If the IRQB Disable flag has
been set, the next instruction will be executed when the IRQB occurs. The processor will not stop after a
WAI instruction if RDY has been forced to a high state. The STP instruction has no effect on RDY. The
RDY pin has an active pull-up and when outputting a low level, the pull-up is turned off to reduce power.
The RDY pin can be wired ORed.

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2.25 Reset (RESB)
The Reset active low input is used to initialize the microprocessor and start program execution. The Reset
input buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pull-up
device. The RESB signal must be held low for at least two clock cycles after VDD reaches operating
voltage. Ready (RDY) has no effect while RESB is being held low. The stack pointer must be initialized by
the user's software. During the Reset conditioning period the following processor initialization takes place:
SH=01, SL=D=0000Registers
XH=00, XL=DBR=00 YH=00, YL=PBR=00 A=
VDA=0E=1 Signals
VPB=1MX=1 VPA=0RWB=1
1 1 0 1 1
N V M X D I Z C/E
Shaded Area = Not Initialized
N V M X D I Z C/E
P Register
When Reset is brought high, an interrupt sequence is initiated
STP and WAI instructions are cleared
RWB remains in the high state during the stack address cycles.
The Reset vector address is 00FFFC,D.(see Table 6-1 for Vectors)
PC is loaded with the contents of 00FFFC,D
2.26 Valid Data Address (VDA) and Valid Program Address (VPA)
The Valid Data Address and Valid Program Address output signals indicate valid memory addresses when
high and are used for memory or I/O address qualification.
VDA VPA
0 0
0 1
1 0
1 1
Internal Operation Address and Data Bus available. The Address Bus may be invalid.
Valid program address-may be used for program cache control.
Valid data address-may be used for data cache control.
Opcode fetch-may be used for program cache control and single step control.
2.27 VDD and VSS
VDD is the positive supply voltage and VSS is system logic ground.
2.28 Vector Pull (VPB)
The Vector Pull active low output indicates that a vector location is being addressed during an interrupt
sequence. VPB is low during the last two interrupt sequence cycles, during which time the processor loads
the PC with the interrupt handler vector location. The VPB signal may be used to select and prioritize
interrupts from several sources by modifying the vector addresses.

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3 ADDRESSING MODES
The W65C816S is capable of directly addressing 16 MBytes of memory. This address space has special
significance within certain addressing modes, as follows:
3.1 Reset and Interrupt Vectors
The Reset and Interrupt Vectors use the majority of the fixed addresses between 00FFE0 and 00FFFF.
3.2 Stack
The Stack may be use memory from 000000 to 00FFFF. The effective address of Stack and Stack Relative
addressing modes will be always be within this range.
3.3 Direct
The Direct addressing modes are usually used to store memory registers and pointers. The effective
address generated by Direct, Direct,X and Direct,Y addressing modes is always in Bank 0 (000000-
00FFFF).
3.4 Program Address Space
The Program Bank register is not affected by the Relative, Relative Long, Absolute, Absolute Indirect, and
Absolute Indexed Indirect addressing modes or by incrementing the Program Counter from FFFF. The only
instructions that affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute Long.
Program code may exceed 64K bytes although code segments may not span bank boundaries.
3.5 Data Address Space
The Data Address space is contiguous throughout the 16 MByte address space. Words, arrays, records, or
any data structures may span 64 KByte bank boundaries with no compromise in code efficiency. The
following addressing modes generate 24-bit effective addresses:
Absolute a
Absolute a,x
Absolute a,y
Absolute Long al
Absolute Long Indexed al,x
Direct Indexed Indirect (d,x)
Direct Indirect (d)
Direct Indirect Indexed (d),y
Direct Indirect Long [d]
Direct Indirect Long Indexed [d],y
Stack Relative Indirect Indexed (d,x),y
The following addressing mode descriptions provide additional detail as to how effective addresses are
calculated. Twenty-four addressing modes are available for the W65C816S.

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3.5.1 Absolute-a
With Absolute addressing the second and third bytes of the instruction form the low order 16 bits of the
effective address. The Data Bank Register contains the high order 8 bits of the operand address.
Opcode
DBR
addrl
addrh
addrh
addrl
Instruction
Operand
3.5.2 Absolute Indexed Indirect-(a,x)
With Absolute Indexed Indirect ((a,x)) addressing the second and third bytes of the instruction are
added to the X Index Register to form a 16-bit pointer in Bank 0. The contents of this pointer are loaded
in the Program Counter for the JMP instruction. The Program Bank Register is not changed.
Instruction:
Opcode
addrl
addrh
addrh
addrl
X Reg
PBR
address
then:
PC = (address)
3.5.3 Absolute Indexed with X-a,x
With Absolute Indexed with X (a,x) addressing the second and third bytes of the instruction are added
to the X Index Register to form the low order 16 bits of the effective address. The Data Bank Register
contains the high order 8 bits of the effective address.
Instruction:
Opcode
addrl
addrh
DBR
addrh
addrl
+
X Reg
Operand
Address:
effective address
3.5.4 Absolute Indexed with Y-a,y
With Absolute Indexed with Y (a,y) addressing the second and third bytes of the instruction are added
to the Y Index Register to form the low order 16 bits of the effective address. The Data Bank Register
contains the high order 8 bits of the effective address.
Instruction:
Opcode
addrl
addrh
DBR
addrh
addrl
+
Y Reg
Operand
Address:
effective address

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3.5.5 Absolute Indirect-(a)
With Absolute Indirect addressing the second and third bytes of the instruction form an address to a
pointer in Bank 0. The Program Counter is loaded with the first and second bytes at this pointer. With
the Jump Long (JML) instruction, the Program Bank Register is loaded with the third byte of the pointer.
Instruction:
Opcode
addrl
addrh
Indirect
00
addrh
addrl
3.5.6 Absolute Long Indexed With X-al,x
With Absolute Long Indexed with X (al,x) addressing the second, third and fourth bytes of the instruction
form a 24-bit base address. The effective address is the sum of this 24-bit address and the X Index
Register.
Instruction:
Opcode
addrl
addrh
baddr
baddr
addrh
addrl
+
X Reg
Operand
Address:
effective address
3.5.7 Absolute Long-al
With Absolute Long (al) addressing the second, third and fourth byte of the instruction form the 24-bit
effective address.
Instruction:
Opcode
addrl
addrh
baddr
Operand
Address:
baddr
addrh
addrl
3.5.8 Accumulator-A
With Accumulator (A) addressing the operand is the Accumulator.

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3.5.9 Block Move-xyc
Block Move (xyc) addressing is used by the Block Move instructions. The second byte of the instruction
contains the high-order 8 bits of the destination address and the Y Index Register contains the low-
order 16 bits of the destination address. The third byte of the instruction contains the high-order 8 bits
of the source address and the X Index Register contains the low-order bits of the source address. The
C Accumulator contains one less than the number of bytes to move. The second byte of the block
move instructions is also loaded into the Data Bank Register.
Instruction:
Opcode
dstbnk
srcbnk
Source Address:
srcbnk
X Reg
Dest. Address:
dstbnk
Y Reg
Increment X and Y (MVN) or decrement X and Y (MVP) and decrement C (if greater than zero), then
PC=PC+3.
3.5.10 Direct Indexed Indirect-(d,x)
Direct Indexed Indirect ((d,x)) addressing is often referred to as Indirect X addressing. The second byte
of the instruction is added to the sum of the Direct Register and the X Index Register. The result points
to the X low-order 16 bits of the effective address. The Data Bank Register contains the high-order 8
bits of the effective address.
Instruction:
Opcode
offset
Direct Register
+
offset
direct address
+
X Reg
00
(address)
then: +
DBR
Operand Address:
effective address

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3.5.11 Direct Indexed with X-d,x
With Direct Indexed with X (d,x) addressing the second byte of the instruction is added to the sum of the
Direct Register and the X Index Register to form the 16-bit effective address. The operand is always in
Bank 0.
Instruction:
Opcode
offset
Direct Register
+
offset
direct address
+
X Reg
Operand
Address:
00
effective address
3.5.12 Direct Indexed with Y-d,y
With Direct Indexed with Y (d,y) addressing the second byte of the instruction is added to the sum of the
Direct Register and the Y Index Register to form the 16-bit effective address. The operand is always in
Bank 0.
Instruction:
Opcode
offset
Direct Register
+
offset
direct address
+
Y Reg
Operand
Address:
00
effective address
3.5.13 Direct Indirect Indexed-(d),y
Direct Indirect Indexed ((d),y) addressing is often referred to as Indirect Y addressing. The second byte
of the instruction is added to the Direct Register (D). The 16-bit content of this memory location is then
combined with the Data Bank register to form a 24-bit base address. The Y Index Register is added to
the base address to form the effective address.
Instruction:
Opcode
offset
Direct Register
+
offset
00
(direct address)
then: +
DBR
base address
+
Y Reg
Operand
Address:
effective address