WDC 65 Series User manual

November 09, 2018
W65C816S
8/16–bit Microprocessor
WDC reserves the right to make changes at any time without notice in order to improve design and supply
the best possible product. Information contained herein is provided gratuitously and without liability, to any
user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee
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Sales and Sales Policies, copies of which are available upon request.
Copyright (C) 1981-2018 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction in whole or in part in anyform.

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TABLE OF CONTENTS
1INTRODUCTION......................................................................................................5
1.1 Features of the W65C816S.........................................................................................................5
2W65C816S FUNCTIONAL DESCRIPTION.............................................................6
2.1 Instruction Register (IR) .............................................................................................................6
2.2 Timing Control Unit (TCU)..........................................................................................................6
2.3 Arithmetic and Logic Unit (ALU)................................................................................................6
2.4 Accumulator (A) ..........................................................................................................................6
2.5 Data Bank Register (DBR)..........................................................................................................6
2.6 Direct (D) ......................................................................................................................................7
2.7 Index (X and Y) ............................................................................................................................7
2.8 Processor Status Register (P) ...................................................................................................7
2.9 Program Bank Register (PBR) ...................................................................................................7
2.10 Program Counter (PC) ................................................................................................................7
2.11 Stack Pointer (S) .........................................................................................................................7
2.12 Pin Function Description..........................................................................................................10
2.13 Abort (ABORTB)........................................................................................................................12
2.14 Address Bus (A0-A15) ..............................................................................................................12
2.15 Bus Enable (BE) ........................................................................................................................12
2.16 Data/Bank Address Bus (D0-D7) .............................................................................................13
2.17 Emulation Status (E).................................................................................................................13
2.18 Interrupt Request (IRQB)..........................................................................................................13
2.19 Memory Lock (MLB)..................................................................................................................13
2.20 Memory/Index Select Status (MX) ...........................................................................................13
2.21 Non-Maskable Interrupt (NMIB) ...............................................................................................14
2.22 Phase 2 In (PHI2).......................................................................................................................14
2.23 Read/Write (RWB) .....................................................................................................................14
2.24 Ready (RDY)...............................................................................................................................14
2.25 Reset (RESB).............................................................................................................................15
2.26 Valid Data Address (VDA) and Valid Program Address (VPA).............................................15
2.27 VDD and VSS.............................................................................................................................15
2.28 Vector Pull (VPB).......................................................................................................................15
3ADDRESSING MODES.........................................................................................16
3.1 Reset and Interrupt Vectors.....................................................................................................16
3.2 Stack...........................................................................................................................................16
3.3 Direct ..........................................................................................................................................16
3.4 Program Address Space ..........................................................................................................16
3.5 Data Address Space .................................................................................................................16
3.5.1 Absolute-a .................................................................................................................................17
3.5.2 Absolute Indexed Indirect-(a,x) .................................................................................................17
3.5.3 Absolute Indexed with X-a,x......................................................................................................17
3.5.4 Absolute Indexed with Y-a,y......................................................................................................17
3.5.5 Absolute Indirect-(a)..................................................................................................................18
3.5.6 Absolute Long Indexed With X-al,x...........................................................................................18
3.5.7 Absolute Long-al........................................................................................................................18
3.5.8 Accumulator-A...........................................................................................................................18
3.5.9 Block Move-xyc .........................................................................................................................19
3.5.10 Direct Indexed Indirect-(d,x)....................................................................................................19
3.5.11 Direct Indexed with X-d,x ........................................................................................................20
3.5.12 Direct Indexed with Y-d,y ........................................................................................................20

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3.5.13 Direct Indirect Indexed-(d),y....................................................................................................20
3.5.14 Direct Indirect Long Indexed-[d],y ...........................................................................................21
3.5.15 Direct Indirect Long-[d]............................................................................................................21
3.5.16 Direct Indirect-(d).....................................................................................................................21
3.5.17 Direct-d....................................................................................................................................22
3.5.18 Immediate-#.............................................................................................................................22
3.5.19 Implied-i...................................................................................................................................22
3.5.20 Program Counter Relative Long-rl...........................................................................................22
3.5.21 Program Counter Relative-r ....................................................................................................22
3.5.22 Stack-s.....................................................................................................................................22
3.5.23 Stack Relative-d,s....................................................................................................................23
3.5.24 Stack Relative Indirect Indexed-(d,s),y....................................................................................23
4TIMING, AC AND DC CHARACTERISTICS .........................................................25
4.1 Absolute Maximum Ratings.....................................................................................................25
4.2 DC Characteristics TA = -40°C to +85°C................................................................................25
5OPERATION TABLES...........................................................................................29
6RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS.................45
6.1 Directives...................................................................................................................................45
6.2 Comments..................................................................................................................................45
6.3 The Source Line ........................................................................................................................45
6.3.1 The Label Field....................................................................................................................45
6.3.2 The Operation Code Field...................................................................................................45
6.3.3 The Operand Field ..............................................................................................................46
6.3.4 Comment Field....................................................................................................................48
7Caveats .................................................................................................................49
7.1 Stack Addressing......................................................................................................................50
7.2 Direct Addressing .....................................................................................................................50
7.3 Absolute Indexed Addressing .................................................................................................50
7.4 ABORTB Input...........................................................................................................................50
7.5 VDA and VPA Valid Memory Address Output Signals..........................................................50
7.6 DB/BA operation when RDY is Pulled Low ............................................................................51
7.7 MX Output..................................................................................................................................51
7.8 All Opcodes Function in All Modes of Operation ..................................................................51
7.9 Indirect Jumps...........................................................................................................................51
7.10 Switching Modes.......................................................................................................................51
7.11 How Interrupts Affect the Program Bank and the Data Bank Registers .............................51
7.12 Binary Mode...............................................................................................................................52
7.13 Wait for Interrupt (WAI) Instruction..........................................................................................52
7.14 Stop-the-Clock (STP) Instruction.............................................................................................52
7.15 Co-Processor (COP) Signatures ..............................................................................................52
7.16 WDM Opcode Use .....................................................................................................................52
7.17 RDY Pulled During Write ..........................................................................................................52
7.18 MVN and MVP Affects on the Data Bank Register.................................................................52
7.19 Interrupt Priorities.....................................................................................................................53
7.20 Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers...................................................53
7.21 Stack Transfers .........................................................................................................................53
7.22 BRK Instruction.........................................................................................................................53
7.23 Accumulator switching from 8-bit to 16-bit............................................................................53
8HARD CORE MODEL ...........................................................................................54
8.1 W65C816 Core Information ......................................................................................................54
9SOFT CORE RTL MODEL ....................................................................................54

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9.1 W65C816 Synthesizable RTL-Code in Verilog HDL...............................................................54
10 ORDERING INFORMATION...............................................................................55
Table of Tables
Table 2-1 W65C816S Microprocessor Programming Model ...............................................................................................9
Table 2-2 Pin Function Table .........................................................................................................................................12
Table 3-1 Addressing Mode Summary..........................................................................................................................24
Table 4-1 Absolute Maximum Ratings ..........................................................................................................................25
Table 4-2 W65C816S AC Characteristics......................................................................................................................27
Table 5-1 W65C816S Instruction Set-Alphabetical Sequence.........................................................................................29
Table 5-2 Emulation Mode Vector Locations (8-bit Mode) ...............................................................................................30
Table 5-3 Native Mode Vector Locations (16-bit Mode) ...................................................................................................30
Table 5-4 Opcode Matrix...................................................................................................................................................31
Table 5-5 Operation, Operation Codes, and Status Register............................................................................................32
Table 6-1 Alternate Mnemonics.........................................................................................................................................46
Table 6-2 Address Mode Formats ....................................................................................................................................47
Table 6-3 Byte Selection Operator ................................................................................................................................48
Table 7-1 Caveats............................................................................................................................................................49
Table of Figures
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram..............................................................................8
Figure 2-2 W65C816S 40 Pin DIP Pinout.........................................................................................................................10
Figure 2-3 W65C816S 44 Pin PLCC Pinout.....................................................................................................................10
Figure 2-4 W65C816S 44 PIN QFP Pinout.......................................................................................................................11
Figure 4-1 General Timing Diagram .................................................................................................................................28
Figure 5-1 Bank Address Latching Circuit......................................................................................................................44

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1 INTRODUCTION
The W65C816S is a low power cost sensitive 8/16-bit microprocessor. The variable length instruction set
and manually optimized core size makes the W65C816S an excellent choice for low power System-on-Chip
(SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor
Company, provides packaged chips for evaluation or volume production. To aid in system development,
WDC provides a Professional Software Development Kit (ProSDK) that is available for free download on a
trial basis, see www.westerndesigncenter.com for more information.
The WDC W65C816S is a fully static CMOS 16-bit microprocessor featuring software compatibility* with the
8-bit NMOS and CMOS 6500-series predecessors. The W65C816S extends addressing to a full 16
megabytes. These devices offer the many advantages of CMOS technology, including increased noise
immunity, higher reliability, and greatly reduced power requirements. A software switch determines whether
the processor is in the 8-bit "emulation" mode, or in the native mode, thus allowing existing systems to use
the expanded features.
As shown in the W65C816S Processor Programming Model, Table 2-1, the Accumulator, ALU, X and Y
Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page
register augments the Direct Page addressing mode (formerly Zero Page addressing). Separate Program
Bank and Data Bank registers provide 24-bit memoryaddressing with segmented or linear addressing.
Four new signals provide the system designer with many options. The ABORTB input can interrupt the
currently executing instruction without modifying internal register, thus allowing virtual memory system
design. Valid Data Address (VDA) and Valid Program Address (VPA) outputs facilitate dual cache memory
by indicating whether a data segment or program segment is accessed. Modifying a vector is made easy by
monitoring the Vector Pull (VPB) output.
1.1 Features of the W65C816S
Advanced fully static CMOS design for low power
consumption and increased noise immunity
Wide operating voltage range, 1.8+/- 5%, 2.5+/-
5%, 3.0+/- 5%, 3.3+/- 10%, 5.0+/- 5% specified for
use with advanced low voltage peripherals
Emulation mode allows complete hardware and
software compatibility with 65xx designs
24-bit address bus provides access to 16 MBytes
of memory space
Full 16-bit ALU, Accumulator, Stack Pointer and
Index Registers
Valid Data Address (VDA) and Valid Program
Address (VPA) output for dual cache and cycle steal
DMA implementation
Vector Pull (VPB) output indicates when interrupt
vectors are being addressed
Abort (ABORTB) input and associated vector
supports processor repairs of bus error conditions
Low power consumption (300uA@1MHz)
Separate program and data bank registers allow
program segmentation or full 16 MByte linear
addressing
New Direct Register and stack relative addressing
provides capability for re-entrant, re-cursive and re-
locatable programming
24 addressing modes - 13 original W65C02S
modes with 92 instructions using 256 opcodes
Wait for Interrupt (WAI) and Stop-the-Clock (STP)
instructions further reduce power consumption,
decrease interrupt latency and allows synchronization
with external events
Co-Processor (COP) instruction with associated
vector supports co-processor configurations, i.e.,
floating point processors
Block move ability
*Except for the BBRx, BBSx, RMBx, and SMBx bit manipulation instructions which do not exist for the
W65C816S

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2 W65C816S FUNCTIONAL DESCRIPTION
The W65C816S provides the design engineer with upward software compatibility from 8-bit W65C02S in
applications to 16-bit system application. In Emulation mode, the W65C816S offers many advantages,
including full software compatibility withW65C02S coding.
Internal organization of the W65C816S can be divided into two parts: 1) The Register Section and 2) The
Control Section. Instructions obtained from program memory are executed by implementing a series of data
transfers within the Register Section. Signals that cause data transfers to be executed are generated within
the Control Section. The W65C816S has a 16-bit internal bus architecture with an 8-bit external data bus
and 24-bit external address bus.
2.1 Instruction Register (IR)
An Operation Code enters the processor on the Data Bus, and is latched into the IR during the opcode fetch
cycle. This opcode is then decoded, along with timing and interrupt signals, to generate various IR control
signals for use during instruction operations.
2.2 Timing Control Unit (TCU)
The Timing Control Unit keeps track of each instruction cycle as it is executed. The TCU is set to zero each
time an instruction fetch is executed, and is advanced at the beginning of each cycle for as many cycles as
is required to complete the instruction. Each data transfer between registers depends upon decoding the
contents of both the Instruction Register and the Timing Control Unit.
2.3 Arithmetic and Logic Unit (ALU)
All Arithmetic and Logic Unit operations take place within the 16-bit ALU. In addition to data operations, the
ALU also calculates the effective address for relative and indexed addressing modes. The result of a data
operation is stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags may
be updated following the ALU data operation.
2.4 Accumulator (A)
The Accumulator is a general purpose register which contains one of the operands and the result of most
arithmetic and logical operations. In the Native mode (E=0), when the Accumulator Select Bit (M) equals
zero, the Accumulator is established as 16 bits wide (A, B=C). When the Accumulator Select Bit (M) equals
one, the Accumulator is 8 bits wide (A). In this case, the upper 8 bits (B) may be used for temporary storage
in conjunction with the Exchange Accumulator (XBA) instruction.
2.5 Data Bank Register (DBR)
During modes of operation, the 8-bit Data Bank Register holds the bank address for memory transfers. The
24-bit address is composed of the 16-bit instruction effective address and the 8-bit Data Bank address. The
register value is multiplexed with the data value and is present on the Data/Address lines during the first half
of a data transfer memory cycle for the W65C816S. The DBR is initialized to zero during Reset.

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2.6 Direct (D)
The 16-bit Direct Register provides an address offset for all instructions using direct addressing. The
effective Direct Address is formed by adding the 8-bit instruction Direct Address field to the Direct Register.
The Direct Register is initialized to zero during Reset. The bank address for Direct Addressing is always
zero
2.7 Index (X and Y)
There are two general purpose registers that are commonly referred to as Index Registers (X and Y) and
are frequently used as an index value for calculation of the effective address. When executing an
instruction with indexed addressing, the microprocessor fetches the opcode and the base address, and then
modifies the address by adding an Index Register contents to the address prior to performing the desired
operation. Pre-indexing or post-indexing of indirect addresses may be selected. In the Native mode (E=0),
both Index Registers are 16 bits wide where the Index Select Bit (X) of the Processor Status (P) register
equals zero. If the Index Select Bit (X) equals one, both registers will be 8 bits wide, and the high byte is
forced to zero.
2.8 Processor Status Register (P)
The 8-bit Processor Status Register contains status flags and mode select bits. The Carry (C), Negative
(N), Overflow (V), and Zero (Z) status flags serve to report the status of most ALU operations. These status
flags are tested by use of Conditional Branch instructions. The Decimal (D), IRQ Disable (I),
Memory/Accumulator (M), and Index (X) bits are used as mode select flags. These flags are set by the
program to change microprocessor operations.
The Emulation (E) select and the Break (B) flags are accessible only through the Processor Status Register.
The Emulation mode select flag is selected by the Exchange Carry and Emulation Bits (XCE) instruction.
Table 8-1, W65C816S Compatibility Information, illustrates the features of the Native (E=0) and Emulation
(E=1) modes. The M and X flags are always equal to one in Emulation mode. When an interrupt occurs
during Emulation mode, the Break flag is written to stack memory as bit 4 of the Processor Status Register.
2.9 Program Bank Register (PBR)
The 8-bit Program Bank Register holds the bank address for all instruction fetches. The 24-bit address
consists of the 16-bit instruction effective address and the 8-bit Program Bank address. The register value
is multiplexed with the data bus and presented on the Data bus lines during the first half of a program
memory cycle. The Program Bank Register is initialized to zero during Reset. The PHK instruction pushes
the PBR register onto the Stack.
2.10 Program Counter (PC)
The 16-bit Program Counter Register provides the addresses which are used to step the microprocessor
through sequential 8-bit program instruction fields. The PC is incremented for each 8-bit instruction field that
is fetched from program memory.
2.11 Stack Pointer (S)
The Stack Pointer is a 16-bit register which is used to indicate the next available location in the stack
memory area. It serves as the effective address in stack addressing modes as well as subroutine and
interrupt processing. The Stack Pointer provides simple implementation of nested subroutines and multiple-
level interrupts. During Emulation mode, the S High-order byte (SH) is always equal to one. The bank
address for all stack operations is Bank zero.

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INTERUPT
LOGIC VDD
VSS
ABORTB
IRQB
NMIB
RESB
TIMING
CONT. RDY
CLOCK
GEN-
ERATOR PHI2
INSTRUCTION DECODE
MINTERMS
INSTRUCTION DECODE SUM OF
MINTERMS
REGISTER TRANSFER LOGIC
STSTEM CONTROL
RWB
VPA
VDA
MLB
VPB
E
MX
PROCESSOR
STATUS (P)
(8 BITS)
INSTRUCTION REGISTER
(8 BITS)
INTERNAL DATA BUS (16 BITS)
DATA
LATCH/
PREDECODER
INTERNAL SPECIAL BUS (16 BITS)
DATA BANK (DBR)
(8 BITS)
PROG. BANK (PBR)
(8 BITS)
DIRECT (D)
(16 BITS)
PROG. COUNTER
(PC) (16 BITS)
ACCUMULATOR
(C) (16 BITS)
(A) (8 BITS)
(B) (8 BITS)
TRANSFER
SWITCHES
ALU
(16 BITS)
STACK POINTER
(S) (16 BITS)
INDEX Y
(16 BITS)
INDEX X
(16 BITS)
ADDRESS BUFFER (LOW)
ADRESS BUFFER (HIGH)
DATA BUS/BANK ADDRESS BUFFER
INTERNAL ADDRESS BUS (16 BITS)
A0-A7
A8-A15
D0-D7
BE
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram

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Table 2-1 W65C816S Microprocessor Programming Model
8 Bits 8 Bits 8 Bits
X Register (XL)
Y Register (YL)
Stack Register (SL)
Accumulator (A)
Counter (PCL)
X Register (XH)
Stack Register (SH)
Y Register (YH)
Accumulator (B)
Program (PCH)
Direct Register (DH) Direct Register (DL)
Data Bank Register (DBR)
Data Bank Register (DBR)
00
Program Bank Register (PBR)
00
Shaded Blocks = 6502 registers
N V M X D I Z C
1 B E
BRK Bit 1=BRK 0=IRQ
Carry 1=true
Zero 1=result zero
IRQ disable 1=disable
Decimal mode 1=true
Index Register Select 1=8-bit, 0=16-bit
Memory Select 1=8-bit, 0=16-bit
Overflow 1=true
Negative 1=negative
Emulation
1=W65C02 Emulation Mode
0=Native Mode

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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VPB
RDY
ABORT
IRQB
MLB
NMIB
VPA
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RESB
VDA
MX
PHI2
BE
E
RWB
D0
D1
D2
D3
D4
D5
D6
D7
A15
A14
A13
A12
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
W65C816S
2.12 Pin Function Description
Figure 2-2 W65C816S 40 Pin DIP Pinout
Figure 2-3 W65C816S 44 Pin PLCC Pinout
W65C816S
6 5 4 3 2 1
44 43 42 41 40
18 19
20 21 22 23 24 25 26 27
28
NMIB
VPA
VDD
A0
A1
NC
A2
A3
A4
A5
A6
MLB IRQB ABORTB RDY VPB VSS RESB VDA MX PHI2 BE
E
RWB
VDD
D0
D1
D2
D3
D4
D5
D6
D7
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
A7 A8 A9
A10 A11
VSS VSS
A12 A13 A14 A15