Western Digital TN-55 User manual

J U L Y 1 9 9 8
WRL
Technical Note TN-55
The Memory
Daughter-Card
Version 1.5
User’s Manual
Marc A. Viredaz
d i gi t a l
Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA

The Western Research Laboratory (WRL) is a computer systems research group that
was founded by Digital Equipment Corporation in 1982. Our focus is computer science
research relevant to the design and application of high performance scientific computers.
We test our ideas by designing, building, and using real systems. The systems we build
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The Memory Daughter-Card Version 1.5
User's Manual
Marc A. Viredaz
July 1998
Abstract
The memory daughter-card is memory extension b oard for the Itsy pocket computer develop ed at
Compaq Computer Corp oration's Western Research Laboratory (WRL) . It provides an additional
bank of ash memory and up to three additional banks of DRAM. It is possible to b o ot from this
daughter-card. This document describes the architecture and the low-level programming mo del of
the memory daughter-card.
Revision 1.0

The Memory Daughter-Card Version 1.5 : User's Manual
Contents
Disclaimer 1
1 Intro duction 1
1.1 Purp ose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Architecture 2
2.1 Memory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Programmer's mo del 4
3.1 Memory daughter-card general-purp ose input/output signals . . . . . . . . . . . . . 4
3.2 Non-volatile memory identication structure . . . . . . . . . . . . . . . . . . . . . . . 5
References 5
List of Figures
1 Architecture of the memory daughter-card . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Tables
1 Memory daughter-card general-purp ose input/output signals . . . . . . . . . . . . . 4
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The Memory Daughter-Card Version 1.5 : User's Manual
Disclaimer
Compaq Computer Corp oration b elieves the information included in this pub-
lication is correct as of the date of publication. Such information is sub ject to
change without notice. Compaq is not resp onsible for inadvertent errors.
Compaq makes no representations that the use of its pro ducts in the man-
ner describ ed in this publication will not infringe on existing or future patent
rights, nor do the descriptions contained in this publication imply the granting
of licenses to make, use, or sell equipment or software in accordance with the
description.
1 Intro duction
This do cument describ es the architecture and the programmer's mo del of the memory daughter-
card for the Itsy pocket computer [Vir98]. It should b e considered as a guide for low-level software
develop ers.
A go o d understanding of the Itsy computer [Vir98] is assumed throughout this report.
1.1 Purp ose
The design of the memory daughter-card was aimed at achieving several goals :
 Provide additional ash memory and DRAM (memory extension).
 Be usable as a \safety daughter-card," i.e., it should b e p ossible to bo ot from the daughter-
card, in order to recover from a corrupted mother-b oard ash memory.
 Be usable as a system test and debug platform, i.e., it should be p ossible to boot from the
daughter-card and use so ckets for the ash memory, so that it can b e programmed with an
external programmer.
 Provide a prototyping platform to interface additional hardware to the Itsy computer.
1.2 History
The rst printed-circuit board (PCB) , referred to as memory daughter-card version 1.0 , was com-
pleted in November 1997. This rst prototyp e had a few minor aws, all of which could b e corrected.
The logic design corresponding to a mo died (i.e., patched) version 1.0 b oard is known as memory
daughter-card version 1.1 . This design corresponds only to a set of schematics, no physical PCB
having b een manufactured.
A second prototype, named memory daughter-card version 1.5 was complete in July 1998.
It corresp onds to a version 1.1 system with a few additional features. From the programmer's
p oint-of-view, there are almost no dierences between the versions 1.1 and 1.5.
This do cument describ es the memory daughter-card version 1.5. All relevant dierences b etween
the versions 1.1 and 1.5 are outlined in foot-notes.
WRL, Compaq 1

The Memory Daughter-Card Version 1.5 : User's Manual
16 Mbyte
Flash
Memory
4 Mbyte
32
RS-232
IrDA
Power
Mother
Board Screen
Touch
1
200 x 320
15 Gray L.
LCD
32
Processor
StrongARM
SA-1100
Interface
Analog
32
DRAM
16 Mbyte
Memory
Card
DRAM
Daughter
9
Flash
Memory
4 Mbyte
32
Telecom.
Codec
Points
Access
Memory
Bus
A/D
GPIO
SSP
SDLC
UART
USB
Figure 1: Architecture of the memory daughter-card.
1.3 Notations
In this rep ort, electrical signals are represented as upp er-case names in a sans-serif font (e.g.,
PWR EN ). Active-low signals are denoted byover-lines (e.g., RESET OUT ), while buses and element
of buses are specied by subscripts (e.g., DCD
31 :: 0
, DCA
0
). In the schematics, the same signals are
represented using the syntax and conventions of the WindowSIL [Tha97 ] CAD to ols. For example,
the signal DCCS
2
app ears as ~dccs[2] .
2 Architecture
Figure 1 presents the architecture of the memory daughter-card (right part), shown in resp ect to
the Itsy computer (left part). The memory daughter-card versions 1.1 and 1.5 are b oth compatible
with both versions of the Itsy mother-b oard (i.e., versions 1.1 and 1.5).
2.1 Memory system
The memory daughter-card features a ash memory deco ded as static-memory bank 2 and the
three dynamic random-access memory (DRAM) banks 1, 2, and 3. Dep ending on the application's
2 WRL, Compaq

The Memory Daughter-Card Version 1.5 : User's Manual
needs, only some of these banks (or even none) might be present. Since this daughter-card is
b o otable, the ash memory is also deco ded as static-memory bank 0, from which the StrongARM
SA-1100 processor [DEC98] b o ots.
2.1.1 Flash memory
A pair of 16-bit ash-memory circuits implement the 32-bit ash memory. These circuits can be
either soldered on the b oard or put in zero insertion force (ZIF) sockets . Many dierent devices
can b e accommo dated :
AMD Am29LV160B OssPT [AMD97e]
AMD Am29LV800 O - ss P T /Am29LV800B OssPT [AMD97c, AMD97d]
AMD Am29LV400 O - ss P T [AMD97a ]
AMD Am29LV200 O - ss P T [AMD97b]
Hitachi HN29V O 800 P - ss /HN29W O 800 P - ss [Hit97c, Hit97d]
Motorola M29F800A2 OPss /M29F800A3 OPss [Mot97]
Sharp LH28F800SG P -L ss [Sha97]
where \ O " sp ecies the internal sector organization, \ ss " sp ecies the sp eed, \ P " sp ecies the
package, and \ T " sp ecies the temp erature range. Any other compatible parts can also b e used.
Following the Itsy static-memory identication scheme [Vir98], a non-volatile memory identi-
cation structure describ es the characteristics of the sp ecic parts used on a given daughter-card
and hence allows the software to congure the memory interface correctly.
The reset/power-down pin of the ash-memory circuits is asserted (0) during a reset (i.e.,
hardware, software, or watch-dog reset) and during sleep mo de. When the ash memory do es not
need to b e accessed, this signal can also be asserted (0) by setting the signal GPIO
16
(
DCFLFOFF )
to 0 (see Section 3.1).
1
When the Itsy computer must boot from the daughter-card, this signal
should never b e set to 0 during sleep mode, since the pro cessor would be unable to read the b o ot
memory up on wake up. This can easily be achieved by setting bit 16 of the power manager GPIO
sleep state register PGSR of the StrongARM SA-1100 pro cessor [DEC98] to 1.
The ready/not-busy pins of the ash-memory circuits can b e monitored using the signals GPIO
17
( DCFL0RY =
BY ), for the least signicant16data bits D
15 :: 0
, and GPIO
18
( DCFL1RY = BY ), for the
most signicant 16 data bits D
31 :: 16
(see Section 3.1).
The hardware write-protection mechanism, featured by some of the supp orted parts, is never
used, and the corresp onding pin is always de-asserted (1). However, it is still possible to protect
the ash memory against write accesses, by using the jumper provided for this purpose. The ash
memory is protected when this jump er is open and is writable when this jump er is short-circuited.
2.1.2 Dynamic RAM
Three pairs of 64 Mbit (i.e., 2
12
rows  2
10
columns  16 bits) self-refresh DRAM circuits implement
the three 32-bit DRAM banks. Many dierent fast-page mode or enhanced data out (EDO) devices
can b e accommo dated :
1
On the memory daughter-card version 1.1, the reset/p ower-down pins are only asserted (0) during sleep mo de or
when the signal GPIO
16
(
DCFLFOFF ) is set to 0.
WRL, Compaq 3

The Memory Daughter-Card Version 1.5 : User's Manual
Signal Name Function Dir. Def.
GPIO
16
DCFLFOFF D aughter- c ard  ash memory f orce o O 1
GPIO
17
DCFL0RY = BY D aughter- c ard  ash memory 0r ead y / b us y I
GPIO
18
DCFL1RY = BY D aughter- c ard  ash memory 1r ead y / b us y I
Table 1: Memory daughter-card general-purp ose input/output signals.
Hitachi HM5165160ALTT- ss [Hit97a]
Hitachi HM5165165ALTT- ss [Hit97b]
Samsung KM416V4100AS-L ss /KM416V4100BS-L ss [Sam97a, Sam98a]
Samsung KM416V4104AS-L ss /KM416V4104BS-L ss [Sam97b, Sam98b]
Toshiba TC5165165AFTS- ss [Tos96 ]
where \ ss " sp ecies the sp eed. Any other compatible parts can also b e used.
Since all DRAM banks must b e accessed at the sp eed of the slowest one, it is b est to use the
same devices as on the Itsy mother-board, that is, 50 ns EDO DRAM circuits (KM416V4104AS-L5 ,
KM416V4104BS-L5 , or TC5165165AFTS-50 ).
3 Programmer's mo del
This section presents additional information on the mo del that the low-level software has of the
memory daughter-card hardware.
3.1 Memory daughter-card general-purp ose input/output signals
Table 1 shows the general-purpose input/output signals used on the memory daughter-card. Both
input signals can be used as interrupts. After a hardware reset (i.e., power-up or push-button
reset), all input/output signals are congured as input. Therefore, a pull-up resistor is used to
provide a default value to the signal GPIO
16
(
DCFLFOFF ), as shown in the last column of Table 1.
The function of all signals are :
GPIO
16
: DCFLFOFF : D aughter- c ard  ash memory f orce o
This output signal is used to control the reset/p ower-down pin of the ash-memory circuits
(see Section 2.1.1). When this signal is set to 0, the reset/p ower-down pins are asserted (0).
When it is set to 1, the reset/p ower-down pins are only asserted (0) during a reset (i.e.,
hardware, software, or watch-dog reset) and during sleep mo de.
2
A pull-up resistor sets the
default value of this signal to 1 when the GPIO
16
pin is congured as input (e.g., after a
hardware reset). When the Itsy computer must boot from the daughter-card, this signal
should never be set to 0 during sleep mo de, since the pro cessor would be unable to read
the b o ot memory up on wake up. This can b e easily achieved by setting bit 16 of the power
manager GPIO sleep state register PGSR of the StrongARM SA-1100 pro cessor [DEC98] to 1.
2
On the memory daughter-card version 1.1, the reset/power-down pins are only asserted (0) when this signal is
set to 0 and during sleep mode.
4 WRL, Compaq

The Memory Daughter-Card Version 1.5 : User's Manual
GPIO
17
: DCFL0RY = BY : D aughter- c ard  ash memory 0r ead y / b us y
This input signal is connected to the ready/not-busy pin of the ash-memory circuit used
for the least signicant16data bits D
15 :: 0
(see Section 2.1.1). It is set to 0 when the ash-
memory circuit is executing an erase or program operation and to 1 when it is ready for
use.
GPIO
18
: DCFL1RY =
BY : D aughter- c ard  ash memory 1r ead y / b us y
This input signal is connected to the ready/not-busy pin of the ash-memory circuit used
for the most signicant 16 data bits D
31 :: 16
(see Section 2.1.1). It is set to 0 when the ash-
memory circuit is executing an erase or program operation and to 1 when it is ready for
use.
3.2 Non-volatile memory identication structure
Following the Itsy static-memory identication scheme , the ash memory must implementa non-
volatile memory identication structure [Vir98]. The class identication value is CID =0, the
read-only bit is R =0, the daughter-card bit is D =1, and the width bit is W =0. The values of
the SIZE eld and of the dierent MSC elds depend on the sp ecic parts used on a given daughter-
card (see Section 2.1.1). The elds EN0 , RY =
BY0 , EN1 , and RY = BY1 , dening the general-purp ose
input/output signals, have the values EN0 =16=10
16
, RY = BY0 =17=11
16
, EN1 =16=10
16
,
and RY = BY1 =18=12
16
.
References
[AMD97a] Advanced Micro Devices. Am29LV400T/Am29LV400B : 4 Megabit (524,288  8-Bit/
262,144  16-Bit) CMOS 3.0 Volt-Only Sector Architecture Flash Memory ,May 1997.
Publication no. 20514, rev. B, amendment +1, preliminary.
[AMD97b] Advanced Micro Devices. Am29LV200T/Am29LV200B : 2 Megabit (262,144  8-Bit/
131,072  16-Bit) CMOS 3.0 Volt-Only Sector Architecture Flash Memory , August
1997. Publication no. 20513, rev. C, amendment +1, preliminary.
[AMD97c] Advanced Micro Devices. Am29LV800T/Am29LV800B : 8 Megabit (1,048,576  8-Bit/
524,288  16-Bit) CMOS 3.0 Volt-Only, Sectored Flash Memory ,Novemb er 1997. Pub-
lication no. 20478, rev. D, amendment 0, preliminary.
[AMD97d] Advanced Micro Devices. Am29LV800B : 8 Megabit (1 M  8-Bit/512 K  16-Bit)
CMOS 3.0 Volt-Only Boot Sector Flash Memory , Decemb er 1997. Publication no. 21490,
rev. E, amendment 0, preliminary.
[AMD97e] Advanced Micro Devices. Am29LV160B : 16 Megabit (2 M  8-Bit/1 M  16-Bit)
CMOS 3.0 Volt-Only Boot Sector Flash Memory , Decemb er 1997. Publication no. 21358,
rev. F, amendment 0, preliminary.
WRL, Compaq 5

The Memory Daughter-Card Version 1.5 : User's Manual
[DEC98] Digital Equipment Corporation, Maynard, MA (USA). DIGITAL Semiconductor
SA-1100 Microprocessor : Technical Reference Manual , March 1998. Do cument
no. EC-R5MTC-TE.
[Hit97a] Hitachi. HM5164160A Series, HM5165160A Series : 4194304-Word  16-Bit Dynamic
RAM , January 1997. Do cument no. ADE-203-596 (Z), rev. 0.1, preliminary.
[Hit97b] Hitachi. HM5164165A Series, HM5165165A Series : 4194304-Word  16-Bit Dynamic
RAM , April 1997. Do cument no. ADE-203-453 (Z), rev. 0.4, preliminary.
[Hit97c] Hitachi. HN29VT800 Series, HN29VB800 Series : 1048576-Word  8-Bit /
524288-Word  16-Bit CMOS Flash Memory , April 1997. Do cument
no. ADE-203-781A (Z), rev. 1.0.
[Hit97d] Hitachi. HN29WT800 Series, HN29WB800 Series : 1048576-Word  8-Bit /
524288-Word  16-Bit CMOS Flash Memory , May 1997. Do cument
no. ADE-203-537A (Z), rev. 1.0.
[Mot97] Motorola. M29F800A3, M29F800A2 : 8 M CMOS Flash Memory , October 1997. Do c-
ument no. M29F800A3/D , rev. 4.
[Sam97a] Samsung Electronics. KM416V4000A, KM416V4100A CMOS DRAM : 4M  16 Bit
CMOS Dynamic RAM with Fast Page Mode , 1997.
[Sam97b] Samsung Electronics. KM416V4004A, KM416V4104A CMOS DRAM : 4M  16 Bit
CMOS Dynamic RAM with Extended Data Out , 1997.
[Sam98a] Samsung Electronics. KM416V4000B, KM416V4100B CMOS DRAM : 4M  16 Bit
CMOS Dynamic RAM with Fast Page Mode , 1998. Preliminary sp ec.
[Sam98b] Samsung Electronics. KM416V4004B, KM416V4104B CMOS DRAM : 4M  16 Bit
CMOS Dynamic RAM with Extended Data Out , 1998. Preliminary sp ec.
[Sha97] Sharp. LH28F800SG : 8 Mbit (512 Kbit  16) SmartVoltage Flash Memory , February
1997. Preliminary.
[Tha97] C. Thacker. WindowSIL/WC User's Guide .SRC, Digital Equipment Corp oration, Palo
Alto, CA (USA), February 1997.
[Tos96] Toshiba. Toshiba MOS Digital Integrated Circuit TC5165165AJS/AFTS-40
TC5165165AJS/AFTS-50 TC5165165AJS/AFTS-60 Silicon Gate CMOS :
4,194,304 Words  16 Bit EDO (Hyper Page) Dynamic RAM , Octob er 1996.
Tentative data.
[Vir98] Marc A. Viredaz. The Itsy Pocket Computer Version 1.5 : User's Manual . Technical
note TN-54, WRL, Compaq, Palo Alto, CA (USA), July 1998. Revision 1.0.
6 WRL, Compaq

7
WRL Research Reports
‘‘Titan System Manual.’’ Michael J. K. Nielsen.
WRL Research Report 86/1, September 1986.
‘‘Global Register Allocation at Link Time.’’ David
W. Wall. WRL Research Report 86/3, October
1986.
‘‘Optimal Finned Heat Sinks.’’ William
R. Hamburgen. WRL Research Report 86/4,
October 1986.
‘‘The Mahler Experience: Using an Intermediate
Language as the Machine Description.’’ David
W. Wall and Michael L. Powell. WRL
Research Report 87/1, August 1987.
‘‘The Packet Filter: An Efficient Mechanism for
User-level Network Code.’’ Jeffrey C. Mogul,
Richard F. Rashid, Michael J. Accetta. WRL
Research Report 87/2, November 1987.
‘‘Fragmentation Considered Harmful.’’ Christopher
A. Kent, Jeffrey C. Mogul. WRL Research
Report 87/3, December 1987.
‘‘Cache Coherence in Distributed Systems.’’
Christopher A. Kent. WRL Research Report
87/4, December 1987.
‘‘Register Windows vs. Register Allocation.’’ David
W. Wall. WRL Research Report 87/5, December
1987.
‘‘Editing Graphical Objects Using Procedural
Representations.’’ Paul J. Asente. WRL
Research Report 87/6, November 1987.
‘‘The USENET Cookbook: an Experiment in
Electronic Publication.’’ Brian K. Reid. WRL
Research Report 87/7, December 1987.
‘‘MultiTitan: Four Architecture Papers.’’ Norman
P. Jouppi, Jeremy Dion, David Boggs, Michael
J. K. Nielsen. WRL Research Report 87/8, April
1988.
‘‘Fast Printed Circuit Board Routing.’’ Jeremy
Dion. WRL Research Report 88/1, March 1988.
‘‘Compacting Garbage Collection with Ambiguous
Roots.’’ Joel F. Bartlett. WRL Research Report
88/2, February 1988.
‘‘The Experimental Literature of The Internet: An
Annotated Bibliography.’’ Jeffrey C. Mogul.
WRL Research Report 88/3, August 1988.
‘‘Measured Capacity of an Ethernet: Myths and
Reality.’’ David R. Boggs, Jeffrey C. Mogul,
Christopher A. Kent. WRL Research Report
88/4, September 1988.
‘‘Visa Protocols for Controlling Inter-Organizational
Datagram Flow: Extended Description.’’
Deborah Estrin, Jeffrey C. Mogul, Gene
Tsudik, Kamaljit Anand. WRL Research
Report 88/5, December 1988.
‘‘SCHEME->C A Portable Scheme-to-C Compiler.’’
Joel F. Bartlett. WRL Research Report 89/1,
January 1989.
‘‘Optimal Group Distribution in Carry-Skip Ad-
ders.’’ Silvio Turrini. WRL Research Report
89/2, February 1989.
‘‘Precise Robotic Paste Dot Dispensing.’’ William
R. Hamburgen. WRL Research Report 89/3,
February 1989.
‘‘Simple and Flexible Datagram Access Controls for
Unix-based Gateways.’’ Jeffrey C. Mogul.
WRL Research Report 89/4, March 1989.
‘‘Spritely NFS: Implementation and Performance of
Cache-Consistency Protocols.’’ V. Srinivasan
and Jeffrey C. Mogul. WRL Research Report
89/5, May 1989.
‘‘Available Instruction-Level Parallelism for Super-
scalar and Superpipelined Machines.’’ Norman
P. Jouppi and David W. Wall. WRL Research
Report 89/7, July 1989.
‘‘A Unified Vector/Scalar Floating-Point Architec-
ture.’’ Norman P. Jouppi, Jonathan Bertoni,
and David W. Wall. WRL Research Report
89/8, July 1989.

8
‘‘Architectural and Organizational Tradeoffs in the
Design of the MultiTitan CPU.’’ Norman
P. Jouppi. WRL Research Report 89/9, July
1989.
‘‘Integration and Packaging Plateaus of Processor
Performance.’’ Norman P. Jouppi. WRL
Research Report 89/10, July 1989.
‘‘A 20-MIPS Sustained 32-bit CMOS Microproces-
sor with High Ratio of Sustained to Peak Perfor-
mance.’’ Norman P. Jouppi and Jeffrey
Y. F. Tang. WRL Research Report 89/11, July
1989.
‘‘The Distribution of Instruction-Level and Machine
Parallelism and Its Effect on Performance.’’
Norman P. Jouppi. WRL Research Report
89/13, July 1989.
‘‘Long Address Traces from RISC Machines:
Generation and Analysis.’’ Anita Borg,
R.E.Kessler, Georgia Lazana, and David
W. Wall. WRL Research Report 89/14, Septem-
ber 1989.
‘‘Link-Time Code Modification.’’ David W. Wall.
WRL Research Report 89/17, September 1989.
‘‘Noise Issues in the ECL Circuit Family.’’ Jeffrey
Y.F. Tang and J. Leon Yang. WRL Research
Report 90/1, January 1990.
‘‘Efficient Generation of Test Patterns Using
Boolean Satisfiablilty.’’ Tracy Larrabee. WRL
Research Report 90/2, February 1990.
‘‘Two Papers on Test Pattern Generation.’’ Tracy
Larrabee. WRL Research Report 90/3, March
1990.
‘‘Virtual Memory vs. The File System.’’ Michael
N. Nelson. WRL Research Report 90/4, March
1990.
‘‘Efficient Use of Workstations for Passive Monitor-
ing of Local Area Networks.’’ Jeffrey C. Mogul.
WRL Research Report 90/5, July 1990.
‘‘A One-Dimensional Thermal Model for the VAX
9000 Multi Chip Units.’’ John S. Fitch. WRL
Research Report 90/6, July 1990.
‘‘1990 DECWRL/Livermore Magic Release.’’
Robert N. Mayo, Michael H. Arnold, Walter
S. Scott, Don Stark, Gordon T. Hamachi.
WRL Research Report 90/7, September 1990.
‘‘Pool Boiling Enhancement Techniques for Water at
Low Pressure.’’ Wade R. McGillis, John
S. Fitch, William R. Hamburgen, Van
P. Carey. WRL Research Report 90/9, December
1990.
‘‘Writing Fast X Servers for Dumb Color Frame Buf-
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91/1, February 1991.
‘‘A Simulation Based Study of TLB Performance.’’
J. Bradley Chen, Anita Borg, Norman
P. Jouppi. WRL Research Report 91/2, Novem-
ber 1991.
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cuits.’’ Don Stark. WRL Research Report 91/3,
April 1991.
‘‘TurboChannel T1 Adapter.’’ David Boggs. WRL
Research Report 91/4, April 1991.
‘‘Procedure Merging with Instruction Caches.’’
Scott McFarling. WRL Research Report 91/5,
March 1991.
‘‘Don’t Fidget with Widgets, Draw!.’’ Joel Bartlett.
WRL Research Report 91/6, May 1991.
‘‘Pool Boiling on Small Heat Dissipating Elements in
Water at Subatmospheric Pressure.’’ Wade
R. McGillis, John S. Fitch, William
R. Hamburgen, Van P. Carey. WRL Research
Report 91/7, June 1991.
‘‘Incremental, Generational Mostly-Copying Gar-
bage Collection in Uncooperative Environ-
ments.’’ G. May Yip. WRL Research Report
91/8, June 1991.
‘‘Interleaved Fin Thermal Connectors for Multichip
Modules.’’ William R. Hamburgen. WRL
Research Report 91/9, August 1991.
‘‘Experience with a Software-defined Machine Ar-
chitecture.’’ David W. Wall. WRL Research
Report 91/10, August 1991.

9
‘‘Network Locality at the Scale of Processes.’’
Jeffrey C. Mogul. WRL Research Report 91/11,
November 1991.
‘‘Cache Write Policies and Performance.’’ Norman
P. Jouppi. WRL Research Report 91/12, Decem-
ber 1991.
‘‘Packaging a 150 W Bipolar ECL Microprocessor.’’
William R. Hamburgen, John S. Fitch. WRL
Research Report 92/1, March 1992.
‘‘Observing TCP Dynamics in Real Networks.’’
Jeffrey C. Mogul. WRL Research Report 92/2,
April 1992.
‘‘Systems for Late Code Modification.’’ David
W. Wall. WRL Research Report 92/3, May
1992.
‘‘Piecewise Linear Models for Switch-Level Simula-
tion.’’ Russell Kao. WRL Research Report 92/5,
September 1992.
‘‘A Practical System for Intermodule Code Optimiza-
tion at Link-Time.’’ Amitabh Srivastava and
David W. Wall. WRL Research Report 92/6,
December 1992.
‘‘A Smart Frame Buffer.’’ Joel McCormack & Bob
McNamara. WRL Research Report 93/1,
January 1993.
‘‘Recovery in Spritely NFS.’’ Jeffrey C. Mogul.
WRL Research Report 93/2, June 1993.
‘‘Tradeoffs in Two-Level On-Chip Caching.’’
Norman P. Jouppi & Steven J.E. Wilton. WRL
Research Report 93/3, October 1993.
‘‘Unreachable Procedures in Object-oriented
Programing.’’ Amitabh Srivastava. WRL
Research Report 93/4, August 1993.
‘‘An Enhanced Access and Cycle Time Model for
On-Chip Caches.’’ Steven J.E. Wilton and Nor-
man P. Jouppi. WRL Research Report 93/5,
July 1994.
‘‘Limits of Instruction-Level Parallelism.’’ David
W. Wall. WRL Research Report 93/6, November
1993.
‘‘Fluoroelastomer Pressure Pad Design for
Microelectronic Applications.’’ Alberto
Makino, William R. Hamburgen, John
S. Fitch. WRL Research Report 93/7, November
1993.
‘‘A 300MHz 115W 32b Bipolar ECL Microproces-
sor.’’ Norman P. Jouppi, Patrick Boyle,
Jeremy Dion, Mary Jo Doherty, Alan Eustace,
Ramsey Haddad, Robert Mayo, Suresh Menon,
Louis Monier, Don Stark, Silvio Turrini, Leon
Yang, John Fitch, William Hamburgen, Rus-
sell Kao, and Richard Swan. WRL Research
Report 93/8, December 1993.
‘‘Link-Time Optimization of Address Calculation on
a 64-bit Architecture.’’ Amitabh Srivastava,
David W. Wall. WRL Research Report 94/1,
February 1994.
‘‘ATOM: A System for Building Customized
Program Analysis Tools.’’ Amitabh Srivastava,
Alan Eustace. WRL Research Report 94/2,
March 1994.
‘‘Complexity/Performance Tradeoffs with Non-
Blocking Loads.’’ Keith I. Farkas, Norman
P. Jouppi. WRL Research Report 94/3, March
1994.
‘‘A Better Update Policy.’’ Jeffrey C. Mogul.
WRL Research Report 94/4, April 1994.
‘‘Boolean Matching for Full-Custom ECL Gates.’’
Robert N. Mayo, Herve Touati. WRL Research
Report 94/5, April 1994.
‘‘Software Methods for System Address Tracing:
Implementation and Validation.’’ J. Bradley
Chen, David W. Wall, and Anita Borg. WRL
Research Report 94/6, September 1994.
‘‘Performance Implications of Multiple Pointer
Sizes.’’ Jeffrey C. Mogul, Joel F. Bartlett,
Robert N. Mayo, and Amitabh Srivastava.
WRL Research Report 94/7, December 1994.

10
‘‘How Useful Are Non-blocking Loads, Stream Buf-
fers, and Speculative Execution in Multiple Issue
Processors?.’’ Keith I. Farkas, Norman
P. Jouppi, and Paul Chow. WRL Research
Report 94/8, December 1994.
‘‘Drip: A Schematic Drawing Interpreter.’’ Ramsey
W. Haddad. WRL Research Report 95/1, March
1995.
‘‘Recursive Layout Generation.’’ Louis M. Monier,
Jeremy Dion. WRL Research Report 95/2,
March 1995.
‘‘Contour: A Tile-based Gridless Router.’’ Jeremy
Dion, Louis M. Monier. WRL Research Report
95/3, March 1995.
‘‘The Case for Persistent-Connection HTTP.’’
Jeffrey C. Mogul. WRL Research Report 95/4,
May 1995.
‘‘Network Behavior of a Busy Web Server and its
Clients.’’ Jeffrey C. Mogul. WRL Research
Report 95/5, October 1995.
‘‘The Predictability of Branches in Libraries.’’ Brad
Calder, Dirk Grunwald, and Amitabh Srivas-
tava. WRL Research Report 95/6, October 1995.
‘‘Shared Memory Consistency Models: A Tutorial.’’
Sarita V. Adve, Kourosh Gharachorloo. WRL
Research Report 95/7, September 1995.
‘‘Eliminating Receive Livelock in an Interrupt-driven
Kernel.’’ Jeffrey C. Mogul and
K. K. Ramakrishnan. WRL Research Report
95/8, December 1995.
‘‘Memory Consistency Models for Shared-Memory
Multiprocessors.’’ Kourosh Gharachorloo.
WRL Research Report 95/9, December 1995.
‘‘Register File Design Considerations in Dynamically
Scheduled Processors.’’ Keith I. Farkas, Nor-
man P. Jouppi, Paul Chow. WRL Research
Report 95/10, November 1995.
‘‘Optimization in Permutation Spaces.’’ Silvio Tur-
rini. WRL Research Report 96/1, November
1996.
‘‘Shasta: A Low Overhead, Software-Only Approach
for Supporting Fine-Grain Shared Memory.’’
Daniel J. Scales, Kourosh Gharachorloo, and
Chandramohan A. Thekkath. WRL Research
Report 96/2, November 1996.
‘‘Efficient Procedure Mapping using Cache Line
Coloring.’’ Amir H. Hashemi, David R. Kaeli,
and Brad Calder. WRL Research Report 96/3,
October 1996.
‘‘Optimizations and Placement with the Genetic
Workbench.’’ Silvio Turrini. WRL Research
Report 96/4, November 1996.
‘‘Memory-system Design Considerations for
Dynamically-scheduled Processors.’’ Keith
I. Farkas, Paul Chow, Norman P. Jouppi, and
Zvonko Vranesic. WRL Research Report 97/1,
February 1997.
‘‘Performance of the Shasta Distributed Shared
Memory Protocol.’’ Daniel J. Scales and
Kourosh Gharachorloo. WRL Research Report
97/2, February 1997.
‘‘Fine-Grain Software Distributed Shared Memory
on SMP Clusters.’’ Daniel J. Scales, Kourosh
Gharachorloo, and Anshu Aggarwal. WRL
Research Report 97/3, February 1997.
‘‘Potential benefits of delta encoding and data com-
pression for HTTP.’’ Jeffrey C. Mogul, Fred
Douglis, Anja Feldmann, and Balachander
Krishnamurthy. WRL Research Report 97/4,
July 1997.

11
WRL Technical Notes
‘‘TCP/IP PrintServer: Print Server Protocol.’’ Brian
K. Reid and Christopher A. Kent. WRL Tech-
nical Note TN-4, September 1988.
‘‘TCP/IP PrintServer: Server Architecture and Im-
plementation.’’ Christopher A. Kent. WRL
Technical Note TN-7, November 1988.
‘‘Smart Code, Stupid Memory: A Fast X Server for a
Dumb Color Frame Buffer.’’ Joel McCormack.
WRL Technical Note TN-9, September 1989.
‘‘Why Aren’t Operating Systems Getting Faster As
Fast As Hardware?.’’ John Ousterhout. WRL
Technical Note TN-11, October 1989.
‘‘Mostly-Copying Garbage Collection Picks Up
Generations and C++.’’ Joel F. Bartlett. WRL
Technical Note TN-12, October 1989.
‘‘Characterization of Organic Illumination Systems.’’
Bill Hamburgen, Jeff Mogul, Brian Reid, Alan
Eustace, Richard Swan, Mary Jo Doherty, and
Joel Bartlett. WRL Technical Note TN-13, April
1989.
‘‘Improving Direct-Mapped Cache Performance by
the Addition of a Small Fully-Associative Cache
and Prefetch Buffers.’’ Norman P. Jouppi.
WRL Technical Note TN-14, March 1990.
‘‘Limits of Instruction-Level Parallelism.’’ David
W. Wall. WRL Technical Note TN-15, Decem-
ber 1990.
‘‘The Effect of Context Switches on Cache Perfor-
mance.’’ Jeffrey C. Mogul and Anita Borg.
WRL Technical Note TN-16, December 1990.
‘‘MTOOL: A Method For Detecting Memory Bot-
tlenecks.’’ Aaron Goldberg and John Hen-
nessy. WRL Technical Note TN-17, December
1990.
‘‘Predicting Program Behavior Using Real or Es-
timated Profiles.’’ David W. Wall. WRL Tech-
nical Note TN-18, December 1990.
‘‘Cache Replacement with Dynamic Exclusion.’’
Scott McFarling. WRL Technical Note TN-22,
November 1991.
‘‘Boiling Binary Mixtures at Subatmospheric Pres-
sures.’’ Wade R. McGillis, John S. Fitch, Wil-
liam R. Hamburgen, Van P. Carey. WRL
Technical Note TN-23, January 1992.
‘‘A Comparison of Acoustic and Infrared Inspection
Techniques for Die Attach.’’ John S. Fitch.
WRL Technical Note TN-24, January 1992.
‘‘TurboChannel Versatec Adapter.’’ David Boggs.
WRL Technical Note TN-26, January 1992.
‘‘A Recovery Protocol For Spritely NFS.’’ Jeffrey
C. Mogul. WRL Technical Note TN-27, April
1992.
‘‘Electrical Evaluation Of The BIPS-0 Package.’’
Patrick D. Boyle. WRL Technical Note TN-29,
July 1992.
‘‘Transparent Controls for Interactive Graphics.’’
Joel F. Bartlett. WRL Technical Note TN-30,
July 1992.
‘‘Design Tools for BIPS-0.’’ Jeremy Dion & Louis
Monier. WRL Technical Note TN-32, December
1992.
‘‘Link-Time Optimization of Address Calculation on
a 64-Bit Architecture.’’ Amitabh Srivastava
and David W. Wall. WRL Technical Note
TN-35, June 1993.
‘‘Combining Branch Predictors.’’ Scott McFarling.
WRL Technical Note TN-36, June 1993.
‘‘Boolean Matching for Full-Custom ECL Gates.’’
Robert N. Mayo and Herve Touati. WRL
Technical Note TN-37, June 1993.
‘‘Piecewise Linear Models for Rsim.’’ Russell Kao,
Mark Horowitz. WRL Technical Note TN-40,
December 1993.
‘‘Speculative Execution and Instruction-Level Paral-
lelism.’’ David W. Wall. WRL Technical Note
TN-42, March 1994.

12
‘‘Ramonamap - An Example of Graphical Group-
ware.’’ Joel F. Bartlett. WRL Technical Note
TN-43, December 1994.
‘‘ATOM: A Flexible Interface for Building High Per-
formance Program Analysis Tools.’’ Alan Eus-
tace and Amitabh Srivastava. WRL Technical
Note TN-44, July 1994.
‘‘Circuit and Process Directions for Low-Voltage
Swing Submicron BiCMOS.’’ Norman
P. Jouppi, Suresh Menon, and Stefanos
Sidiropoulos. WRL Technical Note TN-45,
March 1994.
‘‘Experience with a Wireless World Wide Web
Client.’’ Joel F. Bartlett. WRL Technical Note
TN-46, March 1995.
‘‘I/O Component Characterization for I/O Cache
Designs.’’ Kathy J. Richardson. WRL Tech-
nical Note TN-47, April 1995.
‘‘Attribute caches.’’ Kathy J. Richardson, Michael
J. Flynn. WRL Technical Note TN-48, April
1995.
‘‘Operating Systems Support for Busy Internet Ser-
vers.’’ Jeffrey C. Mogul. WRL Technical Note
TN-49, May 1995.
‘‘The Predictability of Libraries.’’ Brad Calder,
Dirk Grunwald, Amitabh Srivastava. WRL
Technical Note TN-50, July 1995.
‘‘Simultaneous Multithreading: A Platform for Next-
generation Processors.’’ Susan J. Eggers, Joel
Emer, Henry M. Levy, Jack L. Lo, Rebecca
Stamm and Dean M. Tullsen. WRL Technical
Note TN-52, March 1997.
‘‘Reducing Compulsory and Capacity Misses.’’
Norman P. Jouppi. WRL Technical Note
TN-53, August 1990.
‘‘The Itsy Pocket Computer Version 1.5: User’s
Manual.’’ Marc A. Viredaz. WRL Technical
Note TN-54, July 1998.
‘‘The Memory Daughter-Card Version 1.5: User’s
Manual.’’ Marc A. Viredaz. WRL Technical
Note TN-55, July 1998.

13
WRL Research Reports and Technical Notes are available on the World Wide Web, from
http://www.research.digital.com/wrl/techreports/index.html.