Winbond W632GU6NB Series Operating and maintenance instructions

W632GU6NB
16M 8 BANKS 16 BIT DDR3L SDRAM
Publication Release Date: Aug. 20, 2018
Revision: A01
- 1 -
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES...........................................................................................................................................5
3. ORDER INFORMATION.......................................................................................................................6
4. KEY PARAMETERS.............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................9
6. BALL DESCRIPTION..........................................................................................................................10
7. BLOCK DIAGRAM..............................................................................................................................12
8. FUNCTIONAL DESCRIPTION............................................................................................................13
8.1 Basic Functionality..............................................................................................................................13
8.2 RESET and Initialization Procedure....................................................................................................13
8.2.1 Power-up Initialization Sequence.....................................................................................13
8.2.2 Reset Initialization with Stable Power ..............................................................................15
8.3 Programming the Mode Registers.......................................................................................................16
8.3.1 Mode Register MR0.........................................................................................................18
8.3.1.1 Burst Length, Type and Order................................................................................19
8.3.1.2 CAS Latency...........................................................................................................19
8.3.1.3 Test Mode...............................................................................................................20
8.3.1.4 DLL Reset...............................................................................................................20
8.3.1.5 Write Recovery.......................................................................................................20
8.3.1.6 Precharge PD DLL .................................................................................................20
8.3.2 Mode Register MR1.........................................................................................................21
8.3.2.1 DLL Enable/Disable................................................................................................21
8.3.2.2 Output Driver Impedance Control...........................................................................22
8.3.2.3 ODT RTT Values....................................................................................................22
8.3.2.4 Additive Latency (AL) .............................................................................................22
8.3.2.5 Write leveling..........................................................................................................22
8.3.2.6 Output Disable........................................................................................................22
8.3.3 Mode Register MR2.........................................................................................................23
8.3.3.1 Partial Array Self Refresh (PASR)..........................................................................24
8.3.3.2 CAS Write Latency (CWL)......................................................................................24
8.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT).............................24
8.3.3.4 Dynamic ODT (Rtt_WR).........................................................................................24
8.3.4 Mode Register MR3.........................................................................................................25
8.3.4.1 Multi Purpose Register (MPR)................................................................................25
8.4 No OPeration (NOP) Command..........................................................................................................26
8.5 Deselect Command.............................................................................................................................26
8.6 DLL-off Mode ......................................................................................................................................26
8.7 DLL on/off switching procedure...........................................................................................................27
8.7.1 DLL “on” to DLL “off” Procedure.......................................................................................27
8.7.2 DLL “off” to DLL “on” Procedure.......................................................................................28
8.8 Input clock frequency change .............................................................................................................29
8.8.1 Frequency change during Self-Refresh............................................................................29
8.8.2 Frequency change during Precharge Power-down..........................................................29
8.9 Write Leveling .....................................................................................................................................31
8.9.1 DRAM setting for write leveling & DRAM termination function in that mode ....................32

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 2 -
8.9.2 Write Leveling Procedure.................................................................................................32
8.9.3 Write Leveling Mode Exit .................................................................................................34
8.10 Multi Purpose Register........................................................................................................................35
8.10.1 MPR Functional Description.............................................................................................36
8.10.2 MPR Register Address Definition.....................................................................................37
8.10.3 Relevant Timing Parameters............................................................................................37
8.10.4 Protocol Example.............................................................................................................37
8.11 ACTIVE Command..............................................................................................................................43
8.12 PRECHARGE Command....................................................................................................................43
8.13 READ Operation .................................................................................................................................44
8.13.1 READ Burst Operation.....................................................................................................44
8.13.2 READ Timing Definitions..................................................................................................45
8.13.2.1 READ Timing; Clock to Data Strobe relationship....................................................46
8.13.2.2 READ Timing; Data Strobe to Data relationship.....................................................47
8.13.2.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation.............................................48
8.13.2.4 tRPRE Calculation..................................................................................................49
8.13.2.5 tRPST Calculation..................................................................................................49
8.13.2.6 Burst Read Operation followed by a Precharge......................................................55
8.14 WRITE Operation................................................................................................................................57
8.14.1 DDR3L Burst Operation...................................................................................................57
8.14.2 WRITE Timing Violations.................................................................................................57
8.14.2.1 Motivation...............................................................................................................57
8.14.2.2 Data Setup and Hold Violations..............................................................................57
8.14.2.3 Strobe to Strobe and Strobe to Clock Violations.....................................................57
8.14.2.4 Write Timing Parameters........................................................................................57
8.14.3 Write Data Mask...............................................................................................................58
8.14.4 tWPRE Calculation...........................................................................................................59
8.14.5 tWPST Calculation...........................................................................................................59
8.15 Refresh Command..............................................................................................................................66
8.16 Self-Refresh Operation .......................................................................................................................68
8.17 Power-Down Modes............................................................................................................................70
8.17.1 Power-Down Entry and Exit.............................................................................................70
8.17.2 Power-Down clarifications - Case 1 .................................................................................76
8.17.3 Power-Down clarifications - Case 2 .................................................................................76
8.17.4 Power-Down clarifications - Case 3 .................................................................................77
8.18 ZQ Calibration Commands..................................................................................................................78
8.18.1 ZQ Calibration Description...............................................................................................78
8.18.2 ZQ Calibration Timing......................................................................................................79
8.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading......................................79
8.19 On-Die Termination (ODT)..................................................................................................................80
8.19.1 ODT Mode Register and ODT Truth Table ......................................................................80
8.19.2 Synchronous ODT Mode..................................................................................................81
8.19.2.1 ODT Latency and Posted ODT...............................................................................81
8.19.2.2 Timing Parameters.................................................................................................81
8.19.2.3 ODT during Reads..................................................................................................83
8.19.3 Dynamic ODT ..................................................................................................................84
8.19.3.1 Functional Description:...........................................................................................84
8.19.3.2 ODT Timing Diagrams............................................................................................85
8.19.4 Asynchronous ODT Mode................................................................................................89

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 3 -
8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions..........................................90
8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry..90
8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit.....93
8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods 94
9. OPERATION MODE ...........................................................................................................................95
9.1 Command Truth Table........................................................................................................................95
9.2 CKE Truth Table .................................................................................................................................97
9.3 Simplified State Diagram.....................................................................................................................98
10. ELECTRICAL CHARACTERISTICS...................................................................................................99
10.1 Absolute Maximum Ratings ................................................................................................................99
10.2 Operating Temperature Condition.......................................................................................................99
10.3 DC & AC Operating Conditions...........................................................................................................99
10.3.1 Recommended DC Operating Conditions........................................................................99
10.4 Input and Output Leakage Currents..................................................................................................100
10.5 Interface Test Conditions ..................................................................................................................100
10.6 DC and AC Input Measurement Levels.............................................................................................101
10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals..................101
10.6.2 DC and AC Input Levels for Single-Ended Data Signals................................................101
10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)...........103
10.6.4 Single-ended requirements for differential signals .........................................................104
10.6.5 Differential Input Cross Point Voltage ............................................................................105
10.6.6 Slew Rate Definitions for Single-Ended Input Signals....................................................106
10.6.7 Slew Rate Definitions for Differential Input Signals........................................................106
10.7 DC and AC Output Measurement Levels..........................................................................................107
10.7.1 Output Slew Rate Definition and Requirements.............................................................107
10.7.1.1 Single Ended Output Slew Rate...........................................................................108
10.7.1.2 Differential Output Slew Rate ...............................................................................109
10.8 Output Driver DC Electrical Characteristics ......................................................................................110
10.8.1 Output Driver Temperature and Voltage sensitivity........................................................112
10.9 On-Die Termination (ODT) Levels and Characteristics.....................................................................113
10.9.1 ODT Levels and I-V Characteristics...............................................................................113
10.9.2 ODT DC Electrical Characteristics.................................................................................114
10.9.3 ODT Temperature and Voltage sensitivity .....................................................................114
10.9.4 Design guide lines for RTTPU and RTTPD .......................................................................115
10.10 ODT Timing Definitions............................................................................................................116
10.10.1 Test Load for ODT Timings............................................................................................116
10.10.2 ODT Timing Definitions..................................................................................................116
10.11 Input/Output Capacitance........................................................................................................120
10.12 Overshoot and Undershoot Specifications...............................................................................121
10.12.1 AC Overshoot /Undershoot Specification for Address and Control Pins:.......................121
10.12.2 AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask Pins: ........121
10.13 IDD and IDDQ Specification Parameters and Test Conditions................................................122
10.13.1 IDD and IDDQ Measurement Conditions.......................................................................122
10.13.2 IDD Current Specifications.............................................................................................132
10.14 Clock Specification ..................................................................................................................133
10.15 Speed Bins..............................................................................................................................134
10.15.1 DDR3L-1333 Speed Bin and Operating Conditions.......................................................134
10.15.2 DDR3L-1600 Speed Bin and Operating Conditions.......................................................135
10.15.3 DDR3L-1866 Speed Bin and Operating Conditions.......................................................136

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 4 -
10.15.4 DDR3L-2133 Speed Bin and Operating Conditions.......................................................137
10.15.5 Speed Bin General Notes ..............................................................................................138
10.16 AC Characteristics...................................................................................................................139
10.16.1 AC Timing and Operating Condition for -09/09I/09J/-11/11I/11J speed grades.............139
10.16.2 AC Timing and Operating Condition for -12/12I/12J/-15/15I/15J speed grades.............143
10.16.3 Timing Parameter Notes................................................................................................147
10.16.4 Address / Command Setup, Hold and Derating .............................................................150
10.16.5 Data Setup, Hold and Slew Rate Derating.....................................................................157
11. Backward Compatible to 1.5V DDR3 SDRAM VDD/VDDQ Requirements .......................................159
11.1 Input/Output Functional.....................................................................................................................159
11.2 Recommended DC Operating Conditions - DDR3L (1.35V) operation..............................................159
11.3 Recommended DC Operating Conditions - DDR3 (1.5V) operation..................................................159
11.4 VDD/VDDQ Voltage Switch between DDR3L and DDR3..................................................................159
12. PACKAGE SPECIFICATION ............................................................................................................161
13. REVISION HISTORY........................................................................................................................162

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 5 -
1. GENERAL DESCRIPTION
The W632GU6NB is a 2G bits DDR3L SDRAM, organized as 16,777,216 words 8banks 16 bits.
This device achieves high speed transfer rates up to 2133 MT/s (DDR3L-2133) for various
applications. This device is sorted into the following speed grades: -09, -11, -12, -15, 09I, 11I, 12I, 15I,
09J, 11J, 12J and 15J.
The -09 ,09I and 09J speed grades are compliant to the DDR3-2133L (14-14-14) specification (The
09I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 09J industrial plus
grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C).
The -11 ,11I and 11J speed grades are compliant to the DDR3L-1866 (13-13-13) specification (The
11I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 11J industrial plus
grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C).
The -12, 12I and 12J speed grades are compliant to the DDR3L-1600 (11-11-11) specification (The
12I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 12J industrial plus
grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C).
The -15, 15I and 15J speed grades are compliant to the DDR3L-1333 (9-9-9) specification (The 15I
industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 15J industrial plus grade
which is guaranteed to support -40°C ≤ TCASE ≤ 105°C).
The W632GU6NB is designed to comply with the following key DDR3L SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V
Backward compatible to VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 6 -
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
System level timing calibration support via write leveling and MPR read pattern
ZQ Calibration for output driver and ODT using external reference resistor to ground
Asynchronous RESET# pin for Power-up initialization sequence and reset function
Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
Dynamic ODT mode for improved signal integrity and preselectable termination impedances during
writes
2K Byte page size
Packaged in VFBGA 96 Ball (7.5 x13 mm2with thickness of 1.0 mm), using lead free materials
with RoHS compliant
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
OPERATING TEMPERATURE
W632GU6NB-09
DDR3L-2133 (14-14-14)
0°C ≤TCASE ≤95°C
W632GU6NB09I
DDR3L-2133 (14-14-14)
-40°C ≤TCASE ≤95°C
W632GU6NB09J
DDR3L-2133 (14-14-14)
-40°C ≤TCASE ≤105°C
W632GU6NB-11
DDR3L-1866 (13-13-13)
0°C ≤TCASE ≤95°C
W632GU6NB11I
DDR3L-1866 (13-13-13)
-40°C ≤TCASE ≤95°C
W632GU6NB11J
DDR3L-1866 (13-13-13)
-40°C ≤TCASE ≤105°C
W632GU6NB-12
DDR3L-1600 (11-11-11)
0°C ≤TCASE ≤95°C
W632GU6NB12I
DDR3L-1600 (11-11-11)
-40°C ≤TCASE ≤95°C
W632GU6NB12J
DDR3L-1600 (11-11-11)
-40°C ≤TCASE ≤105°C
W632GU6NB-15
DDR3L-1333 (9-9-9)
0°C ≤TCASE ≤95°C
W632GU6NB15I
DDR3L-1333 (9-9-9)
-40°C ≤TCASE ≤95°C
W632GU6NB15J
DDR3L-1333 (9-9-9)
-40°C ≤TCASE ≤105°C

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 7 -
4. KEY PARAMETERS
Speed Bin
DDR3L-2133
DDR3L-1866
DDR3L-1600
DDR3L-1333
Unit
CL-nRCD-nRP
14-14-14
13-13-13
11-11-11
9-9-9
Part Number Extension
-09/09I/09J
-11/11I/11J
-12/12I/12J
-15/15I/15J
Parameter
Sym.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Maximum operating frequency using
maximum allowed settings for Sup_CL
and Sup_CWL
fCKMAX

1066

933

800

667
MHz
Internal read command to first data
tAA
13.09
20
13.91
(13.125)*6
20
13.75
(13.125)*5
20
13.5
(13.125)*5
20
nS
ACT to internal read or write delay
time
tRCD
13.09

13.91
(13.125)*6

13.75
(13.125)*5

13.5
(13.125)*5

nS
PRE command period
tRP
13.09

13.91
(13.125)*6

13.75
(13.125)*5

13.5
(13.125)*5

nS
ACT to ACT or REF command period
tRC
46.09

47.91
(47.125)*6

48.75
(48.125)*5

49.5
(49.125)*5

nS
ACT to PRE command period
tRAS
33
9 * tREFI
34
9 * tREFI
35
9 * tREFI
36
9 * tREFI
nS
CL = 5
CWL = 5
tCK(AVG)
3.0
3.3
3.0
3.3
3.0
3.3
3.0
3.3
nS
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
2.5
3.3
2.5
3.3
2.5
3.3
nS
CL = 7
CWL = 6
tCK(AVG)
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
nS
CL = 8
CWL = 6
tCK(AVG)
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
nS
CL = 9
CWL = 7
tCK(AVG)
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
nS
CL = 10
CWL = 7
tCK(AVG)
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
nS
CL = 11
CWL = 8
tCK(AVG)
1.25
< 1.5
1.25
< 1.5
1.25
< 1.5
Reserved
nS
CL = 13
CWL = 9
tCK(AVG)
1.07
< 1.25
1.07
< 1.25
Reserved
Reserved
nS
CL = 14
CWL = 10
tCK(AVG)
0.938
< 1.07
Reserved
Reserved
Reserved
nS
Supported CL Settings
Sup_CL
5, 6, 7, 8, 9, 10,
11, 13, 14
5, 6, (7), 8, (9), 10,
(11), 13
5, 6, (7), 8, (9), 10,
11
5, 6, (7), 8, 9, 10
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7, 8, 9, 10
5, 6, 7, 8, 9
5, 6, 7, 8
5, 6, 7
nCK
Average
periodic
refresh
Interval
-40°C ≤TCASE ≤85°C
tREFI

7.8*2, 3

7.8*2, 3

7.8*2, 3

7.8*2, 3
μS
0°C ≤TCASE ≤85°C

7.8*1

7.8*1

7.8*1

7.8*1
μS
85°C < TCASE ≤95°C

3.9*4

3.9*4

3.9*4

3.9*4
μS
95°C < TCASE ≤105°C

3.9*4

3.9*4

3.9*4

3.9*4
μS
Operating One Bank Active-Precharge
Current
IDD0

140

135

120

110
mA
Operating One Bank Active-Read-
Precharge Current
IDD1

175

160

145

130
mA
Operating Burst Read Current
IDD4R

230

210

190

165
mA
Operating Burst Write Current
IDD4W

260

235

210

185
mA
Burst Refresh Current
IDD5B

195

190

180

175
mA
Normal Temperature Self-Refresh
Current
IDD6

15

15

15

15
mA
Operating Bank Interleave Current
IDD7

290

260

235

205
mA

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 8 -
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤TCASE ≤85°C with full JEDEC AC and DC specifications.
2. The -09, -11, -12 and -15 speed grades, -40°C ≤TCASE < 0°C is not available.
3. The 09I, 09J, 11I, 11J, 12I, 12J, 15I and 15J speed grades support -40°C ≤TCASE ≤85°C with full JEDEC AC and DC
specifications.
4. The -09, 09I, -11, 11I, -12, 12I, -15 and 15I speed grades, TCASE is able to extend to 95°C. The 09J, 11J, 12J and 15J speed
grades, TCASE is able to extend to 105°C. They are with doubling Auto Refresh commands in frequency to a 32 mS period ( tREFI
= 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b
and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
5. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings must be
programmed to match. For example, DDR3L-1333 (9-9-9) devices supporting down binning to DDR3L-1066 (7-7-7) should program
13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3L-1600 (11-11-11) devices supporting
down binning to DDR3L-1333 (9-9-9) or DDR3L-1066 (7-7-7) should program 13.125 nS in SPD bytes for tAAmin (Byte16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21, 23) also should be programmed
accordingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3L-1333 (9-9-9) and 48.125 nS (tRASmin +
tRPmin = 35 nS + 13.125 nS) for DDR3L-1600 (11-11-11).
6. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRP min must be 13.125 nS. SPD settings must be
programmed to match. For example, DDR3L-1866 (13-13-13) devices supporting down binning to DDR3L-1600 (11-11-11) or
DDR3L-1333 (9-9-9) or DDR3L-1066 (7-7-7) should program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and
tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21, 23) also should be programmed accordingly. For
example, 47.125nS (tRASmin + tRPmin = 34 nS + 13.125 nS).

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 9 -
5. BALL CONFIGURATION
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
DQU4
M
N
DQSU#
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK#
A10/AP
NC
A12/BC# BA1
VREFCA
ZQ
VDD
VSS
DQL5
VSS
DQL3
VSSQ
VSSQ
DQU2
DQU6
VDDQ VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
DQU7
VSS
DQU1
DMU
DQL0
DQSL
DQSL#
DQL4
RAS#
CAS#
WE#
BA2
A0
A3
BA0
CS#
VDD
VSS
VDDQ
DQL6
DQL2
VSSQ
VDDQ
DQU3
VDD
DQU5
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
P
R
T
A1
A11
NC A8
A6
A4 VSS
VDD
VSS
VSS
VDD
VSS RESET#
A7
A5 A2
A9
A13

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 10 -
6. BALL DESCRIPTION
BALL NUMBER
SYMBOL
TYPE
DESCRIPTION
J7, K7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#.
K9
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates,
internal clock signals and device input buffers and output drivers.
Taking CKE Low provides Precharge Power Down and Self-Refresh
operation (all banks idle), or Active Power Down (row Active in any
bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and
VREFDQ have become stable during the power on and initialization
sequence, they must be maintained during all operations (including
Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are
disabled during power down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
L2
CS#
Input
Chip Select: All commands are masked when CS# is registered HIGH.
CS# provides for external Rank selection on systems with multiple
Ranks. CS# is considered part of the command code.
K1
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR3L SDRAM. When enabled, ODT is
applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU, and DML
signal. The ODT signal will be ignored if Mode Registers MR1 and
MR2 are programmed to disable ODT and during Self Refresh.
J3, K3, L3
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
command being entered.
D3, E7
DMU, DML
Input
Input Data Mask: DMU and DML are the input mask signals control the
lower or upper bytes for write data. Input data is masked when
DMU/DML is sampled HIGH coincident with that input data during a
Write access. DM is sampled on both edges of DQS.
M2, N8, M3
BA0−BA2
Input
Bank Address Inputs: BA0−BA2 define to which bank an Active, Read,
Write, or Precharge command is being applied. Bank address also
determines which mode register is to be accessed during a MRS
cycle.
N3, P7, P3, N2, P8,
P2, R8, R2, T8, R3,
L7, R7, N7, T3
A0−A13
Input
Address Inputs: Provide the row address for Active commands and the
column address for Read/Write commands to select one location out
of the memory array in the respective bank. (A10/AP and A12/BC#
have additional functions; see below). The address inputs also provide
the op-code during Mode Register Set command.
Row address: A0−A13.
Column address: A0−A9.
L7
A10/AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to
determine whether Auto-precharge should be performed to the
accessed bank after the Read/Write operation.
(HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled
during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by bank addresses.
N7
A12/BC#
Input
Burst Chop: A12/BC# is sampled during Read and Write commands to
determine if burst chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See section 9.1
“Command Truth Table”on page 95 for details.
T2
RESET#
Input
Active Low Asynchronous Reset: Reset is active when RESET# is
LOW, and inactive when RESET# is HIGH. RESET# must be HIGH
during normal operation. RESET# is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD, RESET# active is destructive to
data contents.

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Publication Release Date: Aug. 20, 2018
Revision: A01
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E3, F7, F2, F8, H3,
H8, G2, H7
DQL0−DQL7
Input/Output
Data Input/Output: Lower byte of Bi-directional data bus.
D7, C3, C8, C2, A7,
A2, B8, A3
DQU0−DQU7
Input/Output
Data Input/Output: Upper byte of Bi-directional data bus.
F3, G3
DQSL, DQSL#
Input/Output
Lower byte data Strobe: Data Strobe output with read data, input with
write data of DQL[7:0]. Edge-aligned with read data, centered in write
data. DQSL is paired with DQSL# to provide differential pair signaling
to the system during read and write data transfer. DDR3L SDRAM
supports differential data strobe only and does not support single-
ended.
C7, B7
DQSU, DQSU#
Input/Output
Upper byte data Strobe: Data Strobe output with read data, input with
write data of DQU[7:0]. Edge-aligned with read data, centered in write
data. DQSU is paired with DQSU# to provide differential pair signaling
to the system during read and write data transfer. DDR3L SDRAM
supports differential data strobe only and does not support single-
ended.
B2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
Supply
Power Supply: 1.283V to 1.45V operational.
A9, B3, E1, G8, J2,
J8, M1, M9, P1, P9,
T1, T9
VSS
Supply
Ground.
A1, A8, C1, C9, D2,
E9, F1, H2, H9
VDDQ
Supply
DQ Power Supply: 1.283V to 1.45V operational.
B1, B9, D1, D8, E2,
E8, F9, G1, G9
VSSQ
Supply
DQ Ground.
H1
VREFDQ
Supply
Reference voltage for DQ.
M8
VREFCA
Supply
Reference voltage for Control, Command and Address inputs.
L8
ZQ
Supply
External reference ball for output drive and On-Die Termination
Impedance calibration: This ball needs an external 240 Ω± 1%
external resistor (RZQ), connected from this ball to ground to perform
ZQ calibration.
J1, J9, L1, L9, M7,
T7
NC
No Connect: No internal electrical connection is present.
Note:
Input only balls (BA0-BA2, A0-A13, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 12 -
7. BLOCK DIAGRAM
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN
DECODER
SENSE
AMPLIFIER
COLUMN
DECODER
SENSE
AMPLIFIER
DATA CONTROL CIRCUIT
DM MASK LOGIC
DQ
BUFFER
COLUMN
DECODER
SENSE
AMPLIFIER
NOTE: The cell array configuration is 16384 * 1024 * 16
ROW DECODER
ROW DECODERROW DECODER
A0
A9
A11
A12
A13
CS#
RAS#
CAS#
WE#
CK, CK#
PREFETCH REGISTER
ODT
CONTROL
COLUMN
DECODER
SENSE
AMPLIFIER
COLUMN
DECODER
COLUMN
DECODER
SENSE
AMPLIFIER
COLUMN
DECODER
CELL ARRAY
BANK #5
ROW DECODER ROW DECODER
ROW DECODERROW DECODER
ODT
CELL ARRAY
BANK #7
CELL ARRAY
BANK #4
CELL ARRAY
BANK #6
CELL ARRAY
BANK #3
CELL ARRAY
BANK #2
CELL ARRAY
BANK #1
ZQ CAL
ZQCL, ZQCS
RZQ
VSSQ
ZQ
To ODT/output drivers
BA2
BA1
BA0
COLUMN
DECODER
SENSE
AMPLIFIER
ROW DECODER
CELL ARRAY
BANK #0
DLL
CK, CK#
WRITE
drivers
READ
drivers
DQL0−DQL7
LDQS, LDQS#
DQU0−DQU7
LDQS, LDQS#
DQL0−DQL7
LDQS, LDQS#
DQU0−DQU7
UDQS, UDQS#
LDM, UDM
LDM, UDM
Note: RZQ and VSSQ are external component

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 13 -
8. FUNCTIONAL DESCRIPTION
8.1 Basic Functionality
The DDR3L SDRAM is a high-speed dynamic random-access memory internally configured as an
eight-bank DRAM. The DDR3L SDRAM uses an 8n prefetch architecture to achieve high-speed
operation. The 8n prefetch architecture is combined with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write operation for the DDR3L SDRAM consists
of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-
bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3L SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write
command. The address bits registered coincident with the Active command are used to select the
bank and row to be activated (BA0-BA2 select the bank; A0-A13 select the row). The address bits
registered coincident with the Read or Write command are used to select the starting column location
for the burst operation, determine if the auto precharge command is to be issued (via A10), and select
BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3L SDRAM must be powered up and initialized in a predefined
manner. The following sections provide detailed information covering device reset and initialization,
register definition, command descriptions, and device operation.
8.2 RESET and Initialization Procedure
8.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 * VDD; all other inputs may be
undefined). RESET# needs to be maintained for minimum 200 µS with stable power. CKE is pulled
“Low” any time before RESET# being de-asserted (min. time 10 nS). The power voltage ramp time
between 300 mV to VDD min. must be no greater than 200 mS; and during the ramp, VDD ≥VDDQ
and (VDD - VDDQ) < 0.3 Volts.
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
In addition, VTT is limited to 0.95 V max once power ramp is finished, AND
VREF tracks VDDQ/2.
OR
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & VREF.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 µS until CKE becomes active. During this time,
the DRAM will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 nS or 5 tCK (which is larger)
before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to
clock (tIS) must be met. Also, a NOP or Deselect command must be registered (with tIS set up time
to clock) before CKE goes active. Once the CKE is registered “High” after Reset, CKE needs to be
continuously registered “High” until the initialization sequence is finished, including expiration of
tDLLK and tZQinit.

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Publication Release Date: Aug. 20, 2018
Revision: A01
- 14 -
4. The DDR3L SDRAM keeps its on-die termination in high-impedance state as long as RESET# is
asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET#
deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS
before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be
statically held at either LOW or HIGH. If Rtt_Nom is to be enabled in MR1, the ODT input signal
must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the
first MRS command to load mode register. (tXPR=max (tXS ; 5 * tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2,
provide “Low” to BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3,
provide “Low” to BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL
Enable”command, provide “Low” to A0, “High” to BA0 and “Low” to BA1-BA2).
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL
reset command, provide “High” to A8 and “Low” to BA0-2).
10.Issue ZQCL command to starting ZQ calibration.
11.Wait for both tDLLK and tZQinit completed.
12.The DDR3L SDRAM is now ready for normal operation.
TIME BREAK DON'T CARE
Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK, CK#
VDD, VDDQ
RESET#
Command
BA
ODT
RTT
tCKSRX
T = 200 µs T = 500 µs
tDLLK
VALID
VALID
VALID
VALIDStatic LOW in case Rtt_Nom is enabled at time Tg. Otherwise static HIGH or LOW
*1ZQCLMRS*1 MRSMRSMRS
MR2 MR3 MR1 MR0
tIS
tIS
tIS
tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
Tmin
CKE
10 ns
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 1 –Reset and Initialization Sequence at Power-on Ramping

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 15 -
8.2.2 ResetInitialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be
undefined). RESET needs to be maintained for minimum 100 nS. CKE is pulled “LOW” before
RESET being de-asserted (min. time 10 nS).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3L SDRAM is ready for normal operation.
TIME BREAK DON'T CARE
Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK, CK#
VDD, VDDQ
RESET#
Command
BA
ODT
RTT
tCKSRX
T = 100 ns T = 500 µs
tDLLK
VALID
VALID
VALID
VALIDStatic LOW in case Rtt_Nom is enabled at time Tg. Otherwise static HIGH or LOW
*1ZQCLMRS*1 MRSMRSMRS
MR2 MR3 MR1 MR0
tIS
tIS
tIS
tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
Tmin = 10 ns
CKE
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 2 –Reset Procedure at Power Stable Condition

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 16 -
8.3 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode
Registers, provided by the DDR3L SDRAM, as user defined variables and they must be programmed
via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not
defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after
power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by
re-executing the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the
accessed mode register must be redefined when the MRS command is issued. MRS command and
DLL Reset do not affect array contents, which mean these commands can be executed any time after
power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the
mode register and is the minimum time required between two MRS commands shown in Figure 3.
TIME BREAK DON'T CARE
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2
CK#
CK
Command
ODT
CKE
VALID
Address
VALID
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALID
VALID VALID VALIDNOP/DESNOP/DESMRSNOP/DESNOP/DESMRS
VALID
ODT
Settings
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALIDVALID VALID
Old settings Updating Settings New Settings
tMRD tMOD
ODTLoff+1
Rtt_Nom DISABLED prior and/or after MRS command
Rtt_Nom ENABLED prior and/or after MRS command
Figure 3 –tMRD Timing

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 17 -
The MRS command to Non-MRS command delay, tMOD is required for the DRAM to update the
features, except DLL reset, and is the minimum time required from a MRS command to a non-MRS
command excluding NOP and DES shown in Figure 4.
TIME BREAK DON'T CARE
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2
CK#
CK
Command
ODT
CKE
VALID
Address
VALID
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALID
VALID VALID VALIDNOP/DESNOP/DESNOP/DESNOP/DESNOP/DESMRS
VALID
ODT
Settings
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALIDVALID VALID
Old settings Updating Settings New Settings
tMOD
Rtt_Nom ENABLED prior and/or after MRS command
Rtt_Nom DISABLED prior and/or after MRS command
ODTLoff+1
Figure 4 –tMOD Timing
The mode register contents can be changed using the same command and timing requirements
during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state
with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register.
If the Rtt_Nom Feature is enabled in the Mode Register prior and/or after a MRS command, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state prior to the MRS
command. The ODT signal may be registered high after tMOD has expired. If the Rtt_Nom feature is
disabled in the Mode Register prior and after a MRS command, the ODT signal can be registered
either LOW or HIGH before, during and after the MRS command. The mode registers are divided into
various fields depending on the functionality and/or modes.

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 18 -
8.3.1 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3L SDRAM. It
controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for
precharge Power Down, which include various vendor specific options to make DDR3L SDRAM useful
for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#,
BA0, BA1 and BA2, while controlling the states of address pins according to the Figure 5 below.
DLL Control for Precharge PD
DLL ResetA8
MRS mode
WR(cycles)
A3 Read Burst Type
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0*1 PPD WR DLL RBT
CL BLTM
0
1No
Yes
BA1 BA0
0 0
0 1
1 0
1 1
MR0
MR1
MR2
MR3
A12
1
0 Slow exit (DLL off)
Fast exit (DLL on)
Burst Length
Address Field
Mode Register 0
Write recovery for Auto precharge CAS Latency
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
1
0
A2
0
0
0
0
0
0
0
0
Latency
Reserved
7
8
9
11
10
5
6
BLA0A1
0
00 18 (Fixed) BC4 or 8 (on the fly)
A11
0
0
0
0
1
1
1
1
A10
0
0
1
1
0
0
1
1
A9
0
1
0
1
0
1
1
0
16*2
5*2
6*2
7*2
8*2
10*2
14*2
12*2
ModeA7
0
1Normal
Test 0
1
Nibble Sequential
Interleave
0
0
A13
CL
0
0
0
0
1
1
1
1
1
10 1BC4 (Fixed) Reserved
BA2
0*1
0
1
00
0
11
1
1Reserved
14
13
0
0
0
0
10 11 1Reserved Reserved
1
0
0
1
11
1
01
1
1Reserved
Reserved
Reserved
1
1
1
A6
Notes:
1. BA2 and A13 are reserved for future use and must be programmed to “0” during MRS.
2. WR (write recovery for Auto precharge)min in clock cycles is calculated by dividing tWR (in nS) by tCK (in nS) and rounding
up to the next integer: WRmin[cycles] = Roundup(tWR[nS] / tCK(avg)[nS]). The WR value in the mode register must be
programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported CAS Latency, please refer to “Speed
Bins”tables for each frequency.
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 5 –MR0 Definition

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 19 -
8.3.1.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type
is selected via bit A3 as shown in Figure 5. The ordering of accesses within a burst is determined by
the burst length, burst type, and the starting column address as shown in Table 1. The burst length is
defined by bits A0-A1. Burst length options include fixed BC4, fixed BL8 and ‘on the fly’ which allows
BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#.
Table 1 –Burst Type and Burst Order
Burst
Length
READ/
WRITE
Starting Column Address
(A2, A1, A0)
Burst type = Sequential
(decimal)
A3 = 0
Burst type = Interleaved
(decimal)
A3 = 1
NOTES
4
Chop
READ
0 0 0
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1, 2, 3
0 0 1
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
1, 2, 3
0 1 0
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1, 2, 3
0 1 1
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1, 2, 3
1 0 0
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1, 2, 3
1 0 1
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1, 2, 3
1 1 0
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1, 2, 3
1 1 1
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1, 2, 3
WRITE
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1, 2, 4, 5
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
1, 2, 4, 5
8
READ
0 0 0
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
0 0 1
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
0 1 0
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
0 1 1
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
2
1 0 0
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
2
1 0 1
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
1 1 0
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
1 1 1
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
WRITE
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the
BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being
selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation.
This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don't Care.
8.3.1.2 CAS Latency
The CAS Latency is defined by MR0 (bits A2, A4, A5 and A6) as shown in Figure 5. CAS Latency is
the delay, in clock cycles, between the internal Read command and the availability of the first bit of
output data. DDR3L SDRAM does not support any half-clock latencies. The overall Read Latency (RL)
is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. For more information on the
supported CL and AL settings based on the operating clock frequency, refer to section 10.15 “Speed
Bins”on page 134. For detailed Read operation refer to section 8.13 “READ Operation”on page 44.

W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 20 -
8.3.1.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values
shown in Figure 5. Programming bit A7 to a ‘1’ places the DDR3L SDRAM into a test mode that is only
used by the DRAM Manufacturer and should NOT be used. No operations or functionality is specified
if A7 = 1.
8.3.1.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset
function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any
time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL
can be used (i.e., Read commands or ODT synchronous operations).
8.3.1.5 Write Recovery
The programmed WR value MR0 (bits A9, A10 and A11) is used for the auto precharge feature along
with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by
dividing tWR (in nS) by tCK(avg) (in nS) and rounding up to the next integer: WRmin[cycles] =
Roundup(tWR[nS]/tCK(avg)[nS]). The WR must be programmed to be equal to or larger than tWR(min).
8.3.1.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power down mode. When MR0 (A12
= 0), or ‘slow-exit’, the DLL is frozen after entering precharge power down (for potential power savings)
and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or
‘fast-exit’, the DLL is maintained after entering precharge power down and upon exiting power down
requires tXP to be met prior to the next valid command.