Winbond W632GG6KB Series User manual

W632GG6KB
16M 8 BANKS 16 BIT DDR3 SDRAM
Publication Release Date: Jan. 03, 2017
Revision: A06
- 1 -
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES...........................................................................................................................................5
3. ORDER INFORMATION.......................................................................................................................6
4. KEY PARAMETERS.............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. BLOCK DIAGRAM..............................................................................................................................11
8. FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality..............................................................................................................................12
8.2 RESET and Initialization Procedure....................................................................................................12
8.2.1 Power-up Initialization Sequence.....................................................................................12
8.2.2 Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1 Mode Register MR0.........................................................................................................17
8.3.1.1 Burst Length, Type and Order................................................................................18
8.3.1.2 CAS Latency...........................................................................................................18
8.3.1.3 Test Mode...............................................................................................................19
8.3.1.4 DLL Reset...............................................................................................................19
8.3.1.5 Write Recovery.......................................................................................................19
8.3.1.6 Precharge PD DLL .................................................................................................19
8.3.2 Mode Register MR1.........................................................................................................20
8.3.2.1 DLL Enable/Disable................................................................................................20
8.3.2.2 Output Driver Impedance Control...........................................................................21
8.3.2.3 ODT RTT Values....................................................................................................21
8.3.2.4 Additive Latency (AL) .............................................................................................21
8.3.2.5 Write leveling..........................................................................................................21
8.3.2.6 Output Disable........................................................................................................21
8.3.3 Mode Register MR2.........................................................................................................22
8.3.3.1 Partial Array Self Refresh (PASR)..........................................................................23
8.3.3.2 CAS Write Latency (CWL)......................................................................................23
8.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT).............................23
8.3.3.4 Dynamic ODT (Rtt_WR).........................................................................................23
8.3.4 Mode Register MR3.........................................................................................................24
8.3.4.1 Multi Purpose Register (MPR)................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1 DLL “on” to DLL “off” Procedure.......................................................................................26
8.7.2 DLL “off” to DLL “on” Procedure.......................................................................................27
8.8 Input clock frequency change .............................................................................................................28
8.8.1 Frequency change during Self-Refresh............................................................................28
8.8.2 Frequency change during Precharge Power-down..........................................................28
8.9 Write Leveling .....................................................................................................................................30
8.9.1 DRAM setting for write leveling & DRAM termination function in that mode ....................31

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 2 -
8.9.2 Write Leveling Procedure.................................................................................................31
8.9.3 Write Leveling Mode Exit .................................................................................................33
8.10 Multi Purpose Register........................................................................................................................34
8.10.1 MPR Functional Description.............................................................................................35
8.10.2 MPR Register Address Definition.....................................................................................36
8.10.3 Relevant Timing Parameters............................................................................................36
8.10.4 Protocol Example.............................................................................................................36
8.11 ACTIVE Command..............................................................................................................................42
8.12 PRECHARGE Command....................................................................................................................42
8.13 READ Operation .................................................................................................................................43
8.13.1 READ Burst Operation.....................................................................................................43
8.13.2 READ Timing Definitions..................................................................................................44
8.13.2.1 READ Timing; Clock to Data Strobe relationship....................................................45
8.13.2.2 READ Timing; Data Strobe to Data relationship.....................................................46
8.13.2.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation.............................................47
8.13.2.4 tRPRE Calculation..................................................................................................48
8.13.2.5 tRPST Calculation..................................................................................................48
8.13.2.6 Burst Read Operation followed by a Precharge......................................................54
8.14 WRITE Operation................................................................................................................................56
8.14.1 DDR3 Burst Operation.....................................................................................................56
8.14.2 WRITE Timing Violations.................................................................................................56
8.14.2.1 Motivation...............................................................................................................56
8.14.2.2 Data Setup and Hold Violations..............................................................................56
8.14.2.3 Strobe to Strobe and Strobe to Clock Violations.....................................................56
8.14.2.4 Write Timing Parameters........................................................................................56
8.14.3 Write Data Mask...............................................................................................................57
8.14.4 tWPRE Calculation...........................................................................................................58
8.14.5 tWPST Calculation...........................................................................................................58
8.15 Refresh Command..............................................................................................................................65
8.16 Self-Refresh Operation .......................................................................................................................67
8.17 Power-Down Modes............................................................................................................................69
8.17.1 Power-Down Entry and Exit.............................................................................................69
8.17.2 Power-Down clarifications - Case 1 .................................................................................75
8.17.3 Power-Down clarifications - Case 2 .................................................................................75
8.17.4 Power-Down clarifications - Case 3 .................................................................................76
8.18 ZQ Calibration Commands..................................................................................................................77
8.18.1 ZQ Calibration Description...............................................................................................77
8.18.2 ZQ Calibration Timing......................................................................................................78
8.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading......................................78
8.19 On-Die Termination (ODT)..................................................................................................................79
8.19.1 ODT Mode Register and ODT Truth Table ......................................................................79
8.19.2 Synchronous ODT Mode..................................................................................................80
8.19.2.1 ODT Latency and Posted ODT...............................................................................80
8.19.2.2 Timing Parameters.................................................................................................80
8.19.2.3 ODT during Reads..................................................................................................82
8.19.3 Dynamic ODT ..................................................................................................................83
8.19.3.1 Functional Description:...........................................................................................83
8.19.3.2 ODT Timing Diagrams............................................................................................84
8.19.4 Asynchronous ODT Mode................................................................................................88

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 3 -
8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions..........................................89
8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry..89
8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit.....92
8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods 93
9. OPERATION MODE ...........................................................................................................................94
9.1 Command Truth Table........................................................................................................................94
9.2 CKE Truth Table .................................................................................................................................96
9.3 Simplified State Diagram.....................................................................................................................97
10. ELECTRICAL CHARACTERISTICS...................................................................................................98
10.1 Absolute Maximum Ratings ................................................................................................................98
10.2 Operating Temperature Condition.......................................................................................................98
10.3 DC & AC Operating Conditions...........................................................................................................98
10.3.1 Recommended DC Operating Conditions........................................................................98
10.4 Input and Output Leakage Currents....................................................................................................99
10.5 Interface Test Conditions....................................................................................................................99
10.6 DC and AC Input Measurement Levels.............................................................................................100
10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals..................100
10.6.2 DC and AC Input Levels for Single-Ended Data Signals................................................101
10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)...........103
10.6.4 Single-ended requirements for differential signals .........................................................104
10.6.5 Differential Input Cross Point Voltage ............................................................................105
10.6.6 Slew Rate Definitions for Single-Ended Input Signals....................................................106
10.6.7 Slew Rate Definitions for Differential Input Signals........................................................106
10.7 DC and AC Output Measurement Levels..........................................................................................107
10.7.1 Output Slew Rate Definition and Requirements.............................................................107
10.7.1.1 Single Ended Output Slew Rate...........................................................................108
10.7.1.2 Differential Output Slew Rate ...............................................................................109
10.8 34 ohm Output Driver DC Electrical Characteristics..........................................................................110
10.8.1 Output Driver Temperature and Voltage sensitivity........................................................112
10.9 On-Die Termination (ODT) Levels and Characteristics.....................................................................113
10.9.1 ODT Levels and I-V Characteristics...............................................................................113
10.9.2 ODT DC Electrical Characteristics.................................................................................114
10.9.3 ODT Temperature and Voltage sensitivity .....................................................................114
10.9.4 Design guide lines for RTTPU and RTTPD .......................................................................115
10.10 ODT Timing Definitions............................................................................................................116
10.10.1 Test Load for ODT Timings............................................................................................116
10.10.2 ODT Timing Definitions..................................................................................................116
10.11 Input/Output Capacitance........................................................................................................120
10.12 Overshoot and Undershoot Specifications...............................................................................121
10.12.1 AC Overshoot /Undershoot Specification for Address and Control Pins:.......................121
10.12.2 AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins:.........121
10.13 IDD and IDDQ Specification Parameters and Test Conditions................................................122
10.13.1 IDD and IDDQ Measurement Conditions.......................................................................122
10.13.2 IDD Current Specifications.............................................................................................132
10.14 Clock Specification..................................................................................................................133
10.15 Speed Bins..............................................................................................................................134
10.15.1 DDR3-1333 Speed Bin and Operating Conditions.........................................................134
10.15.2 DDR3-1600 Speed Bin and Operating Conditions.........................................................135
10.15.3 DDR3-1866 Speed Bin and Operating Conditions.........................................................136

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 4 -
10.15.4 Speed Bin General Notes ..............................................................................................137
10.16 AC Characteristics...................................................................................................................138
10.16.1 AC Timing and Operating Condition for -11 speed grade ..............................................138
10.16.2 AC Timing and Operating Condition for -12/12I/-15/15I speed grades ..........................142
10.16.3 Timing Parameter Notes................................................................................................146
10.16.4 Address / Command Setup, Hold and Derating .............................................................149
10.16.5 Data Setup, Hold and Slew Rate Derating.....................................................................156
11. PACKAGE SPECIFICATION ............................................................................................................158
12. REVISION HISTORY........................................................................................................................159

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 5 -
1. GENERAL DESCRIPTION
The W632GG6KB is a 2G bits DDR3 SDRAM, organized as 16,777,216 words 8banks 16 bits.
This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. The W632GG6KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I.
The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12 and 12I speed
grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is
guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -15 and 15I speed grades are compliant to the
DDR3-1333 (9-9-9) specification (the 15I industrial grade which is guaranteed to support -40°C ≤
TCASE ≤ 95°C).
The W632GG6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 6 -
System level timing calibration support via write leveling and MPR read pattern
ZQ Calibration for output driver and ODT using external reference resistor to ground
Asynchronous RESET# pin for Power-up initialization sequence and reset function
Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
Dynamic ODT mode for improved signal integrity and preselectable termination impedances during
writes
2K Byte page size
Interface: SSTL_15
Packaged in WBGA 96 Ball (9x13 mm2), using lead free materials with RoHS compliant
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
OPERATING TEMPERATURE
W632GG6KB-11
DDR3-1866 (13-13-13)
0°C ≤TCASE ≤95°C
W632GG6KB-12
DDR3-1600 (11-11-11)
0°C ≤TCASE ≤95°C
W632GG6KB12I
DDR3-1600 (11-11-11)
-40°C ≤TCASE ≤95°C
W632GG6KB-15
DDR3-1333 (9-9-9)
0°C ≤TCASE ≤95°C
W632GG6KB15I
DDR3-1333 (9-9-9)
-40°C ≤TCASE ≤95°C

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 7 -
4. KEY PARAMETERS
Speed Bin
DDR3-1866
DDR3-1600
DDR3-1333
Unit
CL-nRCD-nRP
13-13-13
11-11-11
9-9-9
Part Number Extension
-11
-12/12I
-15/15I
Parameter
Sym.
Min.
Max.
Min.
Max.
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX

933

800

667
MHz
Internal read command to first data
tAA
13.91
20
13.75
(13.125) *5
20
13.5
(13.125) *5
20
nS
ACT to internal read or write delay time
tRCD
13.91

13.75
(13.125) *5

13.5
(13.125) *5

nS
PRE command period
tRP
13.91

13.75
(13.125) *5

13.5
(13.125) *5

nS
ACT to ACT or REF command period
tRC
47.91

48.75
(48.125) *5

49.5
(49.125) *5

nS
ACT to PRE command period
tRAS
34
9 * tREFI
35
9 * tREFI
36
9 * tREFI
nS
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
2.5
3.3
2.5
3.3
nS
CL = 7
CWL = 6
tCK(AVG)
Reserved
1.875
< 2.5
1.875
< 2.5
nS
CL = 8
CWL = 6
tCK(AVG)
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
nS
CL = 9
CWL = 7
tCK(AVG)
Reserved
1.5
< 1.875
1.5
< 1.875
nS
CL = 10
CWL = 7
tCK(AVG)
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
nS
CL = 11
CWL = 8
tCK(AVG)
Reserved
1.25
< 1.5
Reserved
nS
CL = 13
CWL = 9
tCK(AVG)
1.07
< 1.25
Reserved
Reserved
nS
Supported CL Settings
Sup_CL
6, 8, 10, 13
6, (7), 8, (9), 10, 11
6, (7), 8, 9, 10
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7, 9
5, 6, 7, 8
5, 6, 7
nCK
Average periodic
refresh Interval
-40°C ≤TCASE ≤85°C
tREFI

*2

7.8 *2, 3

7.8 *2, 3
μS
0°C ≤TCASE ≤85°C

7.8 *1

7.8 *1

7.8 *1
μS
85°C < TCASE ≤95°C

3.9 *4

3.9 *4

3.9 *4
μS
Operating One Bank Active-Precharge Current
IDD0

115

105

100
mA
Operating One Bank Active-Read-Precharge
Current
IDD1

140

130

125
mA
Operating Burst Read Current
IDD4R

280

250

235
mA
Operating Burst Write Current
IDD4W

250

220

200
mA
Burst Refresh Current
IDD5B

155

150

145
mA
Self-Refresh Current, TOPER = 0 ~ 85°C
IDD6

19

19

19
mA
Operating Bank Interleave Current
IDD7

400

380

370
mA
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤TCASE ≤85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C ≤TCASE < 0°C is not available.
3. 12I and 15I speed grades support -40°C ≤TCASE ≤85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
5. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings
must be programmed to match. For example, DDR3-1333 (9-9-9) devices supporting down binning to DDR3-1066 (7-7-7)
should program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11)
devices supporting down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for
tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21,
23) also should be programmed accordingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333
(9-9-9) and 48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3-1600 (11-11-11).

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 8 -
5. BALL CONFIGURATION
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
DQU4
M
N
DQSU#
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK#
A10/AP
NC
A12/BC# BA1
VREFCA
ZQ
VDD
VSS
DQL5
VSS
DQL3
VSSQ
VSSQ
DQU2
DQU6
VDDQ VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
DQU7
VSS
DQU1
DMU
DQL0
DQSL
DQSL#
DQL4
RAS#
CAS#
WE#
BA2
A0
A3
BA0
CS#
VDD
VSS
VDDQ
DQL6
DQL2
VSSQ
VDDQ
DQU3
VDD
DQU5
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
P
R
T
A1
A11
NC A8
A6
A4 VSS
VDD
VSS
VSS
VDD
VSS RESET#
A7
A5 A2
A9
A13

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 9 -
6. BALL DESCRIPTION
BALL NUMBER
SYMBOL
TYPE
DESCRIPTION
J7, K7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#.
K9
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates,
internal clock signals and device input buffers and output drivers.
Taking CKE Low provides Precharge Power Down and Self-Refresh
operation (all banks idle), or Active Power Down (row Active in any
bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and
VREFDQ have become stable during the power on and initialization
sequence, they must be maintained during all operations (including
Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are
disabled during power down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
L2
CS#
Input
Chip Select: All commands are masked when CS# is registered HIGH.
CS# provides for external Rank selection on systems with multiple
Ranks. CS# is considered part of the command code.
K1
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR3 SDRAM. When enabled, ODT is
applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU, and DML
signal. The ODT signal will be ignored if Mode Registers MR1 and
MR2 are programmed to disable ODT and during Self Refresh.
J3, K3, L3
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
command being entered.
D3, E7
DMU, DML
Input
Input Data Mask: DMU and DML are the input mask signals control the
lower or upper bytes for write data. Input data is masked when
DMU/DML is sampled HIGH coincident with that input data during a
Write access. DM is sampled on both edges of DQS.
M2, N8, M3
BA0−BA2
Input
Bank Address Inputs: BA0−BA2 define to which bank an Active, Read,
Write, or Precharge command is being applied. Bank address also
determines which mode register is to be accessed during a MRS
cycle.
N3, P7, P3, N2, P8,
P2, R8, R2, T8, R3,
L7, R7, N7, T3
A0−A13
Input
Address Inputs: Provide the row address for Active commands and the
column address for Read/Write commands to select one location out
of the memory array in the respective bank. (A10/AP and A12/BC#
have additional functions; see below). The address inputs also provide
the op-code during Mode Register Set command.
Row address: A0−A13.
Column address: A0−A9.
L7
A10/AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to
determine whether Auto-precharge should be performed to the
accessed bank after the Read/Write operation.
(HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled
during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by bank addresses.
N7
A12/BC#
Input
Burst Chop: A12/BC# is sampled during Read and Write commands to
determine if burst chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See section 9.1
“Command Truth Table”on page 94 for details.
T2
RESET#
Input
Active Low Asynchronous Reset: Reset is active when RESET# is
LOW, and inactive when RESET# is HIGH. RESET# must be HIGH
during normal operation. RESET# is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD, RESET# active is destructive to
data contents.

W632GG6KB
Publication Release Date: Jan. 03, 2017
Revision: A06
- 10 -
E3, F7, F2, F8, H3,
H8, G2, H7
DQL0−DQL7
Input/Output
Data Input/Output: Lower byte of Bi-directional data bus.
D7, C3, C8, C2, A7,
A2, B8, A3
DQU0−DQU7
Input/Output
Data Input/Output: Upper byte of Bi-directional data bus.
F3, G3
DQSL, DQSL#
Input/Output
Lower byte data Strobe: Data Strobe output with read data, input with
write data of DQL[7:0]. Edge-aligned with read data, centered in write
data. DQSL is paired with DQSL# to provide differential pair signaling
to the system during read and write data transfer. DDR3 SDRAM
supports differential data strobe only and does not support single-
ended.
C7, B7
DQSU, DQSU#
Input/Output
Upper byte data Strobe: Data Strobe output with read data, input with
write data of DQU[7:0]. Edge-aligned with read data, centered in write
data. DQSU is paired with DQSU# to provide differential pair signaling
to the system during read and write data transfer. DDR3 SDRAM
supports differential data strobe only and does not support single-
ended.
B2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
Supply
Power Supply: 1.5V ± 0.075V.
A9, B3, E1, G8, J2,
J8, M1, M9, P1, P9,
T1, T9
VSS
Supply
Ground.
A1, A8, C1, C9, D2,
E9, F1, H2, H9
VDDQ
Supply
DQ Power Supply: 1.5V ± 0.075V.
B1, B9, D1, D8, E2,
E8, F9, G1, G9
VSSQ
Supply
DQ Ground.
H1
VREFDQ
Supply
Reference voltage for DQ.
M8
VREFCA
Supply
Reference voltage for Control, Command and Address inputs.
L8
ZQ
Supply
External reference ball for output drive and On-Die Termination
Impedance calibration: This ball needs an external 240 Ω± 1%
external resistor (RZQ), connected from this ball to ground to perform
ZQ calibration.
J1, J9, L1, L9, M7,
T7
NC
No Connect: No internal electrical connection is present.
Note:
Input only balls (BA0-BA2, A0-A13, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.