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Section 3
Technical description
Refer to the circuit diagram WD1660 at the rear of this manual.
3.1 POWER SUPPLY
DC power is connected to the transmitter module via PL2. It is fed directly to regulator IC1.
This provides a stable output of nominally +5V which is used to power all the remaining
sections of the receiver either directly or via R-C decoupling networks. The 5V output from
IC1 is also available at PL3 for the powering of external equipment with a current
requirement of up to 50mA.
3.2 RF FRONT END & MIXER
The antenna is connected via PL3. The signal passes directly into helical filter F2 which is
tuned for the required frequency range. The use of a filter prior to the RF amplifier
provides a high level of immunity from overloading by strong out-of-band signals. The
signal then passes to a low noise RF amplifier, a bipolar design based around TR3. This
circuit is run at relatively high current in order to minimise the possibility of overloading by
strong signals, but to reduce overall current consumption it is “voltage stacked” with the
synthesiser and VCO in a current sharing arrangement. Thus only ~2V of the 5V supply is
dropped across the front end device. After the RF amplifier, the signal passes through a
second tuned helical filter F4. Along with F2, this provides sufficient selectivity to give
image rejection in excess of 70dB.
The signal then passes to TR1, a dual gate MOSFET which acts as the first mixer.
3.3 VCO & SYNTHESISER
A WD1647 VCO module (U1) is used to generate the first LO. This module is pre-tested
prior to assembly if the SR500 and provides an output of ~1mW at a frequency 45MHz
lower than the wanted frequency. The VCO is locked onto frequency by a PLL frequency
synthesiser based around IC4. X2, a 12.8 MHz TCXO oscillator provides a frequency
reference for the synthesiser. This is stable to better than 2.5ppm over the operating
temperature range.
The synthesiser is serially programmed by IC6, a PIC microcontroller. D2/C24 are used to
provide an out of lock indication from the synthesiser’s LD line. This is input to IC6 to
allow synthesiser reprogramming when an out of lock condition is detected. This has
been included to protect against malfunction of the unit due to corruption of the data held
in the synthesiser (for example during a power supply “brown-out”). The microcontroller
includes an internal EEPROM memory which is used to store operating frequency
information.
