Xerox Dove Product manual

XEROX
Dove lOP Board
Technical Reference Manual
Version 1.2
July 1987

Dove lOP Board Technical Reference Manual
Xerox Corporation
Document Systems Business Unit
Processor Development
475 Oakmead Parkway
Sunnyvale, California 94086

Information contained in this manual is subject to change without
notice.
For this printing, speaker information was added. A revision history
at the back of this publication lists all pages changed since the First
Edition.
The last page of this publication is a Reader Comment form.
Comments are welcome and become the property of Xerox
Corporation.
This publication was produced using ViewPoint on a 6085
Professional Computer System, printed on a Xerox 8040 RAVEN laser
printer, and reproduced on a Xerox 9900 High Speed Copier.
Copyright
co Xerox Corporation 1985, 1986, and 1987.
XEROX @ , ViewPoint, 6085, 8040, and 9900 are trademarks of
XEROX CORPORATION.
No part of this publication may be reproduced or translated, stored in
a database or retrieval system, or transmitted in any form or by any
means, electronic, mechanical, photocopying, recording, or otherwise,
except
as expressly permitted by Xerox Corporation.
Printed in the United States of America .

P.I Purpose
P.2 Audience
p.a Organization
P.4 References
Preface
The lOP Technical Reference Manual describes the hardware on the
Dove lOP board. The manual describes the theory of operation of the
components, and presents information important for programmer
interface.
The following groups are expected to refer to this publication:
Engineers
Systemdesigners
Microprogrammers
Field Service personnel
Mter a brief overview, each major part of the lOP board is discussed in
a separate section. Components' are described as to hardware, theory
ofoperations, and programmer interface.
Hardware describes pins and signals of the component.
Theory of Operations describes system operating modes, which may
include timing.
Programmer Interface describes register assignments and timing.
An addendum describes the speaker.
Appendices contain
supplementary information about the board and
components. Because this manual corresponds to B2 and later builds
ofmachines,
earlier machines will have some differences. Appendix C
lists the documentation that describes the various issued lOPs found
in the Dove machines. Appendix D, reprinted in a separate volume,
contains a representative set of schematics.
The following documents contain supplementary information.
AMD 2942 Specification Sheet. Bipolar Microprocessor
Logic
and Interface 1985 Data Book, Advanced Micro
Devices, Sunnyvale, CA

Dove lOP Board
Application Note 8-A SinglelDouble Density Floppy Disk
Controller using the PD765, NEC Microcomputers, Inc.
Daisy System Requirements Specification. Xerox Office
Systems Division, 1983.
Data Catalog- Specification sheet on the FDC 9229 chip,
Standard Microsystems Corporation.
LAN
Components User 's Manual, Intel Corporation-
1984.
MCC Manchester Code Converter 8023A Data Sheet.
SeeqTechnology Incorporated, 1985.
Memory Components. 512 x 9
BiPort Parallel In-Out
FIFO, United Technologies Mostek.
Microsystems Component Handbook Volumes I
and II,
Intel Corporation -1984.
Specification sheet on the 8x305 microcontroller.
Signetics Corporation.

TABLE OF CONTENTS
1. lOP Board
1.1 Overview
1.2 Hardware
1.2.1 Printed wiring board assemblies (PWBA)
l.2.2 Interfaces to backplane
l.2.3 Power
2. 110 Processor and Related Components
2.1 Hardware
2.1.1 Chip and chip socket
2.l.2 Pin assignments and description
2.2 Theory of Operations
2.2.1 Execution unit
2.2.2 Integrated DMA unit
2.2.3 Integrated timer unit
2.2.4 Integrated interrupt controller
2.2.5 Clock
generator
2.2.6 Chip select unit
2.2.7 Integrated peripheral accessing
2.3 Programmer Interface
2.3.1 Processor
reset and initialization
2.3.1.1 Local bus controller and reset
2.3.l.2 Chip select/ready logic and reset
2.3.l.3 DMA channels and reset
2.3.l.4 Interrupt controller and reset
2.3.l.5 Timers and reset
2.3.2 Chip select address and register bit maps
Table of Contents
1-1
1-3
1-3
1-6
1-8
2-2
2-2
2-3
2-7
2-7
2-8
2-9
2-10
2-10
2-10
2-11
2-12
2-12
2-12
2-13
2-13
2-13
2-13
2-14

Dove lOP Board
3. lOP Memory and Interrupt Controllers
3.1 lOP Memory
3.l.1 Memory addressing
3.l.2 Memory mapping
3.2 Interrupts
3.2.1 Hardware
3.2.2. Theory of operations
3.2.2.1 Master interrupt controller
3.2.2.2 Slave interrupt controllers
3.2.3
Programmer interface
3.2.3.1 Reg~sters
3.2.3.2 Timing
4. Bus Arbiter and Mode Control
4.1 Hardware
4.2 Theory of Operations
4.2.1 Ethernet and rigid disk combinations
4.2.2 lOP, PCE, Ethernet, and rigid disk combinations
4.2.3 Arbiter flow diagrams
5. Rigid Disk Subsystem
Subsystem architecture
S~bsystem programming overview
5.1 Rigid Disk Drive
5.l.1 Hardware
5.l.2 Theory/Programmer interface
5.2 Rigid Disk Controller
5.2.1 Hardware
5.2.2. Theory of operations
5.2.2.1 Command/status registers
5.2.2.2 Scratch pad and local memory
5.2.2.3 Drive status and drive control registers
5.2.2.4 Microcontroller data paths
5.2.2.5 Write logic data path
5.2.2.6 Read logic data path
5.2.2.7 Reading and writing the DMA and FIFO
ii
3-1
3-1
3-2
3-2
3-2
3-4
3-4
3-5
3-7
3-7
3-11
4-2
4-3
4-4
4-9
4-15
5-1
5-2
5-7
5-7
5-7
5-8
5-9
5-11
5-12
5-12
5-12
5-12
5-13
5-14
5-15
Table of Contents

Dove lOP Board
5.2.3
Programmer interface 5-16
5.2.3.1
Registers 5-16
5.2.3.2
Timing
5-19
5.3 DMA
Controller 5-21
5.3.1
Hardware 5-22
5.3.1.1
DMA signals 5-22
5.3.1.2 DMA
as a peripheral for lOP 80186 5-24
5.3.2
Theory of operations
5-25
5.3.2.1 DMA
state machine 5-25
5.3.2.2
States of the state machine
5-26
5.3.2.3 Ope,rating
sequence 5-29
5.3.2.4
State machine timing
5-31
5.3.2.5
Wait states for slower memories 5-41
5.3.3
Programmer interface
5-45
5.3.3.1 Address
register
5-46
5.3.3.2 Word
count
5-47
5.3.3.3 Control
register on AM2942 chip
5-47
5.3.3.4 DMA
command register
5-48
5.3.3.5 DMA
status register
5-48
5.3.3.6
Programming DMA transfers 5-49
5.4 Rigid Disk
FIFO
5-51
5.4.1
Hardware
5-52
5.4.2
Theory of operations
5-52
5.4.3
Programmer interface 5-53
6. Ethernet Controller
6.1 Overview
6-1
6.1.1
Controller functional blocks 6-2
6.1.2
Controller relationship to standards
6-3
6.2
Hardware
6-3
6.3
Theory of Operations 6-9
6.3.1
Interfaces
6-9
6.3.1.1
Communicating with the transceiver
6-9
6.3.1.2
Communicating with the SIA and DLC 6-10
6.3.1.3 Communicating with the lOP
6-11
6.3.1.4
Communicating with the lOP bus
6-12
Table of Contents
iii

Dove lOP Board
6.3.2 Processes
leading to data transmission and reception
6-14
6.3.2.1 Initialization
6-14
6.3.2.2 Successful boot 6-15
6.3.3
Data transmission and net management
6-15
6.3.3.1 Transmission
6-16
6.3.3.2 Network management
6-17
6.3.4
Data reception 6-19
6.3.4.1 Initializing
6-19
6.3.4.2 Receiving a frame 6-19
6.3.5 Diagnostics 6-21
6.3.5.1 Hardware diagnostics 6-22
6.3.5.2 Software diagnostics 6-22
7.
Floppy Disk Subsystem
7.1 Hardware
7-2
7.1.1 Floppy
disk drives 7-2
7.1.2 Diskettes
7-2
7.1.3 Floppy disk
controller 7-3
7.l.3.1
Controller interface 7-3
7.1.3.2 Data separator 7-6
7.2 Theory
of Operations 7-8
7.2.1 Floppy disk controller 7-9
7.2.2 Data separator 7-9
7.2.3 80186 processor (DMA
and timer)
7-9
7.2.4
Interrupt controllers
7-10
7.2.5 Control
register
7-10
7.2.6 Buses 7-10
7.3
Programmer Interface 7-10
7.3.1 Registers 7-10
7.3.1.1 Floppy disk controller registers
7-11
7.3.1.2 DMA
registers
7-13
7.3.1.3
Timer registers
7-14
7.3.1.4
lOP control registers
7-14
7.3.2
Interrupts
7-16
7.3.3 Reset 7-16
7.3.4 Diskette
format
7-16
iv
Table of Contents

Dove lOP Board
7.3.4.1 Preambles and postambles 7-17
7.3.4.2 Sectors 7-18
8. RS232C
Controller
8.1
Hardware 8-1
8.1.1 Serial controller
8-1
8.1.1.1 Controller
8-2
8.1.1.2 Timer
8-4
8.1.2 Interfaces 8-6
8.1.2.1 System interface signals 8-6
8.1.2.2 8274 interface ports 8-7
8.1.2.3 Interface connectors 8-9
8.1.3 Serial channels 8-10
8.2 Theory
of Operations
8-11
8.3
Programmer Interface: Registers 8-12
8.3.1
External registers 8-12
8.3.2 8274
serial controller registers 8-13
8.3.2.1
Write registers 8-13
8.3.2.2 Read registers 8-17
8.3.3 8254
timer registers 8-18
9.
Keyboard/Mouse Controller and Maintenance Panel
9.1
Hardware
9-1
9.2 Theory
of Operations/Programmer Interface 9-2
9.2.1 Keyboard
and mouse interface 9-2
9.2.2 Registers
9-3
9.2.2.1
Command registers
9-3
9.2.2.2 Status registers 9-5
9.2.3 Maintenance panel 9-6
9.2.3.1
Normal commands 9-7
9.2.3.2 Special commands 9-7
10.
Debugger Interface
10.1 Hardware
10-1
10.1.1 Interface connector 10-3
10.1.2
Programmable peripheral interface (PP[) 10-4
10.1.3 Line
drivers 10-4
Table of Contents
v