XESS XSV User manual

RELEASE DATE: 9/11/1999
XSV Board V0.1 ManualXSV Board V0.1 Manual
How to install and use
your new XSV Board
2608 Sweetgum Drive
Apex NC 27502
Toll-free: 800-549-9377
International: 919-387-0076
FAX: [phone]

RELEASE DATE: 9/11/1999
Copyright ©1998-1999 by X Engineering Software Systems Corporation.
All XS-prefix product designations are trademarks of XESS Corp.
All XC-prefix product designations are trademarks of Xilinx.
ABEL is a trademark of DATA I/O Corporation.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
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Printed in the United States of America.
Limited Warranty
X Engineering Software Systems Corp. (XESS) warrants that the Product, in the course of
its normal use, will be free from defects in material and workmanship for a period of one
(1) year and will conform to XESS’s specification therefor. This limited warranty shall
commence on the date appearing on your purchase receipt.
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before XESS receives the Product, or c) is attributable to misuse, improper installation,
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Table of ContentsTable of Contents
Limited Warranty ......................................................................................1
Preliminaries ...................................................................................................4
Getting Help! ............................................................................................4
Packing List..............................................................................................4
XSV Overview.................................................................................................5
XSV Board Features ................................................................................5
Installation.......................................................................................................8
Unpacking the Board................................................................................8
Configuring the Jumpers ..........................................................................8
Applying Power ........................................................................................8
Connecting to a PC..................................................................................8
Setting the Oscillator Frequency...............................................................8
Programming the Interface.....................................................................10
Downloading Virtex Configuration Bitstreams ........................................10
XSV Circuitry.................................................................................................11
Programmable logic: XCV50-XCV800 Virtex FPGA and XC95108 CPLD11
100 MHz programmable oscillator..........................................................11
16 Mbit Flash RAM.................................................................................12
SRAM Banks..........................................................................................14
Video Decoder........................................................................................15
RAMDAC and VGA Monitor Interface....................................................16
Stereo Codec .........................................................................................18
Ethernet PHY .........................................................................................18
Expansion Headers................................................................................21
Pushbuttons and Eight-Position DIP Switch...........................................23

3
Digit and Bargraph LEDs........................................................................24
PS/2 Port................................................................................................26
Dual USB Port........................................................................................26
Parallel Port............................................................................................27
Serial Port...............................................................................................29
Xchecker Cable......................................................................................29
Power Connectors..................................................................................30
XSV Pin Connections....................................................................................31
XSV Schematics...........................................................................................33

1
Preliminaries
Getting Help!
If you follow the instructions in this manual and you encounter problems, here are some
places to get help:
nIf you can't get the XStend Board hardware to work, send an e-mail message
describing your problem to [email protected] or check our web site at
http://www.xess.com.
nIf you can't get your XILINX software tools installed properly, send an e-mail message
describing your problem to [email protected] or check their web site at
http://support.xilinx.com.
Packing List
Here is what you should have received in your package:
nan XSV Board;
na 6-foot, 25-wire cable with a male DB25 connector at each end;
na 3.5" floppy diskette or CDROM with documentation on the XSV Board.

5
2
XSV Overview
The XSV Board brings you the power of the XILINX Virtex FPGA embedded in a
framework for processing video and audio signals. The XSV Board accepts Virtex FPGAs
from 50K to 800K gates in size. The XSV can digitize PAL, SECAM, or NTSC video with
up to 9-bits of resolution on the red, green, and blue channels and can output video
images through a 110 MHz, 24-bit RAMDAC. The FPGA can also process stereo audio
signals with up to 20 bits of resolution and a bandwidth of 50 KHz. Two independent
banks of 512K x 16 SRAM are provided for local buffering of signals and data.
The XSV Board has a variety of interfaces for communicating with the outside world:
parallel and serial ports, Xchecker cable, dual USB ports, PS/2 mouse and keyboard port,
and 10/100 Ethernet PHY layer interface. There are also two independent expansion
ports, each with 38 general-purpose I/O pins connected directly to the Virtex FPGA.
You can configure the XSV Board through a PC parallel port, serial port, Xchecker cable
or from a bitstream stored in the 16 Mbit Flash RAM. The Flash RAM can also store data
for use by the FPGA after configuration is complete.
XSV Board Features
The XSV Board includes the following resources:
nProgrammable logic chips:
XILINX Virtex FPGA: Virtex FPGAs from 57 Kgates (XCV50) up to 888 Kgates
(XCV800) are compatible with the XSV Board. The Virtex FPGA is the main
repository of programmable logic on the XSV Board.
XILINX XC95108 CPLD: The CPLD is used to manage the configuration of the
Virtex FPGA via the parallel port, serial port, or Flash RAM. The CPLD also
controls the configuration of the Ethernet PHY chip.
nProgrammable oscillator that provides a clock signal to the FPGA and CPLD derived
form a 100 MHz base frequency.
n16 Mbit Flash RAM that can store multiple configurations or general-purpose data for
the FPGA.
nTwo independent 512K x 16 SRAM banks used by the FPGA for general-purpose
data storage.
nVideo decoder that accepts NTSC/PAL/SECAM signals through an RCA jack or S-
video connector and outputs the digitized signal to the FPGA.

6
nRAMDAC with a 256-entry, 24-bit colormap that is used by the FPGA to output video
to a VGA monitor.
nStereo codec that lets the FPGA digitize and generate 0-50 KHz audio signals with up
to 20 bits of resolution.
n10BASE-T/100BASE-TX Ethernet PHY that allows the FPGA to access a LAN at up
to 100 Mbps.
nTwo expansion headers interface the FPGA to external circuitry through 76 general-
purpose I/Os.
nFour pushbuttons and one eight-position DIP switch provide general-purpose inputs to
the FPGA and CPLD.
nTwo LED digits and one LED bargraph let the FPGA and CPLD display status
information.
nMouse/keyboard PS/2 port gives the FPGA access to common PC input devices.
nDual USB port provides the FPGA with two independent serial I/O channels with
bandwidths of 1.5 to 12 Mbps.
nParallel/serial port interfaces let the CPLD send and receive data in a parallel or serial
format similar to a PC.
nXchecker cable interface allows downloading and readback of the FPGA
configuration.
nATX power connector or 9 VDC power jack lets the XSV Board receive power from a
standard ATX power supply or a 9 VDC power supply.
The location of these resources are indicated in the simplified view of the XSV Board
shown below. Each of these resources will be described in the following section.

7

8
3
Installation
Unpacking the Board
You should place the XSV Board on a non-conducting surface.
Configuring the Jumpers
Place shunts on jumpers J23 and J24.
Applying Power
You can supply the XSV Board with power in two ways:
1. Attach an ATX PC power supply to connector J11.
2. Attach a 9 VDC power supply with a 2.1mm, center-positive plug to jack J12. The
power supply must be able to source at least 1A.
LED D2 will glow when the power is on.
Connecting to a PC
One DB25 connector on the 6-foot cable should be attached to connector J10 on the XSV
Board and the other end should plug into the parallel port connector of a PC.
Setting the Oscillator Frequency
The XSV Board has a programmable oscillator which provides a clock signal to the FPGA
and CPLD. The oscillator has an internal 100 MHZ frequency source that is scaled by a
divisor between 1 and 2048 to generate the clock signal for the rest of the XSV Board.
The divisor is stored in non-volatile memory in the oscillator chip so it will be restored each
time power is applied to the XSV Board.
The divisor is set as follows:
qRemove power from the XSV Board.

9
qRemove the cable to the parallel port connector.
qPlace shunts on jumpers J23 and J24.
qRestore power to the XSV Board.
qReconnect the cable to the PC parallel port.
qEnter the following command in a DOS window:
XSSETCLK DIVISOR
where DIVISOR is replaced by the actual numeric divisor you wish to program into
the DS1075. This command will configure the XC95108 CPLD so it can program the
oscillator, and then it will program the oscillator frequency.
qWait for the oscillator programming to complete.
qRemove power and the parallel port cable from the XSV Board.
qRemove the shunt on jumper J24.
qRestore power and the parallel port cable to the XSV Board. The clock frequency
should now be 100 MHz ÷ DIVISOR.
You can substitute an external clock source for the internal oscillator. Follow these steps
to configure the programmable oscillator for operation with an external clock source:
qRemove power from the XSV Board.
qRemove the cable to the parallel port connector.
qPlace shunts on jumpers J23 and J24.
qRestore power to the XSV Board.
qReconnect the cable to the PC parallel port.
qEnter the following command in a DOS window:
XSSETCLK DIVISOR -EXTERNAL
where DIVISOR is replaced by the actual numeric divisor you wish to program into
the DS1075 and -EXTERNAL instructs the command to disconnect the internal
oscillator of the DS1075.
qWait for the oscillator programming to complete.
qRemove power and the parallel port cable from the XSV Board.
qRemove the shunt on jumper J24.
qRestore power and the parallel port cable to the XSV Board.

10
qConnect your external frequency source to connector J27. The clock frequency sent
to the CPLD and FPGA should now be external frequency ÷ DIVISOR.
Programming the Interface
The Virtex FPGA is the main repository of programmable logic on the XSV Board. The
CPLD manages the configuration of the FPGA via the parallel or serial ports or from the
Flash memory. Therefore, the CPLD must be configured so that it implements the
necessary interface. The CPLD stores its configuration in its internal non-volatile memory
so the interface is restored each time power is applied to the XSV Board.
The CPLD is configured with an interface as follows:
qRemove power from the XSV Board.
qRemove the cable to the parallel port connector.
qPlace a shunt on jumper J23.
qRestore power to the XSV Board.
qReconnect the cable to the PC parallel port.
qEnter the following command in a DOS window if you want to program the XSV Board
through the PC parallel port:
XSINTFC PARALLEL
(The serial and Flash memory interfaces are not currently implemented.)
qWait for the interface programming to complete.
qRemove power and the parallel port cable from the XSV Board.
qRemove the shunt on jumper J24.
qRestore power and the parallel port cable to the XSV Board.
Now you can download Virtex configuration files into the FPGA of the XSV Board.
Downloading Virtex Configuration Bitstreams
Once the CPLD is programmed with the downloading interface circuit, you can download
bitstreams into the Virtex FPGA using the command:
XSLOAD FILE.BIT
where FILE.BIT is a configuration bitstream generated by the Xilinx implementation tools
for the particular type of Virtex FPGA on your XSV Board.

11
4
XSV Circuitry
This section describes the various sections of the XSV Board and shows how the I/O of
the FPGA and CPLD are connected to the rest of the circuitry. The schematics which
follow are less detailed so as to simplify the descriptions. Please refer to the complete
schematics at the end of this document if you need more details.
Programmable logic: XCV50-XCV800 Virtex FPGA and XC95108 CPLD
The XSV Board contains two programmable logic chips:
nA XILINX Virtex FPGA in a 240-pin QFP package. Virtex FPGAs from 57 Kgates
(XCV50) up to 888 Kgates (XCV800) are compatible with the XSV Board. The Virtex
FPGA is the main repository of programmable logic on the XSV Board.
nA XILINX XC95108 CPLD which is used to manage the configuration of the Virtex
FPGA via the parallel port, serial port, or Flash RAM. The CPLD also controls the
configuration of the Ethernet PHY chip.
100 MHz programmable oscillator
A Dallas DS1075 programmable oscillator provides a clock signal to both the FPGA and
the CPLD. The DS1075 has a maximum frequency of 100 MHz which can be divided to
provide frequencies of 100 MHz, 50 MHz, 33.3 MHz, 25 MHz, ..., 48.7 KHz. The clock
signal is connected to dedicated clock inputs of both the CPLD and FPGA as follows:
DS1075
Output Virtex FPGA Pin XC95108 CPLD Pin
CLK 89 22
To set the divisor value, the DS1075 must be placed in its programming mode. This is
done by pulling the clock output to Vcc on power-up with a shunt on jumper J24. Then
programming commands to set the divisor can be sent to the DS1075 by either the CPLD
or FPGA. The divisor is stored in EEPROM in the DS1075 so it will be restored whenever
power is applied to the XSV Board.
To get a precise frequency value or to sync the XSV circuitry with an external system, you
can insert an external clock signal through connector J27. This external clock replaces the
100 MHz internal oscillator of the DS1075. The clock source is stored in EEPROM so the
DS1075 must be specifically programmed to enable or disable this option.

12
16 Mbit Flash RAM
An Intel 28F016S5 Flash RAM with 16 Mbits of storage (2M ×8) is connected to both the
Virtex FPGA and XC95108 CPLD as follows:
The CPLD and FPGA both have access to the Flash RAM. Typically, the CPLD will
program the Flash with data passed through the parallel or serial port. If the data is an
FPGA configuration bitstream then the CPLD can be configured to program the FPGA
with the Flash bitstream whenever the XSV Board is powered up. After power-up, the
FPGA can read and/or write the Flash. (Of course, the CPLD and FPGA have to be
programmed such that they do not conflict if both are trying to access the Flash.) The
Flash can be disabled by raising the /CE pin to Vcc in which case the I/O lines connected
to the Flash can be used for general-purpose communication between the FPGA and the
CPLD.
The pins of the FPGA and CPLD connected to the Flash RAM are listed below:
16 Mbit
Flash RAM
XC95108
CPLD
Virtex
FPGA
21
8d0-7
a0-20
reset
rdy
we
oe
ce
XC95108
CPLDVirtex FPGA
DS1075
J24
External
Clock
J27

13
Flash RAM
Pin Virtex FPGA Pin XC95108 CPLD Pin
/RESET N/A 3
/CE 170 46
/OE 173 42
/WE 131 43
RDY 171 41
D0 177 32
D1 167 33
D2 163 34
D3 156 35
D4 145 36
D5 138 37
D6 134 39
D7 124 40
A0 132 16
A1 133 17
A2 139 18
A3 141 19
A4 144 20
A5 147 23
A6 152 24
A7 154 25
A8 157 27
A9 160 28
A10 162 29
A11 169 30
A12 168 49
A13 161 50
A14 159 52
A15 155 53
A16 153 54
A17 149 55
A18 146 56
A19 142 58
A20 140 59

14
SRAM Banks
The FPGA has access to two independent banks of SRAM as shown below: Each SRAM
bank is organized as 512K ×16 bits. The FPGA pins connected to the SRAM banks are
shown in the accompanying table.
SRAM Pin Virtex
FPGA Pin
to Left
Bank
Virtex
FPGA Pin
to Right
Bank
/CE 186 109
/OE 228 95
/WE 201 68
D0 202 70
D1 203 71
D2 205 72
D3 206 73
D4 207 74
D5 208 78
D6 209 79
D7 215 80
D8 216 81
D9 217 82
D10 218 84
D11 220 85
D12 221 86
D13 222 87
D14 223 93
D15 224 94
A0 200 67
Virtex
FPGA
19
8
8
4 Mbit
SRAM
4 Mbit
SRAM
we
we
oe
oe
ce
ce
19
8
8
4 Mbit
SRAM
d
0-7
a
0-18
4 Mbit
SRAM
a
0-18
a
0
-
1
8
a
0
-
1
8
d
0-7
d
0
-
7
d
0
-
7
we
we
oe
oe
ce
ce

15
SRAM Pin Virtex
FPGA Pin
to Left
Bank
Virtex
FPGA Pin
to Right
Bank
A1 199 66
A2 195 65
A3 194 64
A4 193 63
A5 192 57
A6 191 56
A7 189 55
A8 188 54
A9 187 53
A10 238 108
A11 237 107
A12 236 103
A13 235 102
A14 234 101
A15 232 100
A16 231 99
A17 230 97
A18 229 96
Video Decoder
The XSV Board can digitize NTSC, SECAM, and PAL video signals using the SAA7113
video decoder. The digitized video arrives at the FPGA over the VPO bus. The arrival of
video data is synchronized with the rising edge of the LLC (line-locked clock) from the
video decoder. The FPGA programs the video options of the SAA7113 using the I2C bus
(SCL and SDA).
SAA7113
Pin Virtex FPGA Pin
LLC 92
RTS0 111
RTS1 110
RTCO 113
SAA7113
Video
Decoder
Virtex
FPGA
sda
vpo
0-7ai11 luma S-Video
Connector
(J8)
RCA Jack
(J9)
chroma
cvbs
llc
scl
rts0 ai12
rts1
ai21
rtco
ai22
8

16
SAA7113
Pin Virtex FPGA Pin
VPO0 116
VPO1 117
VPO2 118
VPO3 125
VPO4 126
VPO5 127
VPO6 128
VPO7 130
SCL 114
SDA 115
RAMDAC and VGA Monitor Interface
The FPGA can generate a video signal for display on a VGA monitor either directly or
using a RAMDAC depending upon the arrangement of the shunts on jumpers J5, J6, and
J7.
When the FPGA is directly generating VGA signals, the lower six bits of the P bus provide
two-bits of red, green, and blue color information to a simple resistor-ladder DAC. The
outputs of the DAC are sent to a VGA monitor along with the horizontal and vertical sync
pulses (/HSYNC, /VSYNC) from the FPGA.
When the RAMDAC generates the VGA color signals, then the FPGA uses the full eight-
bit P bus to pass the index of the color for the current pixel. The index is used to lookup
the 24-bit color value (eight bits for the red, green, and blue components) stored in the
256-entry colormap of the RAMDAC chip. The transfers over the P bus are synchronized
Virtex
FPGA
J5
J6
J7
BT481A
RAMDAC
d
0-7
p
0-7
r
0p
0
p
5
p
4
p
3
p
2
p
1r
1g 0g 1b 0b 1
redred
hsync
vsync
wr
rs
0-2
blank
green
green
pixelclk
blue blue
rd
8
8
VGA
Connector
(J4)

17
with the PIXELCLK generated by the FPGA. The FPGA lowers the /BLANK signal when
the pixels fall outside the desired visible area of the monitor screen.
The colormap of the RAMDAC is initialized by the FPGA using the D bus along with the
RS, /WR, and /RD signals. The 24-bit colormap entries are passed in groups of three
bytes over the eight-bit D bus synchronized by the /WR signal. The register-select signals
(RS0, RS1, RS2) select the staging register for writing the colormap. The contents of the
staging register are written into the colormap after the last byte of color information arrives
over the D bus, and then the internal colormap address is incremented to point to the next
entry.
The shunt placement to enable the FPGA to generate VGA signals directly or through the
RAMDAC is shown below.
J7J7J5J5J6J6
Direct VGA
Shunt SettingRAMDAC Shunt Setting
The pin assignments for the connection of the FPGA to the VGA signal generation circuitry
are shown below. Note that the FPGA shares some connections between the RAMDAC
and the chip which interfaces to the Ethernet (LXT970A). The RAMDAC pins are used to
load the colormap and should not be active except during system initialization. The other
connections are used for Ethernet data transmission and reception and are usually only
active after system initialization.
Direct
VGA Pin RAMDAC Pin Virtex FPGA Pin LXT970A Function
PIXELCLK 52
/HSYNC /HSYNC 48
/VSYNC /VSYNC 49
/BLANK 50
RED0 P0 70
RED1 P1 71
GREEN0 P2 72
GREEN1 P3 73
BLUE0 P4 74
BLUE1 P5 78
P6 79
P7 80
/RD 47
/WR 46
RS0 31 TXD4
RS1 28 RX_ER
RS2 26 RX_DV
D0 42 TXD0
D1 41 TXD1

18
Direct
VGA Pin RAMDAC Pin Virtex FPGA Pin LXT970A Function
D2 40 TXD2
D3 39 TXD3
D4 38 RXD0
D5 36 RXD1
D6 35 RXD2
D7 34 RXD3
Stereo Codec
The XSV Board has a stereo codec that accepts two analog input channels from jack J1,
digitizes the analog values, and sends the digital values to the FPGA as a serial bit
stream. The codec also accepts a serial bit stream from the XS Board and converts it into
two analog output signals, which exit the XSV Board through jack J2. The serial bit
streams are synchronized with a clock from the FPGA that enters the codec on SCLK
signal. The FPGA uses the LRCK signal to select the left or right channel as the
source/destination of the serial data. The master clock from the FPGA (MCLK)
synchronizes all the internal operations of the codec.
The FPGA pins which connect to the codec are as follows:
Stereo
Codec Pin Virtex FPGA Pin
MCLK 3
LRCK 4
SCLK 5
SDIN 6
SDOUT 7
Ethernet PHY
The XSV Board interfaces to an Ethernet LAN at 10 or 100 Mbps. The Ethernet PHY chip
connects to both the FPGA and the CPLD. The FPGA acts as a MAC (media access
controller) and manages the transfer of data packets to and from the PHY chip, while the
CPLD controls the configuration pins that determine the operational mode of the PHY
chip.
Virtex
FPGAAK4520A Codec
mclkinleft
sdout
lrck inrig h t
sclk outleft
outright
sdin
Stereo Jack
(J1)
Stereo Jack
(J2)
Amp

19
The FPGA enables the transmitter with TX_EN and sends bits on TXD4-0 in sync with the
transmit clock (TX_CLK) generated by the PHY chip. The PHY chip is alerted to
transmission errors that occur in the MAC when the TX_ERR signal is asserted. The
FPGA also receives an indication when valid data has been received (RX_DV) and the
data (RXD0-4) in sync with the receiver clock (RX_CLK) from the PHY chip. Any reception
errors are indicated to the FPGA via the RX_ER signal. The CRS signal indicates when
the receiver is non-idle. The COL signal is asserted when data collides on the Ethernet.
The FPGA can disable the interface to the PHY chip by asserting the tristate control
(TRSTE). Otherwise, the FPGA passes management information to and from the PHY
chip over the serial data line (MDIO) in sync with a clock (MDC). the FPGA can be alerted
to changes in PHY chip status by the FDS/MDINT interrupt line.
The CPLD sets the static values on pins which control the configuration of the PHY chip.
Pins MF0-4 set the modes for auto-negotiation, repeating, symbol transmission,
scrambling, etc. Likewise, the configurations signals (CFG0-1) select the 10 Mbps or 100
Mbps operating speed of the PHY chip. MDDIS enables/disables the management
information interface. FDE selects either full-duplex or half-duplex communication mode.
The reset (/RESET) and power-down (PWRDWN) signals do exactly what they say.
The CPLD also gets receives the status outputs from the PHY chip that normally drive
LEDs. The outputs are active-low and indicate when 100 Mbps operation is selected
(/LEDS), the receiver is active (/LEDR), the transmitter is active (/LEDT), the link is active
(/LEDL), and a collision is detected (/LEDC). The CPLD can relay these signals to the
LEDs on the XSV Board if you wish to display the Ethernet status.
XC95108
CPLD
LXT970A
Ethernet
PHY
Virtex
FPGA
mf
0-4
cfg
0-1
mddis
tpop
tpip
tpon
tpin
mdc
fds/mdint
trste
crs
col
rxd0-4
rx_dv
mdio
rx_clk
rx_er
txd0-4
tx_en
tx_clk
tx_err
fde
pwrdwn
leds
ledr
ledt
ledl
ledc
reset
4
4
4
2
RJ45
Connector
(J3)
transformer