Xilinx Spartan-6 FPGA Series User manual

Spartan-6 FPGA
Power Management
User Guide
UG394 (v1.1) September 4, 2012

Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are
subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be
subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be
fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical
Applications: http://www.xilinx.com/warranty.htm#critapps.
© Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, Vivado, and other designated brands
included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective
owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
05/18/10 1.0 Initial Xilinx release.
09/04/12 1.1 • Updated Additional Documentation section.
•InChapter 1, deleted first and last paragraphs from Differential I/O Standards.
Eliminated statements pertaining to differential drivers and receivers disabled in
suspend mode. Reinforced the directive that the SUSPEND pin must be tied to GND
when the suspend feature is disabled by adding “or High” to second paragraph of
SUSPEND Pin. Changed “X” to “0” in first row of Table 1-5. Changed the AWAKE
output pin power supply to VCCO power rail on bank 1 in third paragraph of AWAKE
Pin Behavior when Suspend Feature is Enabled. Added “for Recommended
Operating Conditions” to data sheet power levels referenced in FPGA Voltage
Requirements During Suspend Mode.
•InChapter 2, changed “used” to “being programmed” in description section, last row,
of Table 2-1. Added VCCAUX setting restriction paragraphs to VCCAUX. Removed
“±5%” specification from first paragraph in VCCAUX Specifications and third
paragraph of VCCO.
•InChapter 3, removed “approximately one speed grade slower (~15%)” from first
paragraph in Introduction. Added a UG382 reference to Designing Using the
Lower-Power Spartan-6 LX Devices. Added VCCAUX and IODELAY2 specification
paragraphs to Lower-Power Spartan-6 LX Device Specifications.
•InChapter 5, removed “50%” specification from second paragraph in Saving Power.
Also remove last sentence referencing techniques for past FPGA families from last
paragraph in ISE Design Suite Power Optimization.

Spartan-6 FPGA Power Management www.xilinx.com 3
UG394 (v1.1) September 4, 2012
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1: Power Management With Suspend Mode
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Differences from Extended Spartan-3A Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multi-Pin Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Suspend Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Suspend Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Entering Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Exiting Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PROGRAM_B Programming Pin Always Overrides Suspend Mode . . . . . . . . . . . . . 14
Enable the Suspend Feature and Glitch Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
User Constraints File Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bitstream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Define the Multi-Pin Wake-Up Feature and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Define the I/O Behavior During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Single-Ended I/O Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SUSPEND Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UCF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Design Maintained during Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Design Requirements to Maintain Application Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Suspend Mode Wake-Up Timing Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Wake-Up Timing Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Switch Outputs from Suspend to Normal Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Release Write Protect on Clocked Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dedicated Configuration Pins Unaffected During Suspend Mode . . . . . . . . . . . . 19
JTAG Operations Allowed During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SUSPEND Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SUSPEND Input Glitch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SUSPEND_SYNC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AWAKE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Behavior (Suspend Feature Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AWAKE Pin Behavior when Suspend Feature is Enabled . . . . . . . . . . . . . . . . . . . . . . 21
Controlling Wake-Up from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Synchronizing Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table of Contents

4www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Post-Configuration CRC Limitations When Using Suspend Mode. . . . . . . . . . . . 22
FPGA Voltage Requirements During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Controller Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 2: Voltage Supplies
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VCCINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VCCAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Setting the VCCAUX Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VCCAUX Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Board Design and Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Simultaneously Switching Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power Distribution System Design and Decoupling/Bypass Capacitors . . . . . . . . . . 28
Chapter 3: Lower-Power Spartan-6 LX Devices
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Designing Using the Lower-Power Spartan-6 LX Devices . . . . . . . . . . . . . . . . . . . . 29
Lower-Power Spartan-6 LX Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 4: Power-On and Power-Down Behavior Including Hibernate
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Configuration Data Retention and Brown Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GTP Transceiver Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hibernate Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Forcing FPGA to Quiescent Current Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Entering Hibernate State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Turn Off VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Exiting Hibernate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 5: Power Estimation
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Saving Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Saving Clock Routing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ISE Design Suite Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Spartan-6 FPGA Power Management www.xilinx.com 5
UG394 (v1.1) September 4, 2012
Preface
About This Guide
This document provides information on the various hardware methods of power
management in Spartan-6 FPGAs, primarily focusing on the suspend mode. Other power
management topics include the lower-power Spartan-6 LX devices (-1L) and the
programmable VCCAUX level available in all Spartan-6 devices. In addition, more detail is
provided on the power rails, including hot swap and hibernate (power-off) options.
Guide Contents
This user guide contains the following chapters:
•Chapter 1, Power Management With Suspend Mode
•Chapter 2, Voltage Supplies
•Chapter 3, Lower-Power Spartan-6 LX Devices
•Chapter 4, Power-On and Power-Down Behavior Including Hibernate
•Chapter 5, Power Estimation
Additional Documentation
These documents are available for download at
http://www.xilinx.com/support/documentation/spartan-6.htm.
• Spartan-6 Family Overview
This overview outlines the features and product selection of the Spartan-6 family.
• Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and switching characteristic specifications for the
Spartan-6 family.
• Spartan-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Spartan-6 FPGA Configuration User Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and parallel), multi-bitstream management, bitstream encryption,
boundary-scan and JTAG configuration, and reconfiguration techniques.
• Spartan-6 FPGA SelectIO Resources User Guide
This guide describes the SelectIO™ resources available in all Spartan-6 devices.

6www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Running H/F 3
•Spartan-6FPGAClockingResources User Guide
This guide describes the clocking resources available in all Spartan-6 devices,
including the DCMs and PLLs.
• Spartan-6 FPGA Block RAM Resources User Guide
This guide describes the Spartan-6 device block RAM capabilities.
• Spartan-6 FPGA Configurable Logic Blocks User Guide
This guide describes the capabilities of the configurable logic blocks (CLBs) available
in all Spartan-6 devices.
• Spartan-6 FPGA GTP Transceivers User Guide
This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.
• Spartan-6 FPGA DSP48A1 Slice User Guide
This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and
provides configuration examples.
• Spartan-6 FPGA Memory Controller User Guide
This guide describes the Spartan-6 FPGA memory controller block, a dedicated
embedded multi-port memory controller that greatly simplifies interfacing
Spartan-6 FPGAs to the most popular memory standards.
• Spartan-6 FPGA PCB Design and Pin Planning Guide
This guide provides information on PCB design for Spartan-6 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
These documents provide additional background:
•WP298, Power Consumption at 40 nm and 45 nm, White Paper
At 40 and 45 nm process nodes, power has become the primary factor for FPGA
selection. Spartan-6 FPGAs offer lower power, simpler power systems and PCB
complexity, better reliability, and lower system cost. This white paper details how
Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex®-6 (40 nm) FPGA
families, achieving dramatic power reductions over previous generation devices.
•WP370, Reducing Switching Power with Intelligent Clock Gating, White Paper
Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce
dynamic power by up to 30% for Spartan-6 FPGA designs.
•WP396, High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design,
White Paper
This white paper describes how Spartan-6 FPGAs address the needs of high-volume
systems. The ability to connect efficiently and inexpensively to commodity memories,
high-performance chip-to-chip interface capability, and innovative power down
modes are just a few of the problems solved by high-performance, low-power, and
low-cost Spartan-6 FPGAs.
Additional Support Resources
To search the database of silicon and software questions and answers or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.

Spartan-6 FPGA Power Management www.xilinx.com 7
UG394 (v1.1) September 4, 2012
Chapter 1
Power Management With Suspend Mode
Introduction
Some applications require the lowest possible system cost or highest performance, and
other applications require the lowest possible standby power. Spartan®-6 FPGAs offer
low-power options to balance these cost and performance trade-offs.
The Spartan-6 family offers the suspend mode, an advanced static power-management
feature, which reduces FPGA power consumption while retaining the FPGA's
configuration data and maintaining the design. The device can quickly enter and exit
suspend mode as required in an application.
Differences from Extended Spartan-3A Family
The suspend mode in Spartan-6 FPGAs is a superset of the suspend feature in the
Extended Spartan-3A FPGAs. Two new enhancements include multi-pin wake-up and
suspend synchronization.
Multi-Pin Wake-up
The multi-pin wake-up feature allows the FPGA to monitor for a wake-up signal on up to
eight pins. In the Extended Spartan-3A family, monitoring was limited to the SUSPEND
pin itself. Multi-pin wake-up also allows a number of independent sources to trigger the
FPGA to return to the normal application.
Suspend Synchronization
The Spartan-6 FPGA primitive, SUSPEND_SYNC, enables the synchronization of the
suspend action with the application design. In the Extended Spartan-3A family, the
suspend mode activation begins immediately upon asserting the SUSPEND pin. The
Spartan-6 FPGA SUSPEND_SYNC primitive allows the application design to
acknowledge a suspend request, thereby allowing the application to finish necessary
functions prior to entering the suspend mode.

8www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Suspend Features
The significant features and benefits of the suspend mode:
• Quickly and easily puts the FPGA into a static condition, eliminating most active
current.
• Reduces quiescent current by 40% or more.
• Retains FPGA configuration data and the state of the FPGA application during
suspend mode.
• Fast, programmable FPGA wake-up time from suspend mode.
• Individual control on each user-I/O pin to define pin behavior while in suspend
mode.
• Activated externally by the system using a single dedicated control pin (SUSPEND).
• Indicates the present suspend mode status using the AWAKE pin.
• Awakens an FPGA in suspend mode using any of eight SUSPEND control pins (SCP).
• SUSPEND_SYNC primitive to acknowledge a ready state prior to entering suspend
mode.
Design Steps
To use the suspend feature:
•Enable the Suspend Feature and Glitch Filtering, page 14
•Define the Multi-Pin Wake-Up Feature and Pins, page 15
•Define the I/O Behavior During Suspend Mode, page 15
• Implement steps to maintain application data during suspend mode
(SUSPEND_SYNC) (see Design Requirements to Maintain Application Data, page 17)
• Define the Suspend Mode Wake-Up Timing Controls, page 17
• Define the AWAKE Pin Behavior when Suspend Feature is Enabled, page 21
Entering Suspend Mode
Figure 1-1 is a block diagram of the FPGA entering suspend mode. Figure 1-2, page 10
shows example waveforms.

Spartan-6 FPGA Power Management www.xilinx.com 9
UG394 (v1.1) September 4, 2012
Entering Suspend Mode
The FPGA can only enter suspend mode if enabled in the configuration bitstream (see
Enable the Suspend Feature and Glitch Filtering, page 14). The SUSPEND pin must be Low
during power up and configuration. Once enabled through the bitstream, and the
SUSPEND_SYNC primitive is not present in the design, when the SUSPEND pin is
asserted, the FPGA unconditionally and quickly enters suspend mode.
If the SUSPEND_SYNC primitive is present in the design, the FPGA does not enter
suspend mode until the suspend-acknowledge signal (SACK) is asserted. After the
SUSPEND pin is asserted, the SREQ port of the SUSPEND_SYNC primitive transitions
High. This can be used in the design to initiate any functions that must be completed prior
to the FPGA entering suspend mode. When these functions are complete, drive the SACK
port High.
After the FPGA enters suspend mode, all nonessential FPGA functions are shut down to
minimize power dissipation. The FPGA retains all configuration data while in suspend
mode. After entering suspend mode, all writable clocked primitives are write-protected
against spurious write operations, and all FPGA inputs and interconnects are shut down.
This allows the design state to be held static during suspend mode. If a specific design state
must be maintained, see Design Requirements to Maintain Application Data, page 17.
X-Ref Target - Figure 1-1
Figure 1-1: Entering Suspend Mode
SUSPEND
Attribute
SUSPEND
Attribute
Glitch Filter
Suspend Enable
SRL
LUT RAM
Flip-Flops
Latches
Block RAM
Writable Clocked Primitives
FPGA Application Logic
FPGA
Inputs
FPGA
Outputs
SUSPEND AWAKE
ENABLE_SUSPEND
ENABLE_SUSPEND
Filter Select
Write-Protect Writable
Clocked Primitives
Apply SUSPEND Attribute
to FPGA Outputs
Block FPGA
Inputs
SUSPEND_SYNC
SUSPEND_SYNC
Instantiated
UG394_c1_01_020310
SREQ SACK

10 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Each FPGA output pin or bidirectional I/O pin assumes its defined suspend mode
behavior, which is described as part of the FPGA design using a SUSPEND attribute.
The AWAKE pin goes Low, indicating that the FPGA is in suspend mode. The DONE pin
remains High while the FPGA is in suspend mode because the FPGA configuration data is
not lost.
This section details the waveform notes in Figure 1-2.
Entering Suspend in Figure 1-2
1. An external signal drives the FPGA's SUSPEND pin High, unconditionally forcing the
FPGA into the power-saving suspend mode (if SUSPEND_SYNC is not used). When
SUSPEND_SYNC is used, this phase does not complete until the SACK port of the
SUSPEND_SYNC primitive is asserted. Data values are captured for I/O pins with a
SUSPEND attribute set to DRIVE_LAST_VALUE; however, this value is not presented
until Step 4.
2. In response to the SUSPEND input going High or SACK assertion on the
SUSPEND_SYNC primitive, and after a delay of tSUSPEND_GWE, the FPGA write
protects and preserves the states of all clocked primitives. The states of all flip-flops,
block RAM, distributed RAM (LUT RAM), shift registers (SRL), and I/O latches are
preserved during suspend mode.
X-Ref Target - Figure 1-2
Figure 1-2: Suspend Mode Waveforms (Entering and Exiting)
ug394_c1_02_042910
Blocked
tSUSPEND_DISABLE
tAWAKE_GWE
tAWAKE_GTS
SUSPEND Input
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Write Protected
Defined by SUSPEND Attribute
1
2
3
4
5
6
7
8
10
9
Entering Suspend Mode Exiting Suspend Mode
sw_gts_cycle
sw_gwe_cycle
tSUSPEND_ENABLE
tSUSPENDLOW_AWAKE
tSUSPEND_GTS
tSUSPENDHIGH_AWAKE
tSUSPEND_GWE

Spartan-6 FPGA Power Management www.xilinx.com 11
UG394 (v1.1) September 4, 2012
Entering Suspend Mode
3. After a delay of tSUSPENDHIGH_AWAKE, the FPGA drives the AWAKE output Low to
indicate that it is entering suspend mode.
4. After a delay of tSUSPEND_GTS, the FPGA switches the normal behavior of all outputs
over to the suspend mode behavior defined by the SUSPEND attribute assigned to
each I/O. See Define the I/O Behavior During Suspend Mode, page 15.
5. After a delay of tSUSPEND_DISABLE, FPGA inputs are blocked and the interconnect shut
off (High) to prevent any internal switching activity.
Exiting Suspend in Figure 1-2
6. The system drives the FPGA's SUSPEND input Low, causing the FPGA to exit suspend
mode. If using multi-pin wake-up mode, the system first drives the FPGA's SUSPEND
input LOW, then drives any of the enabled multi-pin wake-up pins High, causing the
FPGA to exit suspend mode.
7. The FPGA releases the inputs and interconnect after a delay of tSUSPEND_ENABLE,
allowing signals to propagate internally. There is no danger of corrupting the internal
state because all clocked primitives are still write protected.
8. After a delay of tSUSPENDLOW_AWAKE or tSCP_AWAKE, the FPGA asserts the AWAKE
signal with the bitstream option drive_awake:yes. If the option is drive_awake:no,
then the FPGA releases AWAKE to become an open-drain output. In this case, an
external pull-up resistor is required or an external signal must drive AWAKE High
before the FPGA continues to awaken. All subsequent timing is measured from when
the AWAKE output transitions High. If multiple FPGAs are waking up and need to be
synchronized, set drive_awake:no in each and then use an external pull-up resistor to
synchronize the AWAKE pins. If other devices are waking up and the FPGA(s) need to
wait, set drive_awake:no and use an external signal to control the AWAKE pin and
drive it High once the rest of the system is ready.
9. After a delay of tAWAKE_GTS, the FPGA switches output behavior from the specified
SUSPEND attribute to the function specified in the FPGA application. The timing of
this switch-over is controlled by the suspend/wake sw_gts_cycle bitstream
generation setting, which defines when the FPGA's internal global three-state (GTS)
control is released. After the specified number of clock cycles, the outputs are active
according to the normal FPGA application. By default, the outputs are enabled four
clock cycles after AWAKE goes High. The outputs are generally released before the
clocked primitives to allow signals to propagate out of the FPGA.
10. After a delay of tAWAKE_GWE, the writable, clocked primitives are released according
to the suspend/wake sw_gwe_cycle bitstream generator setting, which defines when
the FPGA's internal global write enable (GWE) control is asserted. After the specified
cycle, it is again possible to write to flip-flops, block RAM, distributed RAM (LUT
RAM), shift registers (SRL), and I/O latches. By default, the clocked primitives are
released five clock cycles after AWAKE transitions High. The write-protect lock should
be held until after outputs are enabled.

12 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Exiting Suspend Mode
There are four possible ways to exit suspend mode in a powered system:
• Drive the SUSPEND input Low, exiting suspend mode.
• If multi-pin wake-up mode is enabled, drive the SUSPEND input Low and then assert
any one of the user enabled SCP pins.
• Pulse the PROGRAM_B input Low to reset the FPGA and cause the FPGA to
reprogram.
• Power cycle the FPGA, causing the FPGA to reprogram.
The block diagram in Figure 1-3 shows how to exit suspend mode using the SUSPEND
pin.
When SUSPEND transitions Low, the FPGA automatically re-enables all inputs and
interconnects after a delay of tSUSPEND_ENABLE. If using multi-pin wake-up mode,
SUSPEND must first transition Low, then when any of the user enabled SCP pins for
multi-pin wake up mode transition High, the FPGA re-enables all inputs and interconnects
after a delay of tSUSPEND_ENABLE.
When enabled in the FPGA bitstream, all flip-flops are optionally globally set or reset
according to the FPGA design description. By default, the flip-flops are not globally set or
reset, which preserves the state of the FPGA application from the beginning of suspend
mode.
The remaining wake-up process depends on two user-programmable timers which define
when FPGA outputs are re-enabled and when the write-protect lock is released from all
writable clocked primitives. These timers begin after the AWAKE pin is High. The
wake-up timing clock source is also programmable.

Spartan-6 FPGA Power Management www.xilinx.com 13
UG394 (v1.1) September 4, 2012
Exiting Suspend Mode
X-Ref Target - Figure 1-3
Figure 1-3: Exiting Suspend Mode
SUSPEND
Attribute
SUSPEND
Attribute
Wake-Up
Timing Clock
Source
Glitch Filter
Suspend Enable
SRL
LUT RAM
Flip-Flops
Latches
Block RAM
Writable Clocked Primitives
FPGA Application Logic
FPGA
Inputs
FPGA
Outputs
Re-enable
FPGA Inputs
Set/Reset
Flip-Flops
SUSPEND
AWAKE
Enable
Unlock Clocked
Primitives
Activate Outputs
sw_clk
en_sw_gsr
ENABLE_SUSPEND
ENABLE_SUSPEND
sw_gts_cycle
sw_gwe_cycle
Filter Select
14
1 1,024
1,024
5
UG394_c1_03_020310
drive_awake
multipin_wakeup
edge detector
wakeup_mask<0>
edge detector
wakeup_mask<1>
edge detector
wakeup_mask<7>
SCP0
SCP1
SCP7
Multi-Pin Wake-up

14 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
PROGRAM_B Programming Pin Always Overrides Suspend Mode
Pulsing the PROGRAM_B programming pin Low always overrides suspend mode and
forces the FPGA to restart configuration. Power-cycling the FPGA also restarts
configuration. If the SUSPEND input remains High, the device re-enters suspend mode
after finishing configuration.
Enable the Suspend Feature and Glitch Filtering
Before it can be used, the suspend power-saving feature must first be enabled in the FPGA
bitstream. By default, the suspend feature is disabled and driving the SUSPEND pin has no
effect. The suspend feature is enabled using the user constraints file (UCF), or through a
bitstream generator (BitGen) option.
User Constraints File Enable
Suspend mode is enabled and the SUSPEND input glitch filter option is defined using a
CONFIG statement in a UCF. Table 1-1 shows the available options. This is the
recommended method for enabling suspend mode as this attribute also automatically
reserves the AWAKE pin.
Config ENABLE_SUSPEND = "FILTERED" ;
Bitstream Generator
Setting the en_suspend bitstream option is an alternate way to enable the suspend mode.
However, this method is not recommended because it does not automatically reserve the
AWAKE pin in the application.
bitgen -g en_suspend:Yes
The following option enables the glitch filter on the SUSPEND pin.
bitgen -g suspend_filter:Yes
Table 1-1: Available Options for the ENABLE_SUSPEND Attribute
Option Suspend Mode SUSPEND Pin Filter AWAKE Pin
NO Suspend mode is disabled Not applicable. Connect
SUSPEND pin to GND.
Available as a user I/O pin
in the FPGA application.
FILTERED Suspend mode is enabled Glitch filter is enabled. AWAKE status indicator.
UNFILTERED Glitch filter is bypassed.

Spartan-6 FPGA Power Management www.xilinx.com 15
UG394 (v1.1) September 4, 2012
Enable the Suspend Feature and Glitch Filtering
Define the Multi-Pin Wake-Up Feature and Pins
The multi-pin wake-up feature is not required to use the suspend mode feature. If
multi-pin wake-up is not enabled, suspend mode is enabled and disabled using just the
SUSPEND pin. Multi-pin wake-up is enabled using a BitGen option.
bitgen -g multipin_wakeup:Yes
If multi-pin wake-up is enabled, select which pins are monitored for a rising edge to bring
the FPGA out of suspend mode. Eight SCP pins are used for the multi-pin wake-up
feature. Select from one to eight of these pins to monitor. The SCP pins are dual-purpose
user I/O pins and can be used as general-purpose I/O independent of the suspend
options. Any pins that are not used can be masked out as inputs to the multi-pin wake-up.
The option accepts two hex values for the mask. A value of FF enables all SCP pins, 0F
enables SCP<3..0>.
bitgen -g wakeup_mask:FF
Define the I/O Behavior During Suspend Mode
Use a SUSPEND attribute to define the behavior of each I/O and output pin during
suspend mode.
Single-Ended I/O Standards
Each output, open-drain output, or bidirectional I/O pin in the FPGA application that uses
a single-ended I/O standard can be individually programmed for one of the suspend
mode behaviors shown in Table 1-2. The default behavior is for a high impedance pin
during suspend mode although other options are available.
Differential I/O Standards
The output drivers for the LVDS, RSDS, mini-LVDS, PPDS, and TMDS differential I/O
standards are high impedance, using any of the 3STATE attributes described in Table 1-2.
The DRIVE_LAST_VALUE attribute is not supported for differential output drivers.
Treat the pseudo-differential I/O standards, such as BLVDS, DIFF_HSTL, and DIFF_SSTL,
as two single-ended I/O pins. All the attributes apply as for Single-Ended I/O Standards
Table 1-2: Output Behavior Options during Suspend Mode
SUSPEND Attribute Function
DRIVE_LAST_VALUE
The output continues to drive the level that was last stored in the output latch, according
to the chosen standard. Requires VCCO to remain at the recommended operating conditions
for the bank.
3STATE
(default)
The output is in the high-impedance state with no active internal pull-up or pull-down
resistor. Results in the lowest possible I/O current draw.
3STATE_PULLUP
The output is in the high-impedance state with an internal pull-up resistor to the associated
VCCO supply. Requires VCCO to remain at the recommended operating conditions for the
bank.
3STATE_PULLDOWN The output is in the high-impedance state with an internal pull-down resistor to GND.
3STATE_KEEPER The output is high impedance. The internal bus keeper circuit is active. Requires VCCO to
remain at the recommended operating conditions for the bank.

16 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
although for any differential standard the settings must be set appropriately for both pins
of the complementary pair.
When in the high-impedance state, the differential driver pair does not conduct current to
the power or ground rails, or between adjacent pins.
SUSPEND Attribute
The SUSPEND attribute allows each pin to have an individually defined behavior during
suspend mode. The available options are listed in Table 1-2.
UCF Example
This UCF constraint example defines the suspend mode behavior for a specific pin. The
SUSPEND attribute can be included on the same UCF line as other constraints for a pin.
Net "<net_name>" SUSPEND = "io_type" ;
UCF entries for a single-ended pin and a differential pair are shown in the following
example:
NET "TX<0>" IOSTANDARD = LVCMOS_33 | SUSPEND = "DRIVE_LAST_VALUE" ;
NET "TX_P<0>" IOSTANDARD = LVDS_33 | SUSPEND = "3STATE_PULLUP" ;
NET "TX_N<0>" IOSTANDARD = LVDS_33 | SUSPEND = "3STATE_PULLDOWN" ;
Design Maintained during Suspend Mode
After entering suspend mode, all writable clocked primitives are write-protected after a
delay of tSUSPEND_GWE. The state of all clocked memory primitives is maintained during
suspend mode.
• Logic block flip-flops
• I/O block latches and flip-flops
• Logic block distributed RAM (LUT RAM)
• Logic block shift registers (SRL)
• Block RAM and registers
When exiting suspend mode, all writable clocked primitives are re-enabled, controlled by
the sw_gwe_cycle setting.
An additional bitstream option, en_sw_gsr, controls whether all clocked primitives are
globally set or reset when the FPGA awakens from suspend mode. By default,
en_sw_gsr:No signifies that clocked primitives are not set or reset when the FPGA
awakens and all states are preserved.

Spartan-6 FPGA Power Management www.xilinx.com 17
UG394 (v1.1) September 4, 2012
Suspend Mode Wake-Up Timing Controls
Design Requirements to Maintain Application Data
When a design requires that application data be preserved when entering suspend mode,
the SUSPEND_SYNC primitive should be used. When the FPGA enters suspend mode, the
global write enable (GWE) is removed, maintaining the state of all flip-flops and user
RAM. The FPGA requires a delay of tSUSPEND_GWE between recognizing a High on the
SUSPEND pin and disabling GWE internally. This is the first event after SUSPEND
transitions High, before AWAKE toggles, and before the inputs are disabled if
SUSPEND_SYNC is not used. During this delay, additional user clocks to flip-flops or
RAM can continue to update their contents. Since the GWE signal can have some skew
between locations on the device, some locations can be disabled while others remain
enabled on the last clock edge before GWE takes full effect. This situation can be avoided
when using the SUSPEND_SYNC feature. After the suspend request is driven out of the
SUSPEND_SYNC primitive, disable the clocks and/or clock enables on the logic that must
retain its current state. After the disable is complete, drive the SACK port of the
SUSPEND_SYNC primitive and the FPGA begins the process to enter suspend mode.
To avoid initializing the flip-flops when exiting suspend mode, choose en_sw_gsr:No.
Exiting suspend mode should be synchronized to a user clock to avoid race conditions
corrupting the application data. Inputs are enabled first, allowing control signals to
continue to hold off the toggling of storage primitives. The assertion of GWE can be
synchronized to a user clock to align it with a system clock edge.
Suspend Mode Wake-Up Timing Controls
When exiting suspend mode, the wake-up sequence for the FPGA is programmable and
controlled by a single clock.
Wake-Up Timing Clock Source
The wake-up timing when exiting suspend mode is controlled by a selectable clock source
as shown in Figure 1-4 and described in Table 1-3. The clock source is defined by one or
two bitstream generator options, sw_clk and sometimes StartupClk.
The internal oscillator is disabled during suspend mode to conserve power.

18 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
•Thesw_clk option is specific to the suspend feature. By default,
sw_clk:InternalClk.
•TheStartupClk option is available on every application. The same option used to
clock the start-up process at the end of configuration can be used to clock the wake-up
process at the end of suspend. StartupClk:Cclk is the default; however, using this
for suspend wake-up requires a persisted slave configuration mode. When using
sw_clk:StartupClk and StartupClk:Cclk, and exiting suspend mode, the
CCLK pin becomes the clock source. The Persist option also retains the dual-purpose
configuration pins associated with the configuration logic.
X-Ref Target - Figure 1-4
Figure 1-4: Suspend Mode Wake-Up Timing Control Clock Selection
StartupClk
InternalClk
sw_clk
~50 MHz
Internal
Oscillator
Cclk
Jtag
UserClk
CCLK
TCK
STARTUP_SPARTAN6
StartupClk
CLK
CCLK input only available for
applicationsthat configure in Slave
mode. Persist = Yesrequired.
User Clock from
FPGA Interconnect
Suspend
Wake-Up
Timing
Control
UG394_c1_04_121009
Table 1-3: Clock Sources to Wake-Up from Suspend Mode
sw_clk
Setting
StartupClk
Setting Clock Source Restriction
InternalClk NA Internal Oscillator The oscillator has an imprecise frequency of about
50 MHz.
StartupClk
Cclk CCLK pin on FPGA
This option is only available for FPGAs using Slave
configuration mode. The bitstream option Persist:Yes
must be set. This option is not available for FPGAs
using the master configuration mode; use InternalClk
instead.
JtagClk TCK pin on FPGA The JTAG interface must be active to exit suspend
mode.
UserClk
CLK input on the
STARTUP_SPARTAN6
design primitive
The clock input to the STARTUP design primitive can
originate from any non-clocked signal in the FPGA. It
cannot originate from a flip-flop source because all
clocked primitives are write-protected while in
suspend mode.

Spartan-6 FPGA Power Management www.xilinx.com 19
UG394 (v1.1) September 4, 2012
Dedicated Configuration Pins Unaffected During Suspend Mode
Switch Outputs from Suspend to Normal Behavior
The suspend/wake sw_gts_cycle bitstream option controls when I/O pins are released
from their SUSPEND attribute settings and returned to normal operation. The timing is
controlled by the Wake-Up Timing Clock Source, page 17. The default sw_gts_cycle setting
is four cycles, but this control can be set for any value between one and 1,024 clock cycles.
The suspend/wake control becomes active after the AWAKE pin transitions High. After
the specified number of clock cycles, all output, open-drain output, and bidirectional I/O
pins transition from their suspend behavior, either the default 3STATE or individually
specified using the SUSPEND attribute, back to the normal behavior specified in the
original FPGA application.
The outputs should be released before releasing the write-protect lock on all clocked
primitives.
Release Write Protect on Clocked Primitives
The suspend/wake sw_gwe_cycle bitstream option controls when the write-protect lock is
released on all clocked primitives.
The timing is controlled by sw_clk the Wake-Up Timing Clock Source, page 17. The default
sw_gwe_cycle setting is five cycles, but the suspend/wake control can be set for any value
between one and 1,024 clock cycles.
This suspend/wake control becomes active after the AWAKE pin transitions High. After
the specified number of clock cycles, the write-protect lock is released from all writable,
clocked primitives such as flip-flops, block RAM, etc.
When the en_sw_gsr:yes option is set, the clocked primitives are already globally set or
reset to the value specified in the original FPGA design before the write-protect lock is
released. The option en_sw_gsr:no signifies that the state of the FPGA after entering
suspend mode is preserved.
The outputs should be released before releasing the write-protect lock on all clocked
primitives.
Dedicated Configuration Pins Unaffected During Suspend Mode
The following dedicated configuration pins are unaffected when the FPGA is in suspend
mode:
• JTAG pins: TDI, TMS, TCK, and TDO
•DONEpin
•PROGRAM_Bpin
JTAG Operations Allowed During Suspend Mode
Table 1-4 shows the JTAG operations permitted when the FPGA is in suspend mode.
Executing these JTAG operations increases the FPGA's power consumption while in
suspend mode.

20 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Do not use any other JTAG instructions when in suspend mode or while transitioning into
and out of suspend mode. Furthermore, do not enter suspend mode when performing a
readback operation.
SUSPEND Pin
When the suspend feature is enabled (see Enable the Suspend Feature and Glitch Filtering,
page 14), the SUSPEND pin controls when the FPGA enters suspend mode. During normal
FPGA operation, the SUSPEND pin must be Low. When High, the SUSPEND pin forces the
FPGA into the low-power suspend mode. Table 1-5 describes the functionality of the
SUSPEND pin.
If the suspend feature is not enabled for an application (the application never enters
low-power mode), then connect the SUSPEND pin to GND. Do not leave the pin floating
or High.
Characteristics
The SUSPEND pin is an LVCMOS/LVTTL receiver, and power to the input buffer is
supplied by the VCCAUX power rail. The SUSPEND pin has no pull-up resistors during
configuration, and the HSWAPEN control has no effect on the SUSPEND pin.
Table 1-4: JTAG Operations Allowed during Suspend Mode
Boundary-Scan
Command Description
IDCODE
Read the JTAG ID code that describes the Spartan-6 FPGA array
type in the JTAG chain. This value is different from the Device
DNA identifier, which is unique to every device.
BYPASS Enables BYPASS.
USERCODE Read the user-defined code embedded in the FPGA bitstream.
Table 1-5: SUSPEND Pin Functionality
ENABLE_SUSPEND
Settings
SUSPEND
Pin Function
NO (default)
Suspend Mode
Disabled
0
The suspend feature is disabled. The SUSPEND pin is unused and ignored.
Connect the SUSPEND pin to GND.
Filtered, Unfiltered
Suspend Mode
Enabled
0
The FPGA performs the application described in the bitstream loaded into the
FPGA during configuration. When the SUSPEND pin changes from High to
Low, wake the FPGA from suspend mode. Return from suspend mode also
depends on the SCP pins, if used.
1Force the FPGA to enter power-saving suspend mode pending SACK assertion
on SUSPEND_SYNC primitive, if used.