Xilinx AC701 User manual

AC701 Evaluation Board
for the Artix-7 FPGA
User Guide
UG952 (v1.0) October 23, 2012

AC701 Evaluation Board www.xilinx.com UG952 (v1.0) October 23, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
10/23/12 1.0 Initial Xilinx release.

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: AC701 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC701 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Artix-7 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDR3 Memory Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI External Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
USB JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCI Express Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SFP/SFP+ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10/100/1000 Mb/s Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LCD Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Bus Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AC701 Board LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FPGA Mezzanine Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
XADC Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Appendix A: Default Switch and Jumper Settings
User GPIO DIP Switch SW2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Configuration DIP Switch SW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Default Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Master UCF Listing
AC701 Board UCF Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Appendix D: Board Setup
Installing the AC701 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table of Contents

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Appendix E: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix F: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Solution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Further Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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Chapter 1
AC701 Evaluation Board Features
Overview
The AC701 evaluation board for the Artix™-7 FPGA provides a hardware environment for
developing and evaluating designs targeting the Artix-7 XC7A200T-2FBG676C FPGA. The
AC701 board provides features common to many embedded processing systems,
including a DDR3 SODIMM memory, an 4-lane PCI Express® interface, a tri-mode
Ethernet PHY, general purpose I/O, and a UART interface. Other features can be added by
using mezzanine cards attached to the VITA-57 FPGA mezzanine connector (FMC)
provided on the board. A high pin count (HPC) FMC connector is provided. See AC701
Board Features for a complete list of features. The details for each feature are described in
Feature Descriptions, page 7.
Additional Information
See Appendix F, Additional Resources for references to documents, files and resources
relevant to the AC701 board.
AC701 Board Features
• Artix-7 XC7A200T-2FBG676C FPGA
• 1 GB DDR3 memory SODIMM
• 256 Mb Quad-SPI Flash memory
• Secure Digital (SD) connector
• USB JTAG via Digilent module
•ClockGeneration
• Fixed 200 MHz LVDS oscillator
•I
2C programmable LVDS oscillator
• SMA connectors
• SMA connectors for GTP transceiver clocking
•GTPtransceivers
• FMC HPC connector (two GTP transceivers)
• SMA connectors (one pair each for TX, RX and REFCLK)
• PCI Express (four lanes)
• Small form-factor pluggable plus (SFP+) connector
• Ethernet PHY RGMII interface (RJ-45 connector)
• PCI Express endpoint connectivity

6www.xilinx.com AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
Chapter 1: AC701 Evaluation Board Features
• Gen1 4-lane (x4)
• Gen2 4-lane (x4)
• SFP+ Connector
• 10/100/1000 tri-speed Ethernet PHY
• USB-to-UART bridge
•HDMIcodec
•I
2C bus
•I
2C MUX
•I
2C EEPROM (1 KB)
•USERI
2C programmable LVDS oscillator
• DDR3 SODIMM socket
•HDMIcodec
• FMC HPC connector
• SFP+ connector
•I
2C programmable jitter-attenuating precision clock multiplier
• Status LEDs
•Ethernetstatus
• Power good
•FPGAINIT
•FPGADONE
•UserI/O
•USERLEDs(fourGPIO)
• User pushbuttons (five directional)
• CPU reset pushbutton
•UserDIPswitch(4-poleGPIO)
• User SMA GPIO connectors (one pair)
• LCD character display (16 characters x 2 lines)
••Switches
• Power on/off slide switch
• Configuration mode DIP switch
• VITA 57.1 FMC HPC Connector
• Power management
• PMBus voltage and current monitoring via TI power controller
•XADCheader
• Configuration options
•QuadSPI
• USB JTAG configuration port
• Platform cable header JTAG configuration port
The AC701 board block diagram is shown in Figure 1-1. The AC701 board schematics are
available for download from:

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UG952 (v1.0) October 23, 2012
Feature Descriptions
http://www.xilinx.com/AC701
Caution! The AC701 board can be damaged by electrostatic discharge (ESD). Follow
standard ESD prevention measures when handling the board
Feature Descriptions
Figure 1-2 shows the AC701 board. Each numbered feature that is referenced in Figure 1-2
is described in the sections that follow.
Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the
board.
X-Ref Target - Figure 1-1
Figure 1-1: AC701 Board Block Diagram
UG952_c1_01_101512
Artix-7 FPGA
XC7A200T-2FBG676C
128 Mb Quad-SPI
Flash Memory
SD Card
Interface
4-lane PCI Express
Edge Connector
LCD Display
(2 line x 16 characters)
1 KB EEPROM (I2C)
I2C Bus Switch
XADC Header
User Switches,
Buttons, and LEDs
HDMI Video
Interface
Differential Clock
GTP SMA Clock
1 GB DDR3 Memory
(SODIMM)
FMC Connector
(HPC)
10/100/1000 Ethernet
Interface
DIP Switch SW1
Config USB-to-UART Bridge JTAG Interface
micro-B USB Connector SFP+ Single Cage

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Chapter 1: AC701 Evaluation Board Features
X-Ref Target - Figure 1-2
Figure 1-2: AC701 Board Components
UG952_c1_02_101512
18
29
30
31
13
5
14
1
67
30
11
11
8
9
32
10
3
16
17
12
15
2
25
00 Square callout references a component
on the back side of the board
Round callout references a component
on the front side of the board
00
4
26
23
21
28
22
24
20
19
27
Table 1-1: AC701 Board Component Descriptions
Callout Reference Designator Component Description Notes Schematic 0381502
Page Number
1 U1 Artix-7 FPGA Xilinx XC7A200T-2FBG676C
2 J1 DDR3 SODIMM Socket w/Memory Micron MT8JT12864HZ-1G6G1 10
3 U7 Quad-SPI Flash Memory Micron/Numonyx N25Q256A13ESF40G 4
4 U29 SD Card Interface Connector Molex 67840-8001 14
5 U26 USB-JTAG Module Digilent USB JTAG Module (with micro-B
receptacle)
4
6 U51 System Clock Source (back side of board) SiTime SIT9102AI-243N25E200.0000 3
7 U34 Programmable User Clock Source
10MHz-810MHz (back side of board)
Silicon Labs SI570BAB000544DG (default
156.250MHz)
3
8 J31, J32 SMA User Clock Input Rosenberger 32K10K-400L5 3
9 J25, J26 SMA GTP Ref. Clock Input Rosenberger 32K10K-400L5 3
10 U24 Jitter Attenuated Clock (back side of board) Silicon Labs SI5324-C-GM 16
11 U1 GTP Transceivers Embedded within FPGA U1 30
12 P1 PCI Express Edge Connector 4-lane card edge connector 28
13 P3 SFP/SFP+ Connector Molex 74441-0010 20
14 U12 10/100/1000 Tri-Speed Ethernet PHY Marvell 88E1116RA0-NNC1C000 15
15 U2 GTP Transceiver Clock Generator 125MHz ICS ICS84402IAGI-01LF 3
16 J17, U44 USB-to-UART Bridge (back side of board) and
min-B receptacle (front side of board)
Silicon Labs CP2103GM 5

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Feature Descriptions
Artix-7 FPGA
[Figure 1-2, callout 1]
The AC701 board is populated with the Artix-7 XC7A200T-2FBG676C FPGA.
For further information on Artix-7 FPGAs, see DS180, 7 Series FPGAs Overview.
FPGA Configuration
The AC701 board supports two of the five 7 Series FPGA configuration modes:
• Master SPI using the on-board Quad SPI Flash memory
• JTAG using a standard-A to micro-B USB cable for connecting the host PC to the
AC701 board configuration port or via J4 Platform Cable USB/Parallel Cable IV flat
cable connector
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in Table 1-2. The mode switches M2, M1, and M0 are on SW1 positions 1,
2, and 3 respectively as shown in Figure 1-3.
17 P2, U48 HDMI Video Connector and Device Molex 500254-1927, Analog Devices
ADV7511KSTZ-P
19, 18
18 J23 LCD Character Display Connector 2 x 7 0.1 in male pin header 14
19 U52 I2C Bus Switch TI PCA9548ARGER 6
20 DS11 - DS13 Ethernet PHY Status LEDs, Green Lumex SML-LX0603GW 15
21 DS2 - DS5 User GPIO LEDs, Green Lumex SML-LX0603GW 21
22 SW3 – SW7 User Pushbuttons E-Switch E-Switch TL3301EF100QG 21
23 SW2 GPIO DIP Switch, 4-pole C&K SDA04H1SBD 21
24 SW10 User Rotary Switch Panasonic EVQ-WK4001 21
25 J33, J34 SMA User GPIO Rosenberger 32K10K-400L5 3
26 SW15 Power On/Off Slide Switch C&K 1201M2S3AQE2 38
27 SW9 FPGA_PROG_B Pushbutton Switch
(Active-Low)
E-Switch TL3301EF100QG 7
28 SW1 Configuration Mode DIP Switch, 3-pole C&K SDA03H1SBD 7
29 J30 FMC HPC Connector Samtec ASP_134486_01 24-27
30 U8, U9, U49, U53-U60 Power Management (voltage regulators front
side of board, controllers back side of board)
TI UCD90120ARGC controllers in conjunction with
various regulators
39-50
31 J19 XADC Header 2X10 0.1 in. male header 31
32 J44, J45, J46, J47 MGT TX, RX SMA Pairs Rosenberger 32K10K-400L5 3
Table 1-1: AC701 Board Component Descriptions (Cont’d)
Callout Reference Designator Component Description Notes Schematic 0381502
Page Number

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Chapter 1: AC701 Evaluation Board Features
The default mode setting is M[2:0] = 001, which selects Master SPI at board power-on.
Refer to the Configuration Options, page 68 for more information about the mode switch
SW1.
For full details on configuring the FPGA, see UG470, 7 Series FPGAs Configuration User
Guide
Encryption Key Backup Circuit
FPGA U1 implements bitstream encryption key technology. The AC701 board provides the
encryption key backup battery circuit shown in Figure 1-4. The rechargeable 1.5V lithium
button-type battery B1 is soldered to the board with the positive output connected to
FPGA U1 VCCBATT pin G14. The battery supply current IBATT specification is 150 nA max
when board power is off. B1 is charged from the VCC1V8 1.8V rail through a series diode
with a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The nominal
charging voltage is 1.62V.
X-Ref Target - Figure 1-3
Figure 1-3: SW13 Default Settings
Table 1-2: AC701 Board FPGA Configuration Modes
Configuration
Mode
SW13 DIP switch
Settings (M[2:0])
Bus
Width
CCLK
Direction
Master SPI 001 x1, x2, x4 Output
JTAG 101 x1 Not Applicable
R339
1.21K 1%
1/10W
R338
1.21K 1%
1/10W
R337
1.21K 1%
1/10W
FPGA_3V3
SW1
1
2
3
6
5
4
SDA03H1SBD
FPGA_M2
FPGA_M1
FPGA_M0
UG952_c1_03_100212

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Feature Descriptions
I/O Voltage Rails
In addition to Bank 0, there are 8 I/O banks available on the Artix-7 device. The voltages
applied to the FPGA I/O banks used by the AC701 board are listed in Table 1-3.
X-Ref Target - Figure 1-4
Figure 1-4: Encryption Key Backup Circuit
UG952_c1_04_092812
GND
2
2
1
1
B1
1.5V
Seiko
TS518SE_FL35E
2
1
3
BAS40-04
D6
40V
200 mW
NC
FPGA_VBATT
+
VCC1V8 (1.8V)
R83
4.70K 5%
1/10W
Table 1-3: FPGA Bank Voltage Rails
U1 FPGA Bank Power Supply Rail
Net Name Voltage
Bank 0 FPGA_3V3 3.3V
Bank 12 VCCO_VADJ 2.5V
Bank 13 FPGA_1V8 1.8V
Bank 14 FPGA_3V3 3.3V
Bank 15 VCCO_VADJ 2.5V
Bank 16 VCCO_VADJ 2.5V
Bank 33 FPGA_1V5 1.5V
Bank 34 FPGA_1V5 1.5V
Bank 35 FPGA_1V5 1.5V

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Chapter 1: AC701 Evaluation Board Features
DDR3 Memory Module
[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data. The SODIMM socket has a perforated EMI shield
surrounding it as seen in Figure 1-2.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Data path width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V
high-performance (HP) bank. An external 0.75V reference VTTREF is provided for data
interface banks 32 and 34. Any interface connected to these banks that requires a reference
voltage must use this FPGA voltage reference. The connections between the DDR 3
memory and the FPGA are listed in Table 1-4.
Table 1-4: DDR3 Memory Connections to the FPGA
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name
M4 DDR3_A0 98 A0
J3 DDR3_A1 97 A1
J1 DDR3_A2 96 A2
L4 DDR3_A3 95 A3
K5 DDR3_A4 92 A4
M7 DDR3_A5 91 A5
K1 DDR3_A6 90 A6
M6 DDR3_A7 86 A7
H1 DDR3_A8 89 A8
K3 DDR3_A9 85 A9
N7 DDR3_A10 107 A10/AP
L5 DDR3_A11 84 A11
L7 DDR3_A12 83 A12_BC_N
N6 DDR3_A13 119 A13
L3 DDR3_A14 80 A14
K2 DDR3_A15 78 A15
N1 DDR3_BA0 109 BA0
M1 DDR3_BA1 108 BA1
H2 DDR3_BA2 79 BA2
AB6 DDR3_D0 5 DQ0

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Feature Descriptions
AA8 DDR3_D1 7 DQ1
Y8 DDR3_D2 15 DQ2
AB5 DDR3_D3 17 DQ3
AA5 DDR3_D4 4 DQ4
Y5 DDR3_D5 6 DQ5
Y6 DDR3_D6 16 DQ6
Y7 DDR3_D7 18 DQ7
AF4 DDR3_D8 21 DQ8
AF5 DDR3_D9 23 DQ9
AF3 DDR3_D10 33 DQ10
AE3 DDR3_D11 35 DQ11
AD3 DDR3_D12 22 DQ12
AC3 DDR3_D13 24 DQ13
AB4 DDR3_D14 34 DQ14
AA4 DDR3_D15 36 DQ15
AC2 DDR3_D16 39 DQ16
AB2 DDR3_D17 41 DQ17
AF2 DDR3_D18 51 DQ18
AE2 DDR3_D19 53 DQ19
Y1 DDR3_D20 40 DQ20
Y2 DDR3_D21 42 DQ21
AC1 DDR3_D22 50 DQ22
AB1 DDR3_D23 52 DQ23
Y3 DDR3_D24 57 DQ24
W3 DDR3_D25 59 DQ25
W6 DDR3_D26 67 DQ26
V6 DDR3_D27 69 DQ27
W4 DDR3_D28 56 DQ28
W5 DDR3_D29 58 DQ29
W1 DDR3_D30 68 DQ30
V1 DDR3_D31 70 DQ31
G2 DDR3_D32 129 DQ32
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

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Chapter 1: AC701 Evaluation Board Features
D1 DDR3_D33 131 DQ33
E1 DDR3_D34 141 DQ34
E2 DDR3_D35 143 DQ35
F2 DDR3_D36 130 DQ36
A2 DDR3_D37 132 DQ37
A3 DDR3_D38 140 DQ38
C2 DDR3_D39 142 DQ39
C3 DDR3_D40 147 DQ40
D3 DDR3_D41 149 DQ41
A4 DDR3_D42 157 DQ42
B4 DDR3_D43 159 DQ43
C4 DDR3_D44 146 DQ44
D4 DDR3_D45 148 DQ45
D5 DDR3_D46 158 DQ46
E5 DDR3_D47 160 DQ47
F4 DDR3_D48 163 DQ48
G4 DDR3_D49 165 DQ49
K6 DDR3_D50 175 DQ50
K7 DDR3_D51 177 DQ51
K8 DDR3_D52 164 DQ52
L8 DDR3_D53 166 DQ53
J5 DDR3_D54 174 DQ54
J6 DDR3_D55 176 DQ55
G6 DDR3_D56 181 DQ56
H6 DDR3_D57 183 DQ57
F7 DDR3_D58 191 DQ58
F8 DDR3_D59 193 DQ59
G8 DDR3_D60 180 DQ60
H8 DDR3_D61 182 DQ61
D6 DDR3_D62 192 DQ62
E6 DDR3_D63 194 DQ63
AC6 DDR3_DM0 11 DM0
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

AC701 Evaluation Board www.xilinx.com 15
UG952 (v1.0) October 23, 2012
Feature Descriptions
AC4 DDR3_DM1 28 DM1
AA3 DDR3_DM2 46 DM2
U7 DDR3_DM3 63 DM3
G1 DDR3_DM4 136 DM4
F3 DDR3_DM5 153 DM5
G5 DDR3_DM6 170 DM6
H9 DDR3_DM7 187 DM7
W8 DDR3_DQS0_N 10 DQS0_N
V8 DDR3_DQS0_P 12 DQS0_P
AE5 DDR3_DQS1_N 27 DQS1_N
AD5 DDR3_DQS1_P 29 DQS1_P
AE1 DDR3_DQS2_N 45 DQS2_N
AD1 DDR3_DQS2_P 47 DQS2_P
V2 DDR3_DQS3_N 62 DQS3_N
V3 DDR3_DQS3_P 64 DQS3_P
B1 DDR3_DQS4_N 135 DQS4_N
C1 DDR3_DQS4_P 137 DQS4_P
A5 DDR3_DQS5_N 152 DQS5_N
B5 DDR3_DQS5_P 154 DQS5_P
H4 DDR3_DQS6_N 169 DQS6_N
J4 DDR3_DQS6_P 171 DQS6_P
G7 DDR3_DQS7_N 186 DQS7_N
H7 DDR3_DQS7_P 188 DQS7_P
R2 DDR3_ODT0 116 ODT0
U2 DDR3_ODT1 120 ODT1
N8 DDR3_RESET_B 30 RESET_B
T3 DDR3_S0_B 114 S0_B
T2 DDR3_S1_B 121 S1_B
U1 DDR3_TEMP_
EVENT 198 EVENT_B
R1 DDR3_WE_B 113 WE_B
T4 DDR3_CAS_B 115 CAS_B
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

16 www.xilinx.com AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
Chapter 1: AC701 Evaluation Board Features
Other memory interface details are available in UG586, 7 Series FPGAs Memory Interface
Solutions User Guide and UG473, 7 Series FPGAs Memory Resources User Guide
Quad-SPI Flash Memory
[Figure 1-2, callout 3]
The Quad-SPI Flash memory U7 provides 256 Mb of non-volatile storage that can be used
for configuration and data storage.
• Part number: N25Q256A13ESF40G (Numonyx)
• Supply voltage: 3.3V
• Data path width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode and CCLK rate
Four data lines and the FPGA's CCLK pin are wired to the Quad-SPI Flash memory. The
connections between the SPI Flash memory and the FPGA are listed in Table 1-5.
The configuration section of UG470, 7 Series FPGAs Configuration User Guide provides details
on using the Quad-SPI Flash memory. Figure 1-5 shows the connections of the Quad-SPI
Flash memory on the AC701 board. For more details, see the Numonyx
N25Q256A13ESF40G data sheet http://www.micron.com.
P1 DDR3_RAS_B 110 RAS_B
P4 DDR3_CKE0 73 CKE0
N4 DDR3_CKE1 74 CKE1
L2 DDR3_CLK0_N 103 CK0_N
M2 DDR3_CLK0_P 101 CK0_P
N2 DDR3_CLK1_N 104 CK1_N
N3 DDR3_CLK1_P 102 CK1_P
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name
Table 1-5: Quad-SPI Flash Memory Connections to the FPGA
U1 FPGA Pin Net Name
U7 Quad-SPI Flash Memory
Pin Number Pin Name
R14 FLASH_D0 15 DQ0
R15 FLASH_D1 8 DQ1
P14 FLASH_D2 9 DQ2
N14 FLASH_D3 1 DQ3
H13 FPGA_CCLK 16 C
P18 QSPI_IC_CS_B 7 S_B

AC701 Evaluation Board www.xilinx.com 17
UG952 (v1.0) October 23, 2012
Feature Descriptions
SPI External Programming Header
In addition to the QSPI device FPGA U1 connections shown in Table 1-5, the FPGA U1 SPI
interface is connected to an external programming header J7.
Table 1-6 shows the SPI J7 connections to FPGA U1.
Figure 1-6 shows the J7 SPI external programming connector.
X-Ref Target - Figure 1-5
Figure 1-5: 256 Mb Quad-SPI Flash memory
UG952_c1_05_101812
VCC3V3
N25Q256
256 MbSerial
Flash Memory
GND
1
2
3
5
7
6
U7
4
8
VCC3V3
C18
0.1μF 25V
X5R
FLASH_D2
DQ1
16
15
14
12
10
11
13
9
SB
NC3
NC2
NC1
NC0
VCC
HOLD_B/DQ3
WB/VPP/DQ2
VSS
NC4
NC5
NC6
NC7
DQ0
C
R17
DNP
R18
4.7kΩ5%
R431
15Ω1%
R432
15Ω1%
FLASH_D0
FPGA_CCLK
FLASH_D2_R
FLASH_D0_R
GND
VCC3V3
R20
DNP
R19
4.7kΩ5%
R21
4.7kΩ5%
R430
15Ω1%
R429
15Ω1%
FLASH_D2_R
FLASH_D3_R
FLASH_D3
FLASH_D1
QSPI_IC_CS_B
Table 1-6: SPI J7 Connections to the FPGA
U1 FPGA Pin Schematic Net
Name J7 Pin
AE16 FPGA_PROG_B 1
N14 FLASH_D3 2
P14 FLASH_D2 3
J3.2 QSPI_CS_B 4
R14 FLASH_D0 5
R15 FLASH_D1 6
H13 FPGA_CCLK 7
NA GND 8
NA VCC3V3 9

18 www.xilinx.com AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
Chapter 1: AC701 Evaluation Board Features
SD Card Interface
[Figure 1-2, callout 4]
The AC701 board includes a secure digital input/output (SDIO) interface to provide
user-logic access to general purpose non-volatile SDIO memory cards and peripherals. The
SD card slot is designed to support 50 MHz high speed SD cards.
The SDIO signals are connected to I/O bank 14 which has its VCCO set to 3.3V. Figure 1-7
shows the connections of the SD card interface on the AC701 board.
Table 1-7 lists the SD card interface connections to the FPGA.
X-Ref Target - Figure 1-6
Figure 1-6: SPI J7 External Programming Connector
UG952_c1_06_092812
VCC3V3
GND
2
3
4
6
8
7
5
9
FLASH_D3
FLASH_D2
QSPI_CS_B
FLASH_D0
FLASH_D1
FPGA_CCLK
1FPGA_PROG_B
J7
HDR
1X9
X-Ref Target - Figure 1-7
Figure 1-7: SD Card Interface
UG952_c1_07_100212
SDIO Card
Connector
U29
DETECT
DAT2
DAT1
DAT0
CLK
CMD
CD_DAT3
VDD
PROTECT
GNDTAB2VSS1
GNDTAB1
VSS2
GND
GND
SDIO_SDWP 11
SDIO_SDDET 10
SDIO_DAT2 9
SDIO_DAT1 8
SDIO_DAT0 7
SDIO_CLK 5
SDIO_CMD
1SDIO_CD_DAT3
VCC3V3
C52
0.1μF 25V
X5R
GND
4
6
3
D_P
12
GNDTAB3
GNDTAB4
IOGND1
IOGND2
15
16
17
18
13
14
51.1K 1% Eight Places
VCC3V3
R319
R325
R324
R318
R322 R323
R317
R321
2
To FPGA
Bank 14
(U1)

AC701 Evaluation Board www.xilinx.com 19
UG952 (v1.0) October 23, 2012
Feature Descriptions
Table 1-7: SDIO Connections to the FPGA
U1 FPGA Pin
Name Schematic Net Name
U29 SDIO Connector
Pin Number Pin Name
R20 SDIO_SDWP 11 SDWP
P24 SDIO_SDDET 10 SDDET
N23 SDIO_CMD 2 CMD
N24 SDIO_CLK 5 CLK
P23 SDIO_DAT2 9 DAT2
N19 SDIO_DAT1 8 DAT1
P19 SDIO_DAT0 7 DAT0
P21 SDIO_CD_DAT3 1 CD_DAT3

20 www.xilinx.com AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
Chapter 1: AC701 Evaluation Board Features
USB JTAG Module
[Figure 1-2, callout 5]
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U26) where a host computer accesses the AC701 board JTAG chain through
a standard-A plug (host side) to micro-B plug (AC701 board side) USB cable.
A 2-mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables
such as the Platform Cable USB II and the Parallel Cable IV.
The JTAG chain of the AC701 board is illustrated in Figure 1-8. JTAG configuration is
allowed at any time regardless of FPGA mode pin settings. JTAG initiated configuration
takes priority over the configuration method selected through the FPGA mode pin settings
at SW1.
When an FMC daughter card is attached to the AC701 board it is automatically added to
the JTAG chain through electronically controlled single-pole single-throw (SPST) switches
U27. The SPST switch is in a normally closed state and transitions to an open state when an
FMC daughter card is attached. Switch U27 adds an attached FMC HPC daughter card to
the FPGAs JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal.
The JTAG connectivity on the AC701 board allows a host computer to download
bitstreams to the FPGA using the Xilinx iMPACT software. In addition, the JTAG connector
allows debug tools such as the ChipScope™ Pro Analyzer or a software debugger to access
the FPGA. The iMPACT software tool can also indirectly program the Quad-SPI Flash
memory. To accomplish this, the iMPACT software configures the FPGA with a temporary
design to access and program the Quad-SPI Flash memory device. The JTAG circuit is
shown in Figure 1-9.
X-Ref Target - Figure 1-8
Figure 1-8: JTAG Chain Block Diagram
UG952_c1_08_100212
Part of U19
BUFFER
USB
Module
(U26)
or
JTAG
Connector
(J4)
TDO
TDI
U1
FPGA
TDI
TDO
FMC LPC
Connector
TDI TDO
J30
N.C.
SPST Bus Switch
U27
Part of U19
BUFFER