Xilinx Virtex UltraScale FPGA VCU1287 User manual

Virtex UltraScale FPGA
VCU1287 Characterization
Kit IBERT
Getting Started Guide
Vivado Design Suite
UG1203 (v2016.4) December 15. 2016

VCU1287 IBERT Getting Started Guide 2
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Revision History
The following table shows the revision history for this document.
Date Version Revision
12/15/2016 2016.4 Updated for Vivado Design Suite 2016.4. Design file changed to
rdf0368-vcu1287-ibert-2016-4.zip.
10/12/2016 2016.3
Updated for Vivado Design Suite 2016.3. Design file changed to
rdf0368-vcu1287-ibert-2016-3.zip. Updated Figure 1-14, Figure 1-23,
Figure 2-1, Figure 2-4, Figure 2-9, Figure 2-15, and Figure 2-20.
06/08/2016 2016.2 Updated for Vivado Design Suite 2016.2. Design file changed to
rdf0368-vcu1287-ibert-2016-2.zip.
04/13/2016 2016.1
Updated for Vivado Design Suite 2016.1. Design file
rdf0368-vcu1287-ibert-2015-4.zip changed to
rdf0368-vcu1287-ibert-2016-1.zip. Updated Figure 1-20 and Figure 1-29.
Added Training Resources in Appendix B.
02/22/2016 1.0 Initial Xilinx release.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: VCU1287 IBERT Getting Started Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting Up the VCU1287 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Running the GTH IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Running the GTY IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 2: Creating the IBERT Cores
Creating the GTH IBERT Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Creating the GTY IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Appendix A: Warranty
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Chapter 1
VCU1287 IBERT Getting Started Guide
Overview
This document describes setting up the Virtex UltraScale FPGA VCU1287 GTH and GTY
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstration are stored in a Secure Digital (SD) memory card that is provided with the
VCU1287 board. The demonstration shows the capabilities of the Virtex UltraScale
XCVU095-FFVB2104 FPGA GTH and GTY transceiver.
The VCU1287 board is described in detail in the VCU1287 Board User Guide (UG1120)
[Ref 1].
The IBERT demonstrations in this guide operate one GTH Quad and one GTY QUAD. The
procedure consists of:
1. Setting Up the VCU1287 Board, page 6
2. Extracting the Project Files, page 7
3. Connecting the GTH Transceivers and Reference Clocks, page 8
4. Starting the SuperClock-2 Module, page 13
5. Configuring the FPGA, page 16
6. Setting Up the Vivado Design Suite, page 18
7. Viewing GTH Transceiver Operation, page 24
8. Closing the IBERT Demonstration, page 25
9. Connecting the GTY Transceivers and Reference Clocks, page 26
10. Starting the SuperClock-2 Module, page 28
11. Configuring the FPGA, page 29
12. Setting Up the Vivado Design Suite, page 31
13. Viewing GTY Transceiver Operation, page 36
14. Closing the IBERT Demonstration, page 37
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Chapter 1: VCU1287 IBERT Getting Started Guide
Requirements
The hardware and software required to run the GTH and GTY IBERT demonstrations are:
• Virtex UltraScale FPGA VCU1287 GTH and GTY transceiver characterization board,
including:
°One SD card containing the IBERT demonstration designs
°One Samtec Bulls Eye™ cable
°Eight SMA female-to-female (F-F) adapters
°Six 50ΩSMA terminators
°UltraScale transceiver power supply module (installed onboard)
°SuperClock-2 module, Rev 1.0 (installed onboard)
°Active BGA heat sink (installed on FPGA)
°12V DC power adapter
°Two USB cables, standard-A plug to micro-B plug
•HostPCwith:
°SD card reader
°USB ports
• Xilinx® Vivado Design Suite 2016.4
The hardware and software required to rebuild the IBERT demonstration designs are:
• Xilinx Vivado Design Suite 2016.4
• PC with a version of the Windows operating system supported by Xilinx Vivado Design
Suite
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Chapter 1: VCU1287 IBERT Getting Started Guide
Setting Up the VCU1287 Board
This section describes how to set up the VCU1287 board.
CAUTION! The VCU1287 board can be damaged by electrostatic discharge (ESD). Follow
standard ESD prevention measures when handling the board, such as using a grounding
strap and static dissipative mat.
When the VCU1287 board ships from the factory, it is configured for the support of both
GTH and GTY IBERT demonstrations described in this document. If the board has been
re-configured, it must be returned to the default setup before running the IBERT
demonstrations.
1. Move all jumpers and switches to their default positions. The default jumper and switch
positions are listed in the VCU1287 Characterization Board User Guide (UG1121) [Ref 1].
2. Install the UltraScale transceiver power module by plugging it into connectors J124–J46
and J138.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SUPERCLOCK-2 MODULE interface of the VCU1287 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the bottom
of the VCU1287 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the CONTROL
VOLTAGE header, J18, and place another jumper across Si570 INH header J11.
d. Screw down a 50ΩSMA terminator onto each of the six unused Si5368 clock output
SMA connectors: J7, J8, J12, J15, J16, and J17.
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Chapter 1: VCU1287 IBERT Getting Started Guide
Extracting the Project Files
The Vivado Design Suite BIT files required to run the IBERT demonstrations are located in
rdf0368-vcu1287-ibert-2016-4.zip on the SD card provided with the VCU1287
board. The BIT files are also available online at the Virtex UltraScale FPGA VCU1287
Characterization Kit documentation website.
The ZIP file contains these BIT files:
• vcu1287_ibert_q124_125.bit
• vcu1287_ibert_q125_125.bit
• vcu1287_ibert_q126_125.bit
• vcu1287_ibert_q127_125.bit
• vcu1287_ibert_q128_125.bit
• vcu1287_ibert_q129_125.bit
• vcu1287_ibert_q130_125.bit
• vcu1287_ibert_q131_125.bit
• vcu1287_ibert_q224_125.bit
• vcu1287_ibert_q225_125.bit
• vcu1287_ibert_q226_125.bit
• vcu1287_ibert_q227_125.bit
• vcu1287_ibert_q228_125.bit
• vcu1287_ibert_q229_125.bit
• vcu1287_ibert_q230_125.bit
• vcu1287_ibert_q231_125.bit
To copy the files from the SD card:
1. Connect the SD card to the host computer.
2. Locate the file rdf0368-vcu1287-ibert-2016-4.zip on the SD card.
3. Unzip the files to a working directory on the host computer.
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Chapter 1: VCU1287 IBERT Getting Started Guide
Running the GTH IBERT Demonstration
The GTH IBERT demonstration operates one GTH Quad at a time. This section describes how
to test GTH Quad 224. The remaining GTH Quads can be tested following a similar series of
steps.
Connecting the GTH Transceivers and Reference Clocks
Figure 1-1 shows the locations for GTH and GTY transceiver Quads on the VCU1287 board.
Figure 1-1 is for reference only and might not reflect the current revision of the board.
Note: Quads 133, 232, and 233 are not available on the XCVU095 device.
X-Ref Target - Figure 1-1
Figure 1-1: VCU1287 GTH and GTY Quad Locations
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Chapter 1: VCU1287 IBERT Getting Started Guide
All multi-gigabit transceiver (MGT) pins and reference clock pins are routed from the FPGA
to a connector pad that interfaces with Samtec Bulls Eye connectors. Figure 1-2 Ashows the
connector pad. Figure 1-2 Bshows the connector pinout.
The SuperClock-2 module provides LVDS clock outputs for the MGT transceiver reference
clocks in the IBERT demonstrations. Figure 1-3 shows the locations of the differential clock
SMA connectors on the clock module which can be connected to the reference clock cables.
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note: The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
SuperClock-2 module.
For more information on the SuperClock-2 module, see the HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770) [Ref 2].
X-Ref Target - Figure 1-2
Figure 1-2: A—MGT Connector Pad. B—MGT Connector Pinout
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
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Attach the GTH Quad Connector
Before connecting the Bulls Eye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if
it is not already inserted (see Figure 1-4).
Note: Figure 1-4 is for reference only and might not reflect the current version of the connector.
Attach the Samtec Bulls Eye connector to GTH Quad 224 (Figure 1-5), aligning the two
indexing pins on the bottom of the connector with the guide holes on the board. Hold the
connector flush with the board and fasten it by tightening the two captive screws.
X-Ref Target - Figure 1-4
Figure 1-4: Bulls Eye Connector with Elastomer Seal
X-Ref Target - Figure 1-5
Figure 1-5: Bulls Eye Connector Attached to Quad 224
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GTH Transceiver Clock Connections
See Figure 1-2 to identify the P and N coax cables that are connected to the CLK0 reference
clock inputs. Connect these cables to the SuperClock-2 module as follows:
• CLK0_P coax cable → SMA connector J7 (CLKOUT1_P) on the SuperClock-2 module
• CLK0_N coax cable → SMA connector J8 (CLKOUT1_N) on the SuperClock-2 module
Note: Any one of the five differential outputs from the SuperClock-2 module can be used to source
the GTH reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
MGT TX/RX Loopback Connections
See Figure 1-2 to identify the P and N coax cables that are connected to the four receivers
(RX0, RX1, RX2, and RX3) and the four transmitters (TX0, TX1, TX2, and TX3). Use eight SMA
female-to-female (F-F) adapters (Figure 1-6) to connect the transmit and receive cables as
shown in Figure 1-7:
•TX0_P→ SMA F-F Adapter → RX0_P
•TX0_N→ SMA F-F Adapter → RX0_N
•TX1_P→ SMA F-F Adapter → RX1_P
•TX1_N→ SMA F-F Adapter → RX1_N
•TX2_P→ SMA F-F Adapter → RX2_P
•TX2_N→ SMA F-F Adapter → RX2_N
•TX3_P→ SMA F-F Adapter → RX3_P
•TX3_N→ SMA F-F Adapter → RX3_N
Note: To ensure good connectivity, it is recommended that the adapters be secured with a wrench;
however, do not over-tighten the SMAs.
X-Ref Target - Figure 1-6
Figure 1-6: SMA F-F Adapter
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Chapter 1: VCU1287 IBERT Getting Started Guide
Figure 1-8 shows the VCU1287 board with the cable connections required for the Quad 224
GTH IBERT demonstration.
X-Ref Target - Figure 1-7
Figure 1-7: TX-to-RX Loopback Connection Example
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X-Ref Target - Figure 1-8
Figure 1-8: Cable Connections for Quad 224 GTH IBERT Demonstration
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Chapter 1: VCU1287 IBERT Getting Started Guide
Starting the SuperClock-2 Module
The SuperClock-2 module features two clock-source components:
• Always-on Si570 crystal oscillator
• Si5368 jitter-attenuating clock multiplier
Outputs from either source can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. The SuperClock-2 module is configured using the Xilinx XC7Z010CLG225
Zynq-7000APSoC System Controller command line which can be accessed through a
serial communication terminal connection using the enhanced communication port of
the Silicon Labs USB to Dual UART Bridge (Figure 1-9). Additional information about the
Silicon Labs USB-to-UART is available in Silicon Labs CP210x USB-to-UART Installation
Guide (UG1033) [Ref 3].
Review the VCU1287 Evaluation Board User Guide (UG1120) [Ref 1] for additional
information about the System Controller.
2. Set the System Controller configuration DIP switches (SW13) to the OFF position
(Figure 1-10). This disables configuration of the FPGA at power reset.
X-Ref Target - Figure 1-9
Figure 1-9: Silicon Labs Enhanced COM PORT
X-Ref Target - Figure 1-10
Figure 1-10: Configuration DIP Switch (SW13)
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ENABLE
ADDR0
ADDR1
ADDR2
ADDR3
ON
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Chapter 1: VCU1287 IBERT Getting Started Guide
3. Connect J1 connector (USB/UART) on the VCU1287 board to the host computer using
one of the standard-A plug to micro-B plug USB cables provided (Figure 1-11) and
power up the board by placing SW1 in the ON position.
4. Open a serial communication terminal application on the host computer, for example
“HyperTerminal”, and connect to the port number associated with the enhanced COM
port of the Silicon Lab USB-UART Bridge. Set up a new connection as in Figure 1-12, and
press the Return key to connect to view the System Controller options menu.
X-Ref Target - Figure 1-11
Figure 1-11: USB-UART Connector
X-Ref Target - Figure 1-12
Figure 1-12: Terminal Setting
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5. From the main System Controller menu, select option (1) to access the SuperClock-2
options:
VCU1287 System Controller v1.0
- Main Menu -
-----------------------------
1. Set Programmable Clocks
2. Get Power System (PMBUS) Voltages
3. Get Power Monitoring Data (INA226)
4. Adjust FPGA Mezzanine Card (FMC) Settings
5. Get GPIO Data
6. Get EEPROM Data
7. Configure UltraScale FPGA
Select an option
6. Use the Programmable Clocks menu option (2) to set the output clock frequencies of
the Si5368 clocks to 125 MHz.
VCU1287 System Controller v1.0
- Clock Menu -
-----------------------------
1. Set VCU1287 Si570 Frequency
2. Set VCU1287 Si5368 Frequency
3. Save VCU1287 Clock Frequency to EEPROM
4. Restore VCU1287 Clock Frequency from EEPROM
5. View VCU1287 Saved Clocks in EEPROM
6. Set VCU1287 Clock Restore Options
7. Read VCU1287 Si570 Frequency
8. Read VCU1287 Si5368 Frequency
0. Return to Main Menu
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Select an option
7. Select option 2 (Free-Run crystal) operating mode when prompted.
Choose si5368 operating mode:
1 - Auto-Select
2 - Free-Run using XA-XB crystal
Configuring the FPGA
The VCU1287 board additionally utilizes the Xilinx XC7Z010CLG225 Zynq-7000 AP SoC
System Controller to implement a System Integrated Configuration Engine (System ICE) to
configure the FPGA using one of the configuration *.bit files provided on the SD card in
8-bit SMAP configuration mode.
The FPGA can also be configured through the Vivado Design Suite using the *.bit files
available on the SD card and online (as collection
rdf0368-vcu1287-ibert-2016-4.zip )
at the Virtex UltraScale FPGA VCU1287 Characterization Kit documentation website.
Review UltraScale Architecture Configuration User Guide (UG570) [Ref 4] for additional
information about UltraScale device configuration.
1. Insert the SD card provided with the VCU1287 board into the SD card reader slot located
on the bottom-side (upper-right corner) of the VCU1287 board.
2. From the main System Controller menu, select option (7) to access the UltraScale FPGA
configuration options:
VCU1287 System Controller v1.0
- Main Menu -
-----------------------------
1. Set Programmable Clocks
2. Get Power System (PMBUS) Voltages
3. Get Power Monitoring Data (INA226)
4. Adjust FPGA Mezzanine Card (FMC) Settings
5. Get GPIO Data
6. Get EEPROM Data
7. Configure UltraScale FPGA
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Chapter 1: VCU1287 IBERT Getting Started Guide
Select an option
3. Select option (1) to configure the FPGA from the SD card:
VCU1287 System Controller
- CONFIG Menu -
-----------------------------
1. Configure UltraScale FPGA from SD Card
0. Return to Main Menu
Select an option
The IBERT design demonstrations included with the SD cards can be selected using one
of the set numbers listed in Table 1-1.
Table 1-1: IBERT Examples Bitstream Number
IBERT Demonstration Design Bitstream Number
QUAD_124 0
QUAD_125 1
QUAD_126 2
QUAD_127 3
QUAD_128 4
QUAD_129 5
QUAD_130 6
QUAD_131 7
QUAD_224 8
QUAD_225 9
QUAD_226 10
QUAD_227 11
QUAD_228 12
QUAD_229 13
QUAD_230 14
QUAD_231 15
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Chapter 1: VCU1287 IBERT Getting Started Guide
4. Select option (8) to configure the FPGA with the Quad 224 IBERT example design. Press
Enter and review the terminal for configuration progress:
Enter a Bitstream number (0-15):
8
Info: xilinx.sys opened
Info: Opening rev_1/set8/config.def
Info: Configuration definition file "rev_1/set8/config.def" opened
Info: Clock divider is set to 2
Info: Configuration clock frequency is 25MHz
Info: Bitfile "rev_1/set8/vu95Q224.bit" opened
...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
Configuration completed successfully
Setting Up the Vivado Design Suite
1. Connect the host computer to the VCU1287 board using the second standard-A plug to
micro-B plug USB cable. The standard-A plug connects to a USB port on the host
computer and the micro-B plug connects to J165, the Digilent USB JTAG configuration
port on the VCU1287 board (Figure 1-13).
X-Ref Target - Figure 1-13
Figure 1-13: JTAG Connector
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Chapter 1: VCU1287 IBERT Getting Started Guide
2. Start the Vivado Design Suite on the host computer and click Flow > Open Hardware
Manager (highlighted in Figure 1-14).
X-Ref Target - Figure 1-14
Figure 1-14: Vivado Design Suite, Open Hardware Manager
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3. In the Hardware Manager window (Figure 1-15), click Open New Target.
4. An Open Hardware Target wizard opens. Click Next in the first window.
5. In the Hardware Server Settings window, select Local server (target is on local
machine). Click Next.
X-Ref Target - Figure 1-15
Figure 1-15: Open a New Hardware Manager
X15554-121416
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