Xilinx Virtex UltraScale FPGA VCU1287 User manual

Virtex UltraScale FPGA
VCU1287 Characterization
Kit IBERT
Getting Started Guide
Vivado Design Suite
UG1203 (v2016.4) December 15. 2016

VCU1287 IBERT Getting Started Guide 2
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Revision History
The following table shows the revision history for this document.
Date Version Revision
12/15/2016 2016.4 Updated for Vivado Design Suite 2016.4. Design file changed to
rdf0368-vcu1287-ibert-2016-4.zip.
10/12/2016 2016.3
Updated for Vivado Design Suite 2016.3. Design file changed to
rdf0368-vcu1287-ibert-2016-3.zip. Updated Figure 1-14, Figure 1-23,
Figure 2-1, Figure 2-4, Figure 2-9, Figure 2-15, and Figure 2-20.
06/08/2016 2016.2 Updated for Vivado Design Suite 2016.2. Design file changed to
rdf0368-vcu1287-ibert-2016-2.zip.
04/13/2016 2016.1
Updated for Vivado Design Suite 2016.1. Design file
rdf0368-vcu1287-ibert-2015-4.zip changed to
rdf0368-vcu1287-ibert-2016-1.zip. Updated Figure 1-20 and Figure 1-29.
Added Training Resources in Appendix B.
02/22/2016 1.0 Initial Xilinx release.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: VCU1287 IBERT Getting Started Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting Up the VCU1287 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Running the GTH IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Running the GTY IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 2: Creating the IBERT Cores
Creating the GTH IBERT Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Creating the GTY IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Appendix A: Warranty
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Chapter 1
VCU1287 IBERT Getting Started Guide
Overview
This document describes setting up the Virtex UltraScale FPGA VCU1287 GTH and GTY
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstration are stored in a Secure Digital (SD) memory card that is provided with the
VCU1287 board. The demonstration shows the capabilities of the Virtex UltraScale
XCVU095-FFVB2104 FPGA GTH and GTY transceiver.
The VCU1287 board is described in detail in the VCU1287 Board User Guide (UG1120)
[Ref 1].
The IBERT demonstrations in this guide operate one GTH Quad and one GTY QUAD. The
procedure consists of:
1. Setting Up the VCU1287 Board, page 6
2. Extracting the Project Files, page 7
3. Connecting the GTH Transceivers and Reference Clocks, page 8
4. Starting the SuperClock-2 Module, page 13
5. Configuring the FPGA, page 16
6. Setting Up the Vivado Design Suite, page 18
7. Viewing GTH Transceiver Operation, page 24
8. Closing the IBERT Demonstration, page 25
9. Connecting the GTY Transceivers and Reference Clocks, page 26
10. Starting the SuperClock-2 Module, page 28
11. Configuring the FPGA, page 29
12. Setting Up the Vivado Design Suite, page 31
13. Viewing GTY Transceiver Operation, page 36
14. Closing the IBERT Demonstration, page 37
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Chapter 1: VCU1287 IBERT Getting Started Guide
Requirements
The hardware and software required to run the GTH and GTY IBERT demonstrations are:
• Virtex UltraScale FPGA VCU1287 GTH and GTY transceiver characterization board,
including:
°One SD card containing the IBERT demonstration designs
°One Samtec Bulls Eye™ cable
°Eight SMA female-to-female (F-F) adapters
°Six 50ΩSMA terminators
°UltraScale transceiver power supply module (installed onboard)
°SuperClock-2 module, Rev 1.0 (installed onboard)
°Active BGA heat sink (installed on FPGA)
°12V DC power adapter
°Two USB cables, standard-A plug to micro-B plug
•HostPCwith:
°SD card reader
°USB ports
• Xilinx® Vivado Design Suite 2016.4
The hardware and software required to rebuild the IBERT demonstration designs are:
• Xilinx Vivado Design Suite 2016.4
• PC with a version of the Windows operating system supported by Xilinx Vivado Design
Suite
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Chapter 1: VCU1287 IBERT Getting Started Guide
Setting Up the VCU1287 Board
This section describes how to set up the VCU1287 board.
CAUTION! The VCU1287 board can be damaged by electrostatic discharge (ESD). Follow
standard ESD prevention measures when handling the board, such as using a grounding
strap and static dissipative mat.
When the VCU1287 board ships from the factory, it is configured for the support of both
GTH and GTY IBERT demonstrations described in this document. If the board has been
re-configured, it must be returned to the default setup before running the IBERT
demonstrations.
1. Move all jumpers and switches to their default positions. The default jumper and switch
positions are listed in the VCU1287 Characterization Board User Guide (UG1121) [Ref 1].
2. Install the UltraScale transceiver power module by plugging it into connectors J124–J46
and J138.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SUPERCLOCK-2 MODULE interface of the VCU1287 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the bottom
of the VCU1287 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the CONTROL
VOLTAGE header, J18, and place another jumper across Si570 INH header J11.
d. Screw down a 50ΩSMA terminator onto each of the six unused Si5368 clock output
SMA connectors: J7, J8, J12, J15, J16, and J17.
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Chapter 1: VCU1287 IBERT Getting Started Guide
Extracting the Project Files
The Vivado Design Suite BIT files required to run the IBERT demonstrations are located in
rdf0368-vcu1287-ibert-2016-4.zip on the SD card provided with the VCU1287
board. The BIT files are also available online at the Virtex UltraScale FPGA VCU1287
Characterization Kit documentation website.
The ZIP file contains these BIT files:
• vcu1287_ibert_q124_125.bit
• vcu1287_ibert_q125_125.bit
• vcu1287_ibert_q126_125.bit
• vcu1287_ibert_q127_125.bit
• vcu1287_ibert_q128_125.bit
• vcu1287_ibert_q129_125.bit
• vcu1287_ibert_q130_125.bit
• vcu1287_ibert_q131_125.bit
• vcu1287_ibert_q224_125.bit
• vcu1287_ibert_q225_125.bit
• vcu1287_ibert_q226_125.bit
• vcu1287_ibert_q227_125.bit
• vcu1287_ibert_q228_125.bit
• vcu1287_ibert_q229_125.bit
• vcu1287_ibert_q230_125.bit
• vcu1287_ibert_q231_125.bit
To copy the files from the SD card:
1. Connect the SD card to the host computer.
2. Locate the file rdf0368-vcu1287-ibert-2016-4.zip on the SD card.
3. Unzip the files to a working directory on the host computer.
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Chapter 1: VCU1287 IBERT Getting Started Guide
Running the GTH IBERT Demonstration
The GTH IBERT demonstration operates one GTH Quad at a time. This section describes how
to test GTH Quad 224. The remaining GTH Quads can be tested following a similar series of
steps.
Connecting the GTH Transceivers and Reference Clocks
Figure 1-1 shows the locations for GTH and GTY transceiver Quads on the VCU1287 board.
Figure 1-1 is for reference only and might not reflect the current revision of the board.
Note: Quads 133, 232, and 233 are not available on the XCVU095 device.
X-Ref Target - Figure 1-1
Figure 1-1: VCU1287 GTH and GTY Quad Locations
X15535-121416
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Chapter 1: VCU1287 IBERT Getting Started Guide
All multi-gigabit transceiver (MGT) pins and reference clock pins are routed from the FPGA
to a connector pad that interfaces with Samtec Bulls Eye connectors. Figure 1-2 Ashows the
connector pad. Figure 1-2 Bshows the connector pinout.
The SuperClock-2 module provides LVDS clock outputs for the MGT transceiver reference
clocks in the IBERT demonstrations. Figure 1-3 shows the locations of the differential clock
SMA connectors on the clock module which can be connected to the reference clock cables.
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note: The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
SuperClock-2 module.
For more information on the SuperClock-2 module, see the HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770) [Ref 2].
X-Ref Target - Figure 1-2
Figure 1-2: A—MGT Connector Pad. B—MGT Connector Pinout
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
X15541-121416
X15542-121416
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Chapter 1: VCU1287 IBERT Getting Started Guide
Attach the GTH Quad Connector
Before connecting the Bulls Eye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if
it is not already inserted (see Figure 1-4).
Note: Figure 1-4 is for reference only and might not reflect the current version of the connector.
Attach the Samtec Bulls Eye connector to GTH Quad 224 (Figure 1-5), aligning the two
indexing pins on the bottom of the connector with the guide holes on the board. Hold the
connector flush with the board and fasten it by tightening the two captive screws.
X-Ref Target - Figure 1-4
Figure 1-4: Bulls Eye Connector with Elastomer Seal
X-Ref Target - Figure 1-5
Figure 1-5: Bulls Eye Connector Attached to Quad 224
X15543-121416
X15544-121416
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