Xilinx Zynq UltraScale+ ZCU208 User manual

Zynq UltraScale+ RFSoC
ZCU208 and ZCU216 RF
Data Converter Evaluaon
Tool
User Guide
UG1433 (v1.2) October 27, 2021
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Revision History
The following table shows the revision history for this document.
Section Revision Summary
10/27/2021 Version 1.2
Chapter 3: Hardware Design Added time division duplex (TDD) power up/down block
information.
TDD Control Block Added new section.
Appendix B: Command List Added new commands.
06/23/2020 Version 1.1
General updates. Added ZCU208 board information throughout.
RF-ADC DDR Added information on dual RF-ADC tiles.
User Space Components Added note to refer to appendix.
Software Build Revised the steps for making the SD card images and
copying files to the SD card.
Appendix A: Software Design Notes — Multimaster Access
of CLK104 on TCA9548 Multiplexer Added appendix.
Appendix B: Command List
Removed SetSignalDetector and GetSignalDetector
commands. Revised description for RfclkWriteReg. Added
GetExtParentClkList, GetExtParentClkConfig, SetMMCMFin,
GetMMCMFin, and GetMTS_Setup commands.
03/23/2020 Version 1.0
Initial release. N/A
Revision History
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Chapter 2: Overview......................................................................................................6
Installation................................................................................................................................... 7
Chapter 3: Hardware Design.................................................................................... 8
Block RAM Generation and Capture......................................................................................... 9
RF-DAC DDR............................................................................................................................... 10
RF-ADC DDR............................................................................................................................... 10
Clocking Scheme....................................................................................................................... 12
TDD Control Block..................................................................................................................... 13
Chapter 4: Software Design and Build.............................................................. 18
Software Architecture............................................................................................................... 18
User Space Components.......................................................................................................... 19
Kernel Space Components.......................................................................................................20
Software Build............................................................................................................................21
Chapter 5: Protocol Specifications...................................................................... 23
Protocol Overview..................................................................................................................... 23
Protocol Rules............................................................................................................................24
Socket Interface.........................................................................................................................25
Appendix A: Software Design Notes — Multimaster Access of
CLK104 on TCA9548 Multiplexer....................................................................... 26
Appendix B: Command List..................................................................................... 27
Appendix C: Additional Resources and Legal Notices............................. 34
Xilinx Resources.........................................................................................................................34
Documentation Navigator and Design Hubs.........................................................................34
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References..................................................................................................................................34
Please Read: Important Legal Notices................................................................................... 35
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Chapter 1
Introduction
The Zynq® UltraScale+™ RFSoC RF Data Converter (DC) Evaluaon Tool and the ZCU208 and
ZCU216 Evaluaon Kits are the ideal combinaon of evaluaon soware and test plaorm to
facilitate cung edge applicaon development. The evaluaon tool can be used to jump start
RF-class analog designs and to demonstrate the capabilies and excellent performance of the
Gen 3 RF data converters. Advantages of using this tool include acceleraon of the product
design cycle, reducon of product go-to-market expense, and quicker revenue realizaon.
Chapter 1: Introduction
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Chapter 2
Overview
The evaluaon tool enables control of the ZCU208 and ZCU216 RF DC IPs (see Zynq UltraScale+
RFSoC RF Data Converter LogiCORE IP Product Guide (PG269)) and associated designs from a host
computer. The tool allows the exploraon of RF conguraons, generaon and capture of RF
data, and observaon of key RF metrics.
The following gure shows the evaluaon tool and test plaorm overview.
Figure 1: Evaluation Tool and Test Platform Overview
X24062-062220
The tool is built from these components:
•ZCU208 Evaluaon Board User Guide (UG1410)
•ZCU216 Evaluaon Board User Guide (UG1390)
• FPGA hardware design (see Chapter 3: Hardware Design)
• FPGA embedded soware design (see Chapter 4: Soware Design and Build)
• GUI (see RF Data Converter Interface User Guide (UG1309))
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• Protocol used to communicate between the host computer (GUI) and the soware design (see
Chapter 5: Protocol Specicaons)
Installation
See the RF DC Evaluaon Tool for ZCU208 Board Quick Start or the RF DC Evaluaon Tool for
ZCU216 Board Quick Start website for installaon and folder structure informaon.
Chapter 2: Overview
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Chapter 3
Hardware Design
The Vivado® Design Suite project used to build this programmable logic (PL) design is located in
the install directory in the pl folder. The hardware design architecture is based on the RF
analyzer architecture (see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide
(PG269)). Notable addions to this architecture include:
• MicroBlaze™ is replaced by the Cortex®-A53
• PL DDR4 support, including DMA, AXI4-Stream broadcaster and switch, and GPIO control
• Clocking scheme to support DDR4 and mul-le synchronizaon
• I2C connecon to control external clocks (CLK104, see ZCU208 Evaluaon Board User Guide
(UG1410) and ZCU216 Evaluaon Board User Guide (UG1390))
• Time division duplex (TDD) power up/down block to control the TDD real-me signal (RTS)
pins of ADCs and DACs
The following gure shows the high-level hardware architecture.
Chapter 3: Hardware Design
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Figure 2: High-level Hardware Architecture
M_AXIS_03
M_AXIS_10
M_AXIS_11
M_AXIS_12
M_AXIS_00
M_AXIS_01
M_AXIS_02
M_AXIS_13
s00_0
s01_0
s02_0
s03_0
s10_0
s11_0
s12_0
s13_0
user_select_00_0
user_select_01_0
user_select_02_0
user_select_03_0
user_select_10_0
user_select_11_0
user_select_12_0
user_select_13_0
m00_0
m01_0
m02_0
m03_0
m10_0
m11_0
m12_0
m13_0
m20_0
m21_0
m22_0
m23_0
m30_0
m31_0
m32_0
m33_0
S10_AXIS
S11_AXIS
S12_AXIS
S13_AXIS
S20_AXIS
S21_AXIS
S22_AXIS
S23_AXIS
S30_AXIS
S31_AXIS
S32_AXIS
S33_AXIS
S00_AXIS
S01_AXIS
S02_AXIS
S03_AXIS
DAC_DMA_DDR RF_Analyzer
ADC_DDR_DMA
Dout[0:0]
Dout1[0:0]
Dout2[0:0]
Dout3[0:0]
Dout4[0:0]
Dout5[0:0]
Dout6[0:0]
Dout7[0:0]
GPIO_DDR_SWITCH
X23663-012320
Block RAM Generation and Capture
The block RAM generaon and capture are described in the "RF Analyzer" secon in the Zynq
UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269).
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RF-DAC DDR
A DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (PG150)) is instanated to control the external DDR4 memory. It connects to an
AXI DMA controller (see AXI DMA LogiCORE IP Product Guide (PG021)). The waveform loaded
into the DDR4 memory is then broadcast to the RF-DAC les selected by the AXI GPIO (see AXI
GPIO LogiCORE IP Product Guide (PG144)). The GPIO connects to the user_select input of the
block RAM generaon and eecvely bypasses this block when user_select is High.
For crossing clock domains, the broadcasng is done in two steps. The rst step is part of the
DDR clock domain and the second step is part of the RF-DAC le clock domain. The RF-DAC
DDR block architecture is illustrated in the following gure.
Figure 3: RF-DAC DDR Block Architecture
S_AXIS
S_AXIS1
S_AXIS2
S_AXIS3
M00_AXIS
M01_AXIS
M02_AXIS
M03_AXIS
M00_AXIS1
M01_AXIS1
M02_AXIS1
M03_AXIS1
M00_AXIS2
M01_AXIS2
M02_AXIS2
M03_AXIS2
M00_AXIS3
M01_AXIS3
M02_AXIS3
M03_AXIS3
Broadcast_stg2
M_AXIS0
M_AXIS1
M_AXIS2
M_AXIS3
M_AXIS4
M_AXIS5
M_AXIS6
M_AXIS7
M_AXIS8
M_AXIS9
M_AXIS10
M_AXIS11
M_AXIS12
M_AXIS13
M_AXIS14
M_AXIS15
S_AXIS
S_AXIS1
S_AXIS2
S_AXIS3
M_AXIS
M_AXIS1
M_AXIS2
M_AXIS3
Clock_Crossing
S_AXIS
M00_AXIS
M01_AXIS
M02_AXIS
M03_AXIS
axis_inter_dac_stg1
S01_AXI
S00_AXI M00_AXI
broadcast_interconnect
C0_DDR4_S_AXI
dbg_clk
dbg_bus[511:0]
c0_ddr4_ul_clk_sync_rst
ddr4_0
S_AXI_LITE
M_AXI_SG
M_AXI_MM2S
M_AXIS_MM2S
axi_dma_0
S_AXI_PS_DDR
S_AXI_DMA_CTRL
AXI SmartConect (Pre-Production) DDR4 SDRAM (MIG) (Pre-Production)
AXI4-Stream Broadcaster
(Pre-Production)
AXI Direct Memory Access
(Pre-Production)
S_AXI_SG_DAC
X23664-012320
RF-ADC DDR
A DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (PG150)) is instanated to control the external DDR4 memory. The RF-ADC
output is duplicated on the output of the RF analyzer block RAM capture block. An AXI4-Stream
interconnect is then used as a switch to select which RF-ADC waveform is fed into the DMA and
captured into the DDR memory. To allow the soware to control the DMA accurately, a TLAST
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block is created. This block generates a TLAST pulse so that the DMA generates an interrupt
aer the correct number of samples. Because the dual RF-ADC les have two AXI4-Stream
outputs in I/Q mode, an AXI4-Stream combiner is used to write both streams in the DDR
memory. Consequently, the real mode cannot be used to capture the dual RF-ADC les in the
DDR. The RF-ADC DDR block architecture is shown in the following gures.
Figure 4: RF-ADC DDR Block Architecture for Quad RF-ADC Tiles
S00_AXIS
S01_AXIS
S02_AXIS
S03_AXIS
S04_AXIS
S05_AXIS
S06_AXIS
S07_AXIS1
S08_AXIS2
S09_AXIS2
S10_AXIS2
S11_AXIS2
S12_AXIS3
S13_AXIS3
S14_AXIS3
S15_AXIS3
S_AXI_CTRL
axis_inter_adc
S_AXIS0
S_AXIS1
S_AXIS2
S_AXIS3
S_AXIS4
S_AXIS5
S_AXIS6
S_AXIS7
S_AXIS8
S_AXIS9
S_AXIS10
S_AXIS11
S_AXIS12
S_AXIS13
S_AXIS14
S_AXIS15
S_AXI_CTRL s_axis
s00_AXI m_axis
tlast_gen_v1_0_0
S_AXI_LITE
S_AXIS_S2MM
M_AXI_SG
M_AXI_S2MM
axi_dma_0
tlast_gen_v1_0
(Pre-Production)
AXI Direct Memory Access)
(Pre-Production)
S00_AXI
S01_AXI M00_AXI
smartconnect_0
C0_DDR4_S_AXI
dbg_clk
dbg_bus[511:0]
c0_ddr4_ul_clk_sync_rst
ddr4_adc
AXI SmartConect (Pre-Production) DDR4 SDRAM (MIG)
(Pre-Production)
S00_ARB_REQ_SUPPRESS
S01_ARB_REQ_SUPPRESS
S02_ARB_REQ_SUPPRESS
S03_ARB_REQ_SUPPRESS
S04_ARB_REQ_SUPPRESS
S05_ARB_REQ_SUPPRESS
S06_ARB_REQ_SUPPRESS
S07_ARB_REQ_SUPPRESS
S08_ARB_REQ_SUPPRESS
S09_ARB_REQ_SUPPRESS
S10_ARB_REQ_SUPPRESS
S11_ARB_REQ_SUPPRESS
S12_ARB_REQ_SUPPRESS
S13_ARB_REQ_SUPPRESS
S14_ARB_REQ_SUPPRESS
S15_ARB_REQ_SUPPRESS
M00_AXIS S_AXI_SG_ADC
s_axi_dma_adc
s00_axi
s_axi_
ps_adc_ddr
AXI4-Stream Interconnect
(Pre-Production)
X23665-012320
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Figure 5: RF-ADC DDR Block Architecture for Dual RF-ADC Tiles
X23874-042220
Clocking Scheme
The clocking scheme is built to support both individual le clocks and independent RF-ADC or
RF-DAC mul-le synchronizaon (MTS). Consequently, two of the typical clocking schemes
from the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) are
merged. The rst clocking scheme uses the output of each le to connect to a mixed-mode clock
manager (MMCM) or phase-locked loop (PLL), which gives an independent clock per le. The
second clocking scheme supports MTS, takes its input from a fabric pin, and generates an output
for the les selected by the MTS funcons. BUFGMUX and MMCM dual input allows merging
these two clocking schemes. For the RF-ADC, a mixture of MMCM and PLL are used. The RF-
ADC clocking scheme gure shows a representaon for two les. The RF-DAC clocking scheme
gure shows a representaon for two les. For the RF-DAC, only the MMCM is used. The path
used in the MTS case is shown in red.
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Figure 6: RF-ADC Clocking Scheme
PLL
Clk from Tile 1
BUFGMUX
MMCM
Clk from Tile 0
BUFGMUX
Clk from Pin
RF-ADC
Tile 2
RF-ADC
Tile 0
X23666-052820
Figure 7: RF-DAC Clocking Scheme
MMCM
Clk from Tile 1
MMCM
Clk from Tile 0
Clk from Pin
RF-DAC
Tile 2
RF-DAC
Tile 0
X23667-052820
TDD Control Block
The TDD control hardware block demonstrates the TDD power up/down of each ADC and DAC
channel. The block can be used as a reference on how to drive the real-me signal TDD pins,
power and performance measurements, and debugging. The block has the following features:
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• A set of two counters determine the number of symbols per frame and the number of frames
• The number of symbols is programmable, and the number of frames is always 10
• A map of downlink/uplink determine which TDD pins are asserted (DAC or ADC)
• A programmable guard band is possible
• Two trigger modes for the ADC: immediate or programmable
• The ADC programmable trigger can select the frame and symbol
• A programmable delay can be added on the trigger, available in each le
The following gure shows a representaon of the frame and symbol composion.
Figure 8: Frames and Symbols Representation
Guard Band Guard BandDL/UL DL/UL Guard Band Guard BandDL/UL DL/UL
Frame #9 of N Symbols Frame #10 of N Symbols
Frame #1 of N Symbols Frame #2 of N Symbols
X25676-083021
Block Diagram
The TDD control block diagram is shown in the following gure.
Figure 9: TDD Control Block
Trigger Decoder
Arm Trigger &
Enable
AXI Registers
Symbol
Length
Terminal
Count
Decoder
Cross Clock
Domain and Delay
Frame
Counter
Triggers to Capture Memories
Symbol
Counter TDD RTS Pins to ADC/DAC
Guard Length
DL/UL Map
X25660-081321
Ports
The following table lists the TDD control block ports.
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Table 1: Ports
Port Name I/O Clock Description
S00_AXI AXI port S00_AXI_ACLK AXI control port
DACx_CLK In DAC AXI4-Stream clock
ADCx_CLK In ADC AXI4-Stream clock
DACxx_tdd_mode Out S00_AXI_ACLK Connect to DACxx TDD mode pin
ADCxx_tdd_mode Out S00_AXI_ACLK Connect to ADCxx TDD mode pin
Hw_trigger_en_x Out ADC AXI4-Stream clock Enable external trigger on capture block
Trigger_x Out ADC AXI4-Stream clock External trigger
Trigger_ext Out Dac0_clk External trigger for DAC
Register Map
The TDD control block register map is listed in the following table.
Table 2: Register Map
Address Description
0x0 DAC TDD mode pin, bit n: DAC channel n
0x4 ADC TDD mode pin, bit n: ADC channel n
0x8 Bit 0: reset, others: reserved
0xC Bit 0 to 3: ADC hw_trigger_en control
0x10 Symbol to trigger on
0x14 Frame to trigger on
0x18 Arm the trigger
0x30 Tile 0 trigger delay
0x34 Tile 1 trigger delay
0x38 Tile 2 trigger delay
0x3C Tile 3 trigger delay
0x44 Slot length (unused)
0x48 Guard band length
0x4C Symbol length
0x50 Symbol type
Example Usage
The soware commands are documented in Appendix B: Command List. The commands can be
entered into the Command log window of the RF Evaluaon tool GUI (RF Data Converter Interface
User Guide (UG1309). The following examples show the command sequences for DAC and ADC,
respecvely.
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DAC Example
1. Write 1 into the DAC/ADC TDD mode pin register.
• SetTDDRTSPinCtrl 1 0x0001 enables the TDD on DAC le 0 channel 0.
• SetTDDRTDPinCtrl DAC/ADC Channel_mask to 1 for DAC and 0 for ADC. Channel mask
bit 0 = DAC0, bit 1 DAC1, etc.
2. Write the symbol length, guard band length, and symbol type registers.
• SetTDDRTSSlot 0 1000 0x01f: guard band 0, symbol length 1000, half DL, half UL.
3. At this stage, the channels selected in step 1 are operang in TDD mode.
4. An immediate trigger can be issued.
5. To stop the TDD RTS pin asseron/deasseron, SetTDDRTSPinCtrl 10x0000
The following gure shows a representaon of the frames in the DAC example.
Figure 10: DAC Example Frames and Symbols Representation
DL DLDL DL
Frame #1 of
N Symbols
DL
Frame #2 of
N Symbols
Frame #3 of
N Symbols
Frame #4 of
N Symbols
Frame #5 of
N Symbols
UL ULUL UL
Frame #6 of
N Symbols
UL
Frame #7 of
N Symbols
Frame #8 of
N Symbols
Frame #9 of
N Symbols
Frame #10 of
N Symbols
X25677-083021
Dual ADC Example
1. Write the symbol length, guard band length, and symbol type registers.
• SetTDDRTSSlot 0 1000 0x01f: guard band 0, symbol length 1000, half DL, half UL.
2. Write 1 into the ADC TDD mode pin register.
• SetTDDRTSPinCtrl 0 0x0030 enables the TDD on ADC le 1 channel 0 for dual ADC.
• As the ADC is a dual ADC, the two TDD RTS pins need to be driven High.
3. At this stage, the channels selected in step 1 are operang in TDD mode.
4. To set up an ADC trigger on a specic frame and symbol:
• Write symbol and frame trigger registers.
○SetTDDRTSTrigSlot 5 5.
○SetTDDRTSTrigSlot symbol frame.
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• Write 1 in the corresponding bit of the enable register.
○SetTDDRTSEnables 0x0002.
○This controls the hw_trigger_en pins. In this example, it enables the trigger on le 1.
• Write 1 in the trigger register.
○SetTDDRTSTrig 1.
○This controls the hw_trigger pins.
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Chapter 4
Software Design and Build
This chapter describes the soware plaorm running on the applicaon processing unit (APU),
which is logically further subdivided into user and kernel space components (see Figure 11: APU
Linux Soware Plaorm). The Linux applicaon rool in the user space receives the command
over the Ethernet and performs the appropriate acon. This applicaon is the main interface to
the GUI and uses a string-based communicaon protocol described in Chapter 5: Protocol
Specicaons. Device drivers expose a systemac interface to control hardware. These
interfaces are used by the user space applicaon to control hardware.
All conguraons of the RF-ADCs and RF-DACs are done by the Linux applicaon rool running
on the processing system (PS). The applicaon supports all the conguraon opons supported
by the GUI. The GUI sends conguraon details via the Ethernet interface to the Linux
applicaon, which are implemented by their respecve soware APIs.
Software Architecture
The following gure shows the APU Linux soware plaorm, which includes two logical soware
ows: the control path and the datapath. The control path and datapath are implemented using
two dierent TCP sockets. The components in the soware ows are implemented in the user
space and the kernel space.
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Figure 11: APU Linux Software Platform
RFDC GUI
Remote
machine
Rftool (Application)
User space
Device Directory
(/dev)
plmem
sysfs Directory (/sys)
gpio voltage mem_type
select_mem power_input1
Rfclk user
space driver
(Lmx2594/
lmk04828)
driver
RFDC
user
space
driver
MMCM
Control
Kernel space DMA client
driver
DMA
Engine
TCP/IP
stack
AXI DMA
Driver
GEM driver
lic driver UIO
Hardware
GEM I2C CLK104 GPIO Controller Memory RFDC IP
AXI
Infrastructure AXI DMAs MMCM
Libmetal
X23668-031920
User Space Components
The Linux user space components used are:
• The rool is the Linux applicaon that receives commands over the Ethernet from the PC GUI
and performs appropriate acons.
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• RFDC user space drivers provide APIs for communicaon with the RFDC hardware.
• RFCLK user space drivers provide APIs for communicaons with external CLK104 daughter
boards.
Note: See Appendix A: Soware Design Notes — Mulmaster Access of CLK104 on TCA9548
Mulplexer.
• DMA client driver interface /dev/pl_mem is used to allocate a buer from the PL DDR, and
is also used to trigger a DMA transacon from the user space.
Kernel Space Components
The Linux kernel space components used are:
• The GEM driver provides the interface to send and receive packets over the GEM Ethernet
controller.
• The TCP/IP stack provides the interface to create a transmission control protocol (TCP)
socket. It also provides the interface to send and receive data over the TCP socket. The stack
uses the GEM driver to send and receive packets from a network interface card (NIC).
• The DMA client driver provides the interface for a user applicaon to trigger DMA
transacons.
• The AXI DMA driver and DMA engine provide a driver interface to the AXI DMA. The DMA
client driver uses APIs for this DMA engine. The DMA engine uses the AXI DMA driver to
control hardware.
• The libmetal driver is a kernel space driver that allows the execuon of user space drivers.
• Userspace I/O (UIO) is a Linux framework used to export a hardware space to a user space. It
is used by the RFDC user space driver libmetal to congure RFDC hardware.
• MMCM control is reconguring the MMCM/PLL depending on le clock requirement.
The following gure shows the applicaon execuon ow.
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