Xilinx SMPTE 2022-5/6 User manual

SMPTE 2022-5/6 Video
over IP Receiver v4.0
LogiCORE IP Product Guide
Vivado Design Suite
PG033 October 1, 2014

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PG033 October 1, 2014
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Maximum Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: Designing with the Core
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory Requirement and Register Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 5: Test Bench
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A: Verification, Compliance, and Interoperability
Appendix B: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Vivado Lab Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Core Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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Introduction
The Xilinx LogiCORE™ IP SMPTE 2022-5/6
Video over IP Receiver is a module for
broadcast applications that requires bridging
between SMPTE video connectivity standards
bridging between uncompressed SMPTE video
connectivity standards (SD/HD/3G-SDI) and
10Gb/s IP networks. The module is capable of
recovering IP packets lost due to network
transmission errors and ensure the picture
quality of uncompressed, high bandwidth
professional video is maintained. The core is for
developing Internet protocol-based systems to
reduce overall cost in broadcast facilities for
distribution and routing of audio and video
data.
Features
• Handle up to 8 channels of SD/HD/3G-SDI
streams according to SMPTE 2022-6.
Supports SD-SDI, HD-SDI, 3G-SDI Level-A,
3G-SDI Level-B single stream and 3G-SDI
Level-B dual stream.
• Per stream basis Forward Error Correction
(FEC) recovery in accordance to SMPTE
2022-5.
• Supports Level A and Level B FEC
operations.
• Supports block aligned and non-block
aligned FEC operations.
• Supports Virtual Local Area Network
(VLAN) filtering.
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family(1)
Zynq®-7000, Virtex®-7, Kintex®-7
Supported
User Interfaces AXI4-Lite, AXI4-Stream, AXI4
Resources See Ta ble 2-1 , Table 2-2, and Table 2-3
Provided with Core
Design Files Encrypted HDL
Example
Design
SMPTE 2022-5/6 High Bit Rate Media Transport
Over IP Networks with Forward Error Correction
(XAPP1199) [Ref 1]
Tes t B enc h Verilog and VHDL
Constraints
File XDC
Simulation
Model
Encrypted RTL, VHDL Behavioral,
VHDL or Verilog source HDL
Supported
S/W Driver N/A
Tested Design Flows(2)
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design
Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
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IP Facts
Features (continued)
• Configurable channel filtering based on any combinations of the following:
°IP source address
°IP destination address
°User Datagram Protocol (UDP) source port
°UDP destination port
°Real-time Transport Protocol (RTP) Synchronization Source (SSRC) identifier
°VLAN tag value
• Seamless switching (SMPTE2022-7)
• RTP timestamp check bypass
• Statistic indicators
°Received packet
°Reordered packet, Duplicated packet count
°Recovered packet count
°Valid packet count, Unrecoverable packet count
°Out of range packet count
°Packet interval measure
°Buffer overflow flag
°Seamless protect flag
°Link differential measure
• Include or remove FEC engine or secondary link during compile time
• AXI4-Stream data interfaces
• AXI4-Lite control interface
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Chapter 1
Overview
As broadcast and communications markets converge, and the use of IP networks for
transport of video streams becomes more attractive to broadcasters and
telecommunication companies alike, the adoption of 10 Gb/s Ethernet for the transmission
of multiple uncompressed Serial Digital Interface (SDI) streams is becoming a major
customer requirement. The industry is primarily looking at the SMPTE 2022 set of standards
to create an open and interoperable way of connecting video over 10GbE equipment
together and ensuring that Quality of Service (QoS) is high and packet loss is kept to a
minimum or recovered through FEC. As shown in Figure 1-1, high bit rate SMPTE 2022-5/6
is aimed at contribution networks (for example, between broadcast center and regional
studio).
The core includes Forward Error Correction (FEC). FEC protects the video stream during
transport of high-quality video over IP networks. With FEC, the transmitter adds
systematically generated redundant data to its video. This carefully designed redundancy
allows the receiver to detect and correct a limited number of packet errors occurring
anywhere in the video without the need to ask the transmitter for additional video data.
These errors, in the form of lost video packets, can be caused by many reasons, from
thermal noise to storage system defects and transmission noise introduced by the
environment. FEC gives the receiver the ability to correct these errors without needing a
reverse channel to request retransmission of data. In real time systems, the latency is too
great to request a retransmission. The ability of Xilinx FPGAs to bridge the broadcast and
the communications industries by performing highly integrated real-time video interfaces
help broadcasters reduce costs as well as reduce the overall time it takes to acquire, edit
and produce content. Now that video can be reliably delivered over 10 Gb/s Ethernet
(10GbE), broadcasters can replace some of the expensive mobile infrastructures supporting
X-Ref Target - Figu re 1-1
Figure 1-1: High Bit Rate SMPTE 2022-5/6 between Broadcast Center and Local Studio
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Chapter 1: Overview
outside live broadcasts, as well as enable remote production from existing fixed studio set
ups, which dramatically reduces both capital expenditure and operating expenses.
Feature Summary
The core maps Ethernet packets into raw SD/HD/3G-SDI video streams and is capable of
recovering IP packets lost to network transmission errors to ensure the highest picture
quality of uncompressed, high bandwidth professional video.
The core support of VLAN comes from being able to operate seamlessly when receiving
VLAN tagged Ethernet packets. You can configure and instantiate the core from the
Vivado® design tools. Core functionality can be controlled dynamically through an
AXI4-Lite interface.
Applications
• Transport uncompressed high bandwidth professional video streams over IP networks
• Support real-time audio/video applications such as contribution, primary distribution,
and digital cinema
Licensing and Ordering Information
License Checkers
If the IP requires a license key, the key must be verified. The Vivado design tools have
several license check points for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following Vivado flow:
Vivado Synthesis, Vivado Implementation, write_bitstream (Tcl Console command)
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
If a Hardware Evaluation License is being used, the core will stop transmitting video after
timeout.
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Chapter 1: Overview
License Type
This Xilinx LogiCORE™ IP module is provided under the terms of the Xilinx Core License
Agreement. The module is shipped as part of the Vivado Design Suite.
IMPORTANT: For full access to all core functionalities in simulation and in hardware, you must
purchase a license for the core. Contact your local Xilinx sales representative for information about
pricing and availability.
For more information, visit the SMPTE 2022-5/6 Video Over IP product web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.
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Chapter 2
Product Specification
Standards
The core is compliant with the AXI4, AXI4-Stream and AXI4-Lite interconnect standards. See
the Video IP: AXI Feature Adoption section of the AXI Design Reference Guide (UG761) [Ref 2]
for additional information. The function of the core is compliant with SMPTE 2022-5/6
standard.
Maximum Frequencies
The maximum achievable clock frequency can vary. The maximum achievable clock
frequency and all resource counts can be affected by other tool options, additional logic in
the FPGA, using a different version of Xilinx tools and other factors. See the resource
utilization tables for device family specific information.
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Chapter 2: Product Specification
Resource Utilization
Resources required for the this core have been estimated for the devices shown in
Table 2-1, Table 2 -2, and Tab le 2-3 . These values were generated using the Vivado® Design
Suite.
Table 2-1: Resource Utilization for Zynq-7000 Devices (xc7z045, speed -1)
SDI
CHANNEL
FEC
INCLUDE FFs LUTs Slices
LUT FF
Pairs
36k
BLock
RAMs
18k
BLock
RAMs DSP48E1s
1 0 7,698 6,549 2,745 8,456 14 2 0
2 0 10,585 8,676 3,624 11,351 21 3 0
3 0 13,434 10,104 4,836 14,329 28 4 0
4 0 16,305 10,717 5,502 16,571 35 5 0
5 0 19,145 12,132 6,194 19,046 42 6 0
6 0 22,016 13,429 7,564 21,972 49 7 0
7 0 24,876 14,480 8,786 25,012 56 8 0
8 0 27,743 15,253 9,827 28,044 63 9 0
1 1 12,900 9,238 3,959 12,649 50 7 0
2 1 16,398 11,503 5,239 16,011 57 9 0
3 1 20,042 13,654 6,607 19,601 78 12 0
4 1 23,656 14,913 7,770 22,798 85 15 0
5 1 27,284 16,973 8,821 26,194 120 21 0
6 1 30,893 19,140 10,677 30,144 127 21 0
7 1 34,491 20,447 10,434 32,144 134 24 0
8 1 38,105 21,569 12,152 36,419 141 27 0
Table 2-2: Resource Utilization for Virtex-7 FPGAs (xc7vx690t, Speed -1)
SDI
CHANNEL
FEC
INCLUDE FFs LUTs Slices
LUT FF
Pairs
36k
BLock
RAMs
18k
BLock
RAMs DSP48E1s
1 0 7,698 6,546 2,531 8,380 14 2 0
2 0 10,585 8,665 3,643 11,341 21 3 0
3 0 13,434 10,103 4,756 14,258 28 4 0
4 0 16,305 10,702 5,637 16,702 35 5 0
5 0 19,145 12,140 6,501 19,299 42 6 0
6 0 22,016 13,418 7,516 21,975 49 7 0
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