Zenith H-100 User manual

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H/Z-IOO COMPUTER SERVICE DATA MANUALj
ADDITIONAL AND UPDATE MATERIAL
DIRECTIONS:
REPLACE the following pages with the accompanying
updated pages:
Pages 3-21 through 3-28,
Pages 3-67/3-68,
Pages 3-141 through 3-144,
First two pages in Section 5, Disk Controller
and Drives.
ADD Part II to Section 5. This is new data for the
H-207 Floppy Disk Controller Board.
CHANGE the following:
Page 2-99, Parts Required,
Part number of the programming plug ...
from: HE 969-18 to: HE 432-1168.
Page 3-159, Connectors and Sockets,
Part number of the 4-pin right-angle connector ...
from: HE 432-363 to HE 434-363.
UPDATE the Motherboard schematics (refer to the enclosed
schematic
revision sheet) .
10/82
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INITIAL SETUP
INTRODUCTION
The H/Z-100 is easy to disassemble; even an all-in-one unit
requires only about 15 minutes to remove the motherboard.
However, due to the way the unit is packaged, there are
very few test points that you can reach while the unit is
assembled and operating. To get around this, you should
build the following extender cables.
These extender cables allow you to spread out the H/Z-100
over a 29" x46" surface. This permits you to easily reach
every Ie while the unit is operating.
PARTS REQUIRED
2-99
10-82
Qty.
2
1
4
20 ft.
20
1
2
1
Description
40-pin ribbon cable w/connectors
34-pin ribbon cable w/connectors
Small alligator clips for
jumper wire construction
#18 stranded wire
Large spring connector
10-pin adapter plug
10-hole socket shell
Programming plug
Part No.
HE 134-1108
HE 134-1025
HE 260-16
HE 344-155
HE 432-753
HE 432-788
HE 432-1061
HE-432-1168

10-82
TEST, Pin 23 Test Input: This input is examined
by-t"ti'e"wait-for test" software instruction. If pin
23 is low, execution continues, otherwise the processor
waits in an idle state.
MN/MX, Pin 33 Minimum/Maximum: Logic one on this
pi n pl ac es the 8088 in the minimun mode, the mode used
by the H/Z-100. When placed in the maximum mode, some
of the pin functions change. Usually, the maximlDll mode
1s used for larger systems and multi-processing systems.
RESET, Pin 21 Reset: Goes high to reset the 8088.
The interrupts are disabled, certain registers in the
8088 are set or cleared, and the instruction pointer
(program counter) points to the memory address 16 bytes
below the top end of the 1 megabyte range (FFFFOH).
This line is asserted when the RESET line at U236-11
is pull ed low. A Sc hm it t tr igger shape s this signal
and the clock circuits retimes it before applying it
to the 8088.
READY, Pin 22 Ready: This is an acknowledgement
signal from the addressed memory or I/O port that it
is ready to transfer data. When this line is low, the
CPU goes into a wait state until the addressed device
brings it high. This allows using the 8088 with slow
memory or I/O dev ices.
The READY signal is generated when U205-9 places a logic
one on U236-4. U236 synchronizes this signal with the
8088 clock to ensure correct set up and hold times.
eLK, Pin 19 8088 Clock Input. Five-megahertz clock
to provide timing to the 8088.
This signal comes from U236-8 which derives it from
the 15-MHz crystal at Y103. Duty cycle is about 33i
for optimized timing inside the 8088. When the 8088
is the active processor, this line also goes to the
processor swap port as 886 to provide system timing.
3-21

3-22
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PROCESSOR SWAP PORT (MBl)

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PROCESSOR SWAP PORT
OVERVIEW
The processor swap port controls which CPU is to be active,
handles interrupt routing, and ensures proper timing of
the clock circuits during the swap. To access the swap
port, the CPU writes a control byte to port OFEH. Only
three bits of the byte are used: ADO controls the interrupt
mask, ADl controls the swap interrupt line, and AD7 performs
the processor swap.
PROCESSOR SWAP
Refer to schematic MBl as you read the following.
At power up, the reset circuits clear U171-9 to logic zero.
This pin, 8SEL, connects to U186-5, a12H6 PAL. This IC
responds by placing a logic zero on U181-12 and a l~c
one on U181-2. On the first positive transition of 85~,
the 85HOLD line will go low, enabling the 8085 CPU. On
the first positive transition of ~, the 88HOLD line will
go high, disabling the 8088 cpu.
The 8085, while executing the code in the monitor ROM, soon
transfers control to the 8088. It does this by setting
bit 7 of the processor swap port control byte to logic one.
Here's how .•.
The CPU addresses port OFEH to assert SWAPCS (from the 1/0
decoder) at U206-5. It then sets AD7 to logic one at
U111-12. Finally, it asserts the write line at U206-6.
As a result, Ul11-11 goes high and latches U171-9 to logic
one. The 8SEL line is now asserted.
The values at U172-12 and U172-2 are also latched to their
respective outputs, but these will be covered later.
3-23

3-24
The 8SEL line. now logic one. causes U186-13 to change to
logic one. U186-18 to change to logic zero. and U186-16
to change to logic one.
The HOLD. line at U185-11 asserts whenever a board on the
S-100 bus takes control of the H/Z-100. This causes U186
to disable both the 8085 and the 8088 through U187. Both
CPUs respond by returning their hold-acknowledge signals;
the 8088 at U186-3 and the 8085 at U171-2. When this
happens. U186 asserts the HAK line at pin 17. This, in
turn, raises the S-100 pHLOA line to logic one at U180-9.
The board that generated the HOLD· request can now take
control of the H/Z-100.
SWAP TIMING
The 88SEL line also goes to U188-4, a quad D-type latch.
This circuit is designed to suppress any glitches on the
system clock line when the H/Z-100 switches from one CPU
to the other. It also ensures that the CPU being disabled
is no longer active when the other CPU is enabled.
The 8085 and the 8088 run on separate crystal-controlled
clocks; the 8085 from Y101 and the 8088 from Y103. Although
these clocks are stable. they aren't in phase. Switching
from one clock to another can cause a glitch on the system
clock line, S~. which can upset the timing in other
circuits.

3-25
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SWITCHING FROM 8085 to 8088

3-26
To see how U188 and its associated circuits block this
spike, refer to the waveforms on the previous page.
The two top waveforms are the respective clocks for the
8085 and 8088 CPUs. These are present at the inputs of
inverters U200-2 and U200-14. Assuming that the 8085 is
the active processor, then U200-1 is low and 85' couples
through the inverter to form Sl. It also couples through
U225B to clock U188.
At
time T1, the 8088 is selected; the 88SEL line goes to
logic one as shown at A on the waveforms illustration.
The next clock pulse at U188-9 latches this logic one into
U188-2, the Q1 output at B.
The next clock pulse causes the Q2 output to latch high,
shown at C. This tri-states U200 through the exclusive-DR
gate at U203B. At the same time, Q2 goes low to couple
the 88~ clock to the ~ line. Since, in this example, the
two clocks are nearly l80-degrees out of phase, the clock
immediately returns to zero, causing the spike at D in the
waveforms illustration.
Up until this time, the output of U203-8, another exclusive-
OR gate, has been logic one. This is because its inputs
Q2 and Q3 of U188 have been in opposite states. However,
since Q2 went low at time T3, both inputs to U203C are the
same, causing U203-8 to go to logic zero (waveform E).
This forces the system clock output at U225-3 to logic one
until time T4 (waveform F).