Zenith H-100 User manual

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H/Z-IOO COMPUTER SERVICE DATA MANUALj
ADDITIONAL AND UPDATE MATERIAL
DIRECTIONS:
REPLACE the following pages with the accompanying
updated pages:
Pages 3-21 through 3-28,
Pages 3-67/3-68,
Pages 3-141 through 3-144,
First two pages in Section 5, Disk Controller
and Drives.
ADD Part II to Section 5. This is new data for the
H-207 Floppy Disk Controller Board.
CHANGE the following:
Page 2-99, Parts Required,
Part number of the programming plug ...
from: HE 969-18 to: HE 432-1168.
Page 3-159, Connectors and Sockets,
Part number of the 4-pin right-angle connector ...
from: HE 432-363 to HE 434-363.
UPDATE the Motherboard schematics (refer to the enclosed
schematic
revision sheet) .
10/82
,.
::::}U:U~
..................
/

INITIAL SETUP
INTRODUCTION
The H/Z-100 is easy to disassemble; even an all-in-one unit
requires only about 15 minutes to remove the motherboard.
However, due to the way the unit is packaged, there are
very few test points that you can reach while the unit is
assembled and operating. To get around this, you should
build the following extender cables.
These extender cables allow you to spread out the H/Z-100
over a 29" x46" surface. This permits you to easily reach
every Ie while the unit is operating.
PARTS REQUIRED
2-99
10-82
Qty.
2
1
4
20 ft.
20
1
2
1
Description
40-pin ribbon cable w/connectors
34-pin ribbon cable w/connectors
Small alligator clips for
jumper wire construction
#18 stranded wire
Large spring connector
10-pin adapter plug
10-hole socket shell
Programming plug
Part No.
HE 134-1108
HE 134-1025
HE 260-16
HE 344-155
HE 432-753
HE 432-788
HE 432-1061
HE-432-1168

10-82
TEST, Pin 23 Test Input: This input is examined
by-t"ti'e"wait-for test" software instruction. If pin
23 is low, execution continues, otherwise the processor
waits in an idle state.
MN/MX, Pin 33 Minimum/Maximum: Logic one on this
pi n pl ac es the 8088 in the minimun mode, the mode used
by the H/Z-100. When placed in the maximum mode, some
of the pin functions change. Usually, the maximlDll mode
1s used for larger systems and multi-processing systems.
RESET, Pin 21 Reset: Goes high to reset the 8088.
The interrupts are disabled, certain registers in the
8088 are set or cleared, and the instruction pointer
(program counter) points to the memory address 16 bytes
below the top end of the 1 megabyte range (FFFFOH).
This line is asserted when the RESET line at U236-11
is pull ed low. A Sc hm it t tr igger shape s this signal
and the clock circuits retimes it before applying it
to the 8088.
READY, Pin 22 Ready: This is an acknowledgement
signal from the addressed memory or I/O port that it
is ready to transfer data. When this line is low, the
CPU goes into a wait state until the addressed device
brings it high. This allows using the 8088 with slow
memory or I/O dev ices.
The READY signal is generated when U205-9 places a logic
one on U236-4. U236 synchronizes this signal with the
8088 clock to ensure correct set up and hold times.
eLK, Pin 19 8088 Clock Input. Five-megahertz clock
to provide timing to the 8088.
This signal comes from U236-8 which derives it from
the 15-MHz crystal at Y103. Duty cycle is about 33i
for optimized timing inside the 8088. When the 8088
is the active processor, this line also goes to the
processor swap port as 886 to provide system timing.
3-21

3-22
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ISWAP PORTI
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...... -----------= .... '<.ItI-L-D._('7'(I MOL'·
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•• \. ........ +-F~
r--------------------------:~ ....... ~----~II.I> .. IlEF·
IW"
PROCESSOR SWAP PORT (MBl)

10-82
PROCESSOR SWAP PORT
OVERVIEW
The processor swap port controls which CPU is to be active,
handles interrupt routing, and ensures proper timing of
the clock circuits during the swap. To access the swap
port, the CPU writes a control byte to port OFEH. Only
three bits of the byte are used: ADO controls the interrupt
mask, ADl controls the swap interrupt line, and AD7 performs
the processor swap.
PROCESSOR SWAP
Refer to schematic MBl as you read the following.
At power up, the reset circuits clear U171-9 to logic zero.
This pin, 8SEL, connects to U186-5, a12H6 PAL. This IC
responds by placing a logic zero on U181-12 and a l~c
one on U181-2. On the first positive transition of 85~,
the 85HOLD line will go low, enabling the 8085 CPU. On
the first positive transition of ~, the 88HOLD line will
go high, disabling the 8088 cpu.
The 8085, while executing the code in the monitor ROM, soon
transfers control to the 8088. It does this by setting
bit 7 of the processor swap port control byte to logic one.
Here's how .•.
The CPU addresses port OFEH to assert SWAPCS (from the 1/0
decoder) at U206-5. It then sets AD7 to logic one at
U111-12. Finally, it asserts the write line at U206-6.
As a result, Ul11-11 goes high and latches U171-9 to logic
one. The 8SEL line is now asserted.
The values at U172-12 and U172-2 are also latched to their
respective outputs, but these will be covered later.
3-23

3-24
The 8SEL line. now logic one. causes U186-13 to change to
logic one. U186-18 to change to logic zero. and U186-16
to change to logic one.
The HOLD. line at U185-11 asserts whenever a board on the
S-100 bus takes control of the H/Z-100. This causes U186
to disable both the 8085 and the 8088 through U187. Both
CPUs respond by returning their hold-acknowledge signals;
the 8088 at U186-3 and the 8085 at U171-2. When this
happens. U186 asserts the HAK line at pin 17. This, in
turn, raises the S-100 pHLOA line to logic one at U180-9.
The board that generated the HOLD· request can now take
control of the H/Z-100.
SWAP TIMING
The 88SEL line also goes to U188-4, a quad D-type latch.
This circuit is designed to suppress any glitches on the
system clock line when the H/Z-100 switches from one CPU
to the other. It also ensures that the CPU being disabled
is no longer active when the other CPU is enabled.
The 8085 and the 8088 run on separate crystal-controlled
clocks; the 8085 from Y101 and the 8088 from Y103. Although
these clocks are stable. they aren't in phase. Switching
from one clock to another can cause a glitch on the system
clock line, S~. which can upset the timing in other
circuits.

3-25
10-82
SWITCHING FROM 8085 to 8088

3-26
To see how U188 and its associated circuits block this
spike, refer to the waveforms on the previous page.
The two top waveforms are the respective clocks for the
8085 and 8088 CPUs. These are present at the inputs of
inverters U200-2 and U200-14. Assuming that the 8085 is
the active processor, then U200-1 is low and 85' couples
through the inverter to form Sl. It also couples through
U225B to clock U188.
At
time T1, the 8088 is selected; the 88SEL line goes to
logic one as shown at A on the waveforms illustration.
The next clock pulse at U188-9 latches this logic one into
U188-2, the Q1 output at B.
The next clock pulse causes the Q2 output to latch high,
shown at C. This tri-states U200 through the exclusive-DR
gate at U203B. At the same time, Q2 goes low to couple
the 88~ clock to the ~ line. Since, in this example, the
two clocks are nearly l80-degrees out of phase, the clock
immediately returns to zero, causing the spike at D in the
waveforms illustration.
Up until this time, the output of U203-8, another exclusive-
OR gate, has been logic one. This is because its inputs
Q2 and Q3 of U188 have been in opposite states. However,
since Q2 went low at time T3, both inputs to U203C are the
same, causing U203-8 to go to logic zero (waveform E).
This forces the system clock output at U225-3 to logic one
until time T4 (waveform F).

10-82
At time T4, the first positive-going edge of the 8088 clock
causes the 01 output of U188 to go high. This opens the
gate at U225A to pass the system clock, which is now the
8088 signal.
As mentioned earlier, the other function that 88SEL and
U188
perform is to ensure that the CPU being disabled is
completely disabled before the other CPU is activated.
To see how this is done, again refer to the waveforms
illustration.
Once again, assume that the H/Z-100 is switching from the
8085 to the 8088. At time T 1, the 88SEL line goes high,
which is coupled to U203-11. The other input of this
exclusive-OR gate is the Q2 line from U188. Since both
inputs are now the same state, U203-11 goes to logic zero
to preset both HOLD latches at U187.
Both CPUs respond by going into a HOLD stat~ and sending
hold-acknowledge signals to U186; the 8088 to pin 3 and
the 8085 to pin 4 through U171. This asserts HAK at pin
17 which drives the S-100 pHLDA line at U180-9.
At time T3, the Q2 line goes low and U203-11 returns to
logic one, thus releasing the latches at U187 from their
preset states. The next 88l clock pulse latches the logic
zero at U187-2 into U187-5, removing the 8088 from the hold
state.
Al so at thi s time, U 188-7 goes high to drive U215-3 high.
This last IC connects to pin 21 of the S-100 bus to form
the NDEF (8088) line. This line is a "not-to-be-defined"
line that can be used for any function by the computer
manufacturer. For the H/Z-100, this line asserts when the
8088 is active.
3-27

3-28
INTERRUPT MASK
The interrupt mask circuits ensure that interrupt requests
are sent to the currently active CPU. The mask bit. MSK.
is set or cleared by setting or clearing bit 0 of the
processor swap port. If set. and the 8085 is active, the
8085 gets all interrupt requests. If cleared. and the 8085
is ac t i ve. the in terrupt request is blocked. However. the
swap port will disable the 8085 and enable the 8088. If
the 8088 is active. all interrupt requests are sent to the
8088 regardless of the mask bit. Here's hoW it's done .••
Immediately after reset. the 8085 CPU is the active
processor. Control lines 5SEL at U171-8 and MSK at U112-6
are logic one. These two lines connect to U225-9 and
U225-1
O. shown near the 8085 IC on the schematic. U220-2
inverts the resulting logic zero to enable U189A and U189D.
So all interrupts are sent to the 8085; maskable through
U189A. non-maskable through U189D.
The 8SEL line. which is the complement of 5SEL. disables
U1898 and U189C. the AND gates to the 8088. Later. when
the 8085 hands control to the 8088 CPU. 8SEL will go high
and 5SEL will go low.
If. while the 8085 is selected. the MSK line is set to logic
zero. U220-2 disables U189A and U189D. This blocks the
interrupt request from both the 8085 and the 8088. However.
if an interrupt request should occur. either standard or
NMI, U156-6 will go high to assert the NMINT line.
The NMINT line connects to U155-9 in the processor swap
port. The other input is the MSK line which is also high.
As a result, U155-8 goes low to assert the 8SEL line. The
H/Z-100 swaps
to the 8088 processor as described previously.
When the 8088 CPU is active. 8SEL is high to enable U1898
and U189C. U189A and U189D are disabled because 5SEL is
logic zero at U225-9. So, no matter what the setting of
the R:rK bit at U?25-10. all interrupt requests will be
routed to the BOB8 processor.

MAP SELECTING
Map selecting takes place at pins 1and 15 of U111. These
two lines, MAPSELO and MAPSEL1, also go to U173-7 and -8;
but currently are not used by this IC. Depending on the
logic state of U111-1 and U111-15, plus the address on lines
BA12-BA15, the memory map will appear to be in one of the
four configurations shown in the illustration:
Confisuration 11: HAPSEL 1=0 HAPSELO -= 0
This is the default confisuration, memory is contiguous
from 0 to 192K.
Confisuration 12: HAPSELl =0 HAPSELO =1
In this configuration, the first 48K of bank zero
appears to be swapped with the first 48K of bank 1-
The two 16K areas and the rest of RAH are unchanged.
This configuration may be used for HP/H while runfling
the 8085 CPU.
Configuration 13: HAPSELl =1 HAPSELO =0
In this configuration, the first 48K of bank zero
appears to be swapped with the first 48K of bank 2.
The two 16K areas and the middle 64K of RAH are
unchanged. This configuration alay also be used for
HP/H while running the 8085 CPU.
Confisuration 14: HAPSELl =1 HAPSELO =1
In this configuration, 56K in bank 0 appears to be
swapped with 5t>K in bank 1. four kilobyte buffers
above and below each 56K area remain unchanged, as
does the top 64K bank. This configuration would permit
using an extended BIOS when running CP/H-85.
3-67
Note that, in all cases, the memory only
swapped from the memory's point of view.
addresses the swapped memory, the memory map
asserts a different RAS line than it normally
appears to be
When the CPU
decoder merely
would.
10-82
For example, assume that the H/Z-100 is operating in
Configuration 114. If the CPU should write to the byte at
the 6K location, U111 would assert REN1 instead of RENO. The
memory
at the 70K location will be written to. Bear in
mind, however, that as far as the CPU (and the programmer)
is concerned, the byte at 6K was wri tten to.
Address lines BA12-BA15 allow the memory map decoder to
keep some sections of memory in place--down to 4K
increments.

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PROCESSOR SWAP TESTS
SWAP TEST #1
1. Lift pin 5 of U186 (MS1).
2. Jumper U186-5 to ground.
3. Apply power and perform the following steps:
3-141
CHECK
·S100-21
=L
·U180-9 =L
·U186-3 =H
·U186-4 =L
(MS1)
(MS1)
(MS1)
(MS1)
IF NOT OKAY, CHECK
U215-3
UlaO-l0
U2l1-30
U17l-5
10-82
Go to Swap Test #2
U17l-l
:: L
(MS1)
U2l0-38
U171-5 =L
(MS1)
U171-1
U180-10
::
L
(MS1)
U186-17
U186-3 =H
(MS1)
U2ll-30
U186-4
::
L
(MS 1) U171-5
U186-l6 =L
(MS 1) U186-3
U186-17 =L
(MS1)
U186-4
U186-l8 =H
(MS1)
U186 is defective.
U187-2
::
H
(MS1)
U186-l8
U187-3 =p
(MS1)
Restore U186-5 and go to CLOCK
CIRCUITS TESTS.
U187-5 =H
(MB 1) U187-2. U187-3
U187-9 =L
(MS 1) U187-10,
U187-ll,
U187-12
U187-l0
::
H
(MS1)
U203-l1
U187-ll
::
P (MS1)
Restore U186-5 and go
to CLOCK
CIRCUITS TESTS.
U187-l2 =L
(MS1)
U186-3
U203-1l
::
H
(MS1)
U203-l2, U203-l3
U203-12
::
L
(MS1)
U186-l6
U203-13
:: H
(MS 1)
Restore U186-5 and go
to CLOCK
CIRCUITS TESTS.

3-142
U210-38 =L
(MB1)
U210-39
U210-39 =L
(MS 1) U187-9
U211-30 =H
(MS1)
U211-31
U211-31 =H
(MS1)
U187-5
U215-2 =L
(MS 1)
Restore U186-5 and
go to CLOCK
CIRCUITS TESTS.
U215-3 =L
(MS 1)
U215-2
-----------------------------------------------------------------------
-----------------------------------------------------------------------
SWAP TEST #2
1. Lift pins 4and 5 of U186.
2. Jumper U186-4 and U186-5 to 5 volts.
3. Apply power and perform the following tests:
CHECK
.S 100-21 =H
·U 171-5 =H
·U180-9 =L
(MS1)
(MS1)
(MS1)
IF NOT OKAY, CHECK
U215-3
U171-3, U171-2, U171-1
U180-10
Go to Swap Test #3.
U171-1 =H
U171-2 =H
U171-3 =p
(MS1)
(MSl )
(MS1)
U210-38
U210-38
Restore U186-4 and U186-5
and go
to CLOCK CIRCUITS
TESTS.
U180-10 =L
(MS1)
U186-3 =L
(MS 1)
U186-13 =H
(MS 1)
U186-16 =H
(MS1)
U186-17 =L
(MS 1)
U186-18 =L
(MS1)
U186-17
U211-30
U186-3
U186-3
U186-3
U186 is defective.

U187-2 =L
(MB1) U186-18
U187-3 =p
(MB1) Restore
U186-4 and U186-5
and go
to CLOCK CIRCUITS
TESTS.
U187-4 =H
(MB1) U203-11
U187-5 =L
(MB1 )U187-2_ U187-3_ U187-4
U187-9 =H
(MB1)
U187-11_ U187-12
U187-11 =P
(MB1)
Restore U186-4 and U186-5
and go
to CLOCK CIRCUITS
TESTS.
U187-12 =H
(MB1 )U186-13
U203-11 =H
(MB1)
U203-13_ U203-12
U203-12 =H
(MB1)
U186-16
U203-13 =L
(MB1)
Restore U186-4 and U186-5
and go
to CLOCK CIRCUITS
TESTS.
U210-38 =H
(MB1)
U210-39
U210-39 =H
(MB1)
U181-9
U211-30 =L
(MB1)
U211-31
U211-31 =L
(MB1)
U187-5
U215-2 =H
(MB1 )
Restore
U186-4 and U186-5
and go
to CLOCK CIRCUITS
TESTS.
U215-3 =L
(MB1)
U215-2
======================================================================
SWAP TEST #3
3-143
1. Restore pin 4 of U186; leave pin 5 lifted.
2. Jumper U186-5 to ground.
3. Turn on the H/Z-100.
4. Connect ajumper wire from ground to pin 74 of the
S-100 bus (HOLD·).
5. Perform the following tests:
..
CHECK
·U180-9 =H
(MB 1)
IF NOT OKAY_ CHECK
U180-10
10-82
Go to Swap Test #4.

3-144
U180-10 =H
U186-13 =H
U186-16 =H
U
186-17 =H
(MB1)
(MB1)
(MBl )
(MB1)
U186-17
U186 is defective.
t
U186 is defective.t
U186-13. U186-18
tNOTE:
Before replacing U186. check the continuity between
pins 6and 15. and between pins 7and 14. Also
check for ground at pins 2. 8. 9. 10. 11. 12. and 19.
===============;======================================================
SWAP TEST #4
1. Remove the jumper between ground and pin 5.
2. Connect the jumper from pin 5 to +5 volts.
CHECK
.U180-9 =H
End of tests.
U180-10 =H
U186-13 =H
U
186-17 =H
U186-18 =H
(MB1)
(MB1)
(MB1)
(MB1)
(MB1)
IF NOT OKAY. CHECK
U180-10
U180-17
U186 is defective.
t
U186-13. U186-18
U186 is defective.
t
tNOTE. Before replacing U186. check the continuity between
pins 6and 15, and between pins 7and 14. Also
check for ground at pins 2. 8, 9, 10. 11, 12, and 19.

PARTS LIST
C! ?CJ 1 ~, ..
~~
:':5:': :Tl~'i
HEATH
Part ';0.
c: ;lCe IT
Com? ~Io.
DESCRIP710:/
HEAT"
Part :/0.
CIRCUIT
Compo ~O.
OESCRl?i!C~
HEl,iH
Part No.
INTEGRATED CIRCUITS (CONTINUED)
I
INTEGRATED CIRCUITS (CONTINUED)
I
CRYSTALS
YI01
10.000 MHz crystal HE 404-645
U 170 74ALS1020
HE 443-1081 U210
8085A
HE 443-1010
YI02 6.000 MHz crystal
HE 404-647
U171
74ALS74
HE 443-1051
U211
8088
HE 443-1009
Y103
15.000 MHz crystal
HE 404-644
U172
7"ALS74 HE 443-1051 U212
74LS273
HE 443-805
UI73
HAL14L4
HE 444-130
U213
74LS373
HE 443-837
U174
74LS32
HE 443-875
U214
74LS244
HE 443-791
CONNECTORS - SOCKETS
U175
74L510
HE 443-797
U215
74L5125
HE 443-811
U176
74L5174
HE 443-879
U216
74ALS28
HE 443-1048
8-pin IC socket
HE 434-230
U 177
74LS240
HE 443-754
U217 74LS244
HE 443-791 14-pin
IC socket HE 434-298
U178
74LS244
HE 443-791
U218
96LS02
HE 443-1040 16-pin
IC socket
HE 434-299
U179 825129 PROM
HE 444-101
U219
74ALS74
HE 443-1051 18-pin
IC socket
HE 434-310
20-pin IC socket
HE 434-311
U180
74LS367
HE 443-857
U220 74LS04
HE 443-755
24-pin IC socket
HE 434-307
U181 74LS244
HE 443-791
U221
74L532
HE 443-875 28-pin
IC socket
HE 434-310
Ul82 74L514
HE 443-872 U222
74L500
HE 443-728 40-pin
IC socket HE 434-253
u183
7"LS02
HE 443-779 U223
74L5244
HE 443-791
2-pin connector
HE 432-1171
U184
74LS156
HE 443-1036
U224
74ALS28
HE 443-1048
3-pin connector
HE 432-1102
u185
74L514
HE 443-872
U225
74AL537
HE 443-1049
4-pin right-angle connector HE-434-363
U186
HA1.12H6
HE 444-128
U226
74S288' PROM
HE 444-105
9-pin right-angle molex
HE 432-1202
U187
74ALS74
HE 443-1051
U227
74LS373
HE 443-837
U188
74LS175
HE 443-752
U228
781.12 .12V regulator
HE 442-644 connector
10-pin connector HE 432-903
U189 741.S08
HE 443-780
U229
791.12 -12V regulator
HE 442-646
20-pin connector
HE 432-1227
2764 ROI1
HE 444-87
U230
75189
HE 443-795
25-pin Fright-angle "0"
HE 432-1195
U190
connector
U191
4.000 HHz oscillator
HE 150-132
U231
75452
HE 443-74
25-pin H right-angle "0"
HE 432-1194
U192
74L5169
HE 443-1054 U232
555 timer
HE 442-53 connector
U193
'!4U367
HE 443-857
U233 74ALS74
HE 443-1051
40-pin connector
HE 432-1062
U194
7417
HE 443-72
U234
74ALS74
HE 443-1051 Jumper
HE 432-1041
U195 74L5240
HE 443-754
U235 74ALS10
HE 443-1047
S-10D board edge connector
HE 432-1193
U196
74L5373
HE 443-837
U236 8284A
HE 443-1011
U197
741.Sfl3
HE 443-837
U237 74LS125
HE 443-811
U198
74LS373
HE 443-837
U238 74ALS74
HE 443-1051 HARDWARE
U199
741.S156
HE 443-1036
U239 74LS244
HE 443-791
14 lockwasher
HE 254-9
U200
74LS368
HE 443-1024
U240
4.9152 MHz oscillator
HE 150-133
14 nut
HE 252-15
U201
74L5125
HE 443-811 U24'
74L5244
HE 443-791 4-40 x
5/16" hex "0" spacer HE 255-757
U202
74A1.S74
HE 443-1051
U242
2661-2
HE 443-1061 4-40 x
5/16" black HE 250-1469
U203 74LS86
HE 443-891
U243
2661-2
HE 443-1061
phillips-head screw
U204
8741A
HE 444-141
U244
74LS244
HE 443-791
U205 74S74
HE 443-900 U245
75188
HE 443-794
U206
74ALS02
HE 443-1045
U246
75189
HE 443-795 I
HISCELLANEOUS
U207
74LS14
HE 443-872
U247
75189
HE 443-795
HE 85-2653-1
U208
8259A
HE 443-1012
U248 75188
HE 443-794
PC board
U209
825~A HE 443-1012 Wire. bare
HE 340-8
Wire, blue wirewrap
HE 344-189
0101
IN5817 diode
HE 57-507
0102 IN4149 diode
HE 56-56
0103 1N4149 diode
HE 56-56
0104
1N4149 diode
HE 56-56
SW101 8-section slide switch
HE 60-621
Xl01
Audio transducer
HE 473-29
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