Ziatech Corporation ZT 8906 User manual

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ZT 8905/8906
ZT 8905/8906
H A R D W A R E M A N U A L
For ZT 8905 Revision A.3
Single Board Computer
with Pentium Processor
®
For ZT 8906 Revision A.3
ZT M8905
September 9, 1997
102575
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ZT 8905/8906
ZT 8905/8906
H A R D W A R E M A N U A L
For ZT 8905 Revision A.3
Single Board Computer
with Pentium Processor
®
For ZT 8906 Revision A.3
ZT M8905
September 9, 1997
102575
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

ALI is a registered trademark and Aladdin is a trademark of Acer Laboratories, Inc.
CompactPCI is a trademark of the PCI Industrial Computers Manufacturers Group.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Intel and Pentium are registered trademarks of Intel Corporation.
OS/2 and PC/AT are registered trademarks of International Business Machines, Inc.
QNX is a registered trademark of Quantum Software Systems Ltd.
STD 32 is a registered trademark of Ziatech Corporation.
STD 32 STAR SYSTEM is a trademark of Ziatech Corporation.
UNIX is a registered trademark of AT&T Bell Laboratories.
VRTX32 is a registered trademark of Ready Systems, Inc.
Windows is a trademark and MS-DOS is a registered trademark of Microsoft Corporation.
All other brand or product names may be trademarks or registered trademarks of their respective
holders.
©Copyright 1997 Ziatech Corporation
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WHAT'S IN THIS MANUAL?
This manual describes the operation and use of the ZT 8905/8906 Single Board Computer with
Pentium Processor. The term ZT 8905 is used throughout this manual to reference both the ZT 8905
and the ZT 8906, except where otherwise noted. Specific differences between the two are explicitly
stated. The following summarizes the focus of each major section in this manual.
Chapter 1, "Introduction," introduces the key features of the ZT 8905. It includes a product
definition, a list of product features, a functional block diagram, and a brief description of each block.
This chapter is most useful to those who wish to compare the features of the ZT 8905 against the
needs of a specific application.
Chapter 2, "Getting Started," summarizes the information needed to install and configure your
ZT 8905.
Chapter 3, "STD 32 Bus Interface," presents a detailed description of the ZT 8905 interface to the
STD 32 bus architecture. The topics discussed include compatibility, interrupt structure, and multiple
master operation.
Chapter 4, "Interrupt Controller," describes the two Intel-compatible 8259 cascaded interrupt
controllers. This chapter summarizes and illustrates the interrupt sources and the interrupt
controllers' programmable registers.
Chapter 5, "Counter/Timers," discusses the three programmable counter/timers. It includes a
diagram of the counter/timer architecture, a summary of operating modes, and descriptions of the
programmable registers.
Chapter 6, "DMA Controller," provides an overview of ZT 8905 DMA architecture and DMA
controller operation. Descriptions of DMA controller programmable registers are also included.
Chapter 7, "Real-Time Clock," lists the major features of the real-time clock and provides register
descriptions.
Chapter 8, "Serial Controller," discusses operation of the two serial ports and provides register
descriptions.
Chapter 9, "IEEE 1284 Parallel Port Interface," contains descriptions of the programmable
registers for the IEEE-1284 compatible printer interface.
Chapter 10, "Optional IDE Interface," covers the mounting and enabling of an optional local
Intelligent Drive Electronics (IDE) interface. It also discusses the types of configurations in which the
addition of a local hard disk can be an advantage.
Chapter 11, "System Registers," provides register descriptions and a brief overview of the System
registers used to control and monitor a variety of functions on the ZT 8905.
Chapter 12, "Watchdog Timer," explains operation of the watchdog timer and includes code for
arming and strobing the timer.
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Chapter 13, "PCI Mezzanine Local Bus," introduces the features of the Peripheral Component
Interconnect (PCI) local bus interface that provides a high speed path between the CPU and
peripherals.
Chapter 14, "Programmable LED," provides code for turning the LED on and off.
Appendix A, "Board Configuration," describes the software configuration registers, jumpers, and
cuttable traces on the ZT 8905. This appendix details factory default settings as well as information to
tailor your board to a specific application.
Appendix B, "Specifications," contains the electrical, environmental, and mechanical specifications
for the ZT 8905. It also provides illustrations of cables and connector pinouts, and tables showing
connector pin assignments.
Appendix C, "Customer Support," offers a product revision history, technical assistance and
warranty information, and the necessary information should you need to return your ZT 8905 for
repair.
Appendix D, "PCI Configuration Space Map," presents the generic layout of the PCI Configuration
Header for all PCI compliant devices. It also contains a table showing the PCI bus mapping of the
ZT 8905's on-board devices.
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CONTENTS
CHAPTER 1. INTRODUCTION ............................................................................................................. 1
PRODUCT DEFINITION........................................................................................................... 1
Stand Alone.................................................................................................................. 1
STD 32 Single Master.................................................................................................. 2
STD 32 Multiple Master (STAR SYSTEM)................................................................... 2
FEATURES OF THE ZT 8905................................................................................................... 2
DEVELOPMENT CONSIDERATIONS...................................................................................... 3
FUNCTIONAL BLOCKS............................................................................................................ 4
STD 32 Bus Interface................................................................................................... 5
Pentium Processors..................................................................................................... 5
Memory and I/O Addressing......................................................................................... 6
PCI Local Bus............................................................................................................... 6
Serial I/O....................................................................................................................... 6
Interrupts......................................................................................................................7
Counter/Timers............................................................................................................. 7
DMA.............................................................................................................................. 7
Watchdog Timer........................................................................................................... 7
Real-Time Clock........................................................................................................... 8
Keyboard Controller...................................................................................................... 8
IEEE® 1284 Parallel Port/Printer Interface .................................................................. 8
Speaker Interface......................................................................................................... 9
Optional IDE Interface.................................................................................................. 9
CHAPTER 2. GETTING STARTED..................................................................................................... 11
UNPACKING........................................................................................................................... 11
WHAT'S IN THE BOX?........................................................................................................... 11
SYSTEM REQUIREMENTS.................................................................................................... 11
MEMORY CONFIGURATION................................................................................................. 12
I/O CONFIGURATION ............................................................................................................ 13
CONNECTOR CONFIGURATION.......................................................................................... 15
JUMPER DESCRIPTIONS...................................................................................................... 16
ZT 8905 SETUP...................................................................................................................... 16
System Configuration Overview................................................................................. 17
Operating System Installation..................................................................................... 19
CHAPTER 3. STD 32 BUS INTERFACE............................................................................................. 21
STD 32 BACKGROUND ......................................................................................................... 21
STD-80 PERIPHERAL SUPPORT.......................................................................................... 21
Address Multiplexing .................................................................................................. 21
Interrupts.................................................................................................................... 22
I/O Expansion............................................................................................................. 22
DMA Slave Support.................................................................................................... 22
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Contents
STD 32 BUS COMPATIBILITY................................................................................................22
Standard Architecture.................................................................................................22
Extended Architecture.................................................................................................23
Multiprocessing...........................................................................................................23
STD 32 Compliance Levels ........................................................................................23
STD BUS INTERRUPTS .........................................................................................................24
Maskable Interrupts ....................................................................................................24
Non-Maskable Interrupts ............................................................................................26
RESET.....................................................................................................................................26
MULTIPLE MASTER AND INTELLIGENT I/O.........................................................................26
Multiple Master............................................................................................................27
Intelligent I/O...............................................................................................................27
Multiple Master Vs. Intelligent I/O...............................................................................28
Multiple Master System Requirements.......................................................................28
Multiple Master Reset.................................................................................................30
CHAPTER 4. INTERRUPT CONTROLLER.........................................................................................31
INTERRUPT SOURCES..........................................................................................................33
PROGRAMMABLE REGISTERS ............................................................................................33
Initialization Registers (ICW1-ICW4)..........................................................................34
Initialization Register ICW1..................................................................................35
Initialization Register ICW2..................................................................................35
Initialization Register ICW3..................................................................................35
Initialization Register ICW4..................................................................................36
Operational Registers (OCW1-OCW3) ......................................................................36
Operational Register OCW1 ................................................................................36
Operational Register OCW2 ................................................................................37
Operational Register OCW3 ................................................................................38
Status Registers (IRR, ISR, IPR)................................................................................38
Status Register IRR..............................................................................................38
Status Register ISR..............................................................................................39
Status Register IPR..............................................................................................39
Extended Mode Register ............................................................................................40
ADDITIONAL INFORMATION.................................................................................................40
CHAPTER 5. COUNTER/TIMERS.......................................................................................................41
PROGRAMMABLE REGISTERS ............................................................................................42
Count Registers and Count Latch...............................................................................42
Status Register ...........................................................................................................43
Control Register..........................................................................................................44
General Control Register......................................................................................44
Count Latch Control Register...............................................................................44
Multiple Latch Control Register ............................................................................45
ADDITIONAL INFORMATION.................................................................................................45
CHAPTER 6. DMA CONTROLLER .....................................................................................................47
ZT 8905 SPECIFICS................................................................................................................47
PROGRAMMABLE REGISTERS ............................................................................................48
Address Register ........................................................................................................50
Count Register............................................................................................................50
Status Register ...........................................................................................................51
Command Register.....................................................................................................51
Write Request Register...............................................................................................52
Write Single Mask Register ........................................................................................52
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Contents
Write Mode Register .................................................................................................. 53
DMA Extended Mode Register................................................................................... 53
Clear Byte Register .................................................................................................... 54
Clear Master Register ................................................................................................ 54
Clear Mask Register................................................................................................... 54
Write Mask Register................................................................................................... 54
DMA Page Register.................................................................................................... 55
DMA Extended Page Register ................................................................................... 55
ADDITIONAL INFORMATION................................................................................................. 55
CHAPTER 7. REAL-TIME CLOCK......................................................................................................57
PROGRAMMABLE REGISTERS............................................................................................ 57
Register A................................................................................................................... 58
Register B................................................................................................................... 58
Register C .................................................................................................................. 59
Register D .................................................................................................................. 59
ADDITIONAL INFORMATION................................................................................................. 59
CHAPTER 8. SERIAL CONTROLLER................................................................................................ 61
ZT 8905 SPECIFICS...............................................................................................................61
Address Mapping ....................................................................................................... 61
Interrupt Selection ...................................................................................................... 62
Handshake Signals .................................................................................................... 62
Serial Channel Interface............................................................................................. 62
PROGRAMMABLE REGISTERS............................................................................................ 62
Baud Rate Divisors..................................................................................................... 63
Divisor Latch LSB and MSB....................................................................................... 64
Interrupt Control Register........................................................................................... 64
Interrupt Status Register ............................................................................................ 65
Line Control Register.................................................................................................. 65
Line Status Register................................................................................................... 66
Modem Control Register ............................................................................................ 66
Modem Status Register.............................................................................................. 67
ADDITIONAL INFORMATION................................................................................................. 67
CHAPTER 9. IEEE-1284 PARALLEL PORT INTERFACE................................................................. 69
PARALLEL PORT CONFIGURATION OPTIONS................................................................... 69
ADDRESS MAPPING.............................................................................................................. 70
INTERRUPT SELECTION ...................................................................................................... 70
DMA SELECTION...................................................................................................................70
PROGRAMMABLE REGISTERS............................................................................................ 70
Line Printer Data Register.......................................................................................... 70
Line Printer Status Register ....................................................................................... 71
Line Printer Control Register...................................................................................... 71
ADDITIONAL INFORMATION................................................................................................. 72
CHAPTER 10. OPTIONAL IDE INTERFACE...................................................................................... 73
HARD DISK MOUNTING........................................................................................................ 73
ENABLING THE ON-BOARD IDE CONTROLLER................................................................. 73
SINGLE BOARD APPLICATIONS.......................................................................................... 73
STAR SYSTEM APPLICATIONS............................................................................................ 74
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