Ziatech Corporation ZT 8906 User manual

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ZT 8905/8906
ZT 8905/8906
H A R D W A R E M A N U A L
For ZT 8905 Revision A.3
Single Board Computer
with Pentium Processor
®
For ZT 8906 Revision A.3
ZT M8905
September 9, 1997
102575
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ZT 8905/8906
ZT 8905/8906
H A R D W A R E M A N U A L
For ZT 8905 Revision A.3
Single Board Computer
with Pentium Processor
®
For ZT 8906 Revision A.3
ZT M8905
September 9, 1997
102575
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

ALI is a registered trademark and Aladdin is a trademark of Acer Laboratories, Inc.
CompactPCI is a trademark of the PCI Industrial Computers Manufacturers Group.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Intel and Pentium are registered trademarks of Intel Corporation.
OS/2 and PC/AT are registered trademarks of International Business Machines, Inc.
QNX is a registered trademark of Quantum Software Systems Ltd.
STD 32 is a registered trademark of Ziatech Corporation.
STD 32 STAR SYSTEM is a trademark of Ziatech Corporation.
UNIX is a registered trademark of AT&T Bell Laboratories.
VRTX32 is a registered trademark of Ready Systems, Inc.
Windows is a trademark and MS-DOS is a registered trademark of Microsoft Corporation.
All other brand or product names may be trademarks or registered trademarks of their respective
holders.
©Copyright 1997 Ziatech Corporation
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WHAT'S IN THIS MANUAL?
This manual describes the operation and use of the ZT 8905/8906 Single Board Computer with
Pentium Processor. The term ZT 8905 is used throughout this manual to reference both the ZT 8905
and the ZT 8906, except where otherwise noted. Specific differences between the two are explicitly
stated. The following summarizes the focus of each major section in this manual.
Chapter 1, "Introduction," introduces the key features of the ZT 8905. It includes a product
definition, a list of product features, a functional block diagram, and a brief description of each block.
This chapter is most useful to those who wish to compare the features of the ZT 8905 against the
needs of a specific application.
Chapter 2, "Getting Started," summarizes the information needed to install and configure your
ZT 8905.
Chapter 3, "STD 32 Bus Interface," presents a detailed description of the ZT 8905 interface to the
STD 32 bus architecture. The topics discussed include compatibility, interrupt structure, and multiple
master operation.
Chapter 4, "Interrupt Controller," describes the two Intel-compatible 8259 cascaded interrupt
controllers. This chapter summarizes and illustrates the interrupt sources and the interrupt
controllers' programmable registers.
Chapter 5, "Counter/Timers," discusses the three programmable counter/timers. It includes a
diagram of the counter/timer architecture, a summary of operating modes, and descriptions of the
programmable registers.
Chapter 6, "DMA Controller," provides an overview of ZT 8905 DMA architecture and DMA
controller operation. Descriptions of DMA controller programmable registers are also included.
Chapter 7, "Real-Time Clock," lists the major features of the real-time clock and provides register
descriptions.
Chapter 8, "Serial Controller," discusses operation of the two serial ports and provides register
descriptions.
Chapter 9, "IEEE 1284 Parallel Port Interface," contains descriptions of the programmable
registers for the IEEE-1284 compatible printer interface.
Chapter 10, "Optional IDE Interface," covers the mounting and enabling of an optional local
Intelligent Drive Electronics (IDE) interface. It also discusses the types of configurations in which the
addition of a local hard disk can be an advantage.
Chapter 11, "System Registers," provides register descriptions and a brief overview of the System
registers used to control and monitor a variety of functions on the ZT 8905.
Chapter 12, "Watchdog Timer," explains operation of the watchdog timer and includes code for
arming and strobing the timer.
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Chapter 13, "PCI Mezzanine Local Bus," introduces the features of the Peripheral Component
Interconnect (PCI) local bus interface that provides a high speed path between the CPU and
peripherals.
Chapter 14, "Programmable LED," provides code for turning the LED on and off.
Appendix A, "Board Configuration," describes the software configuration registers, jumpers, and
cuttable traces on the ZT 8905. This appendix details factory default settings as well as information to
tailor your board to a specific application.
Appendix B, "Specifications," contains the electrical, environmental, and mechanical specifications
for the ZT 8905. It also provides illustrations of cables and connector pinouts, and tables showing
connector pin assignments.
Appendix C, "Customer Support," offers a product revision history, technical assistance and
warranty information, and the necessary information should you need to return your ZT 8905 for
repair.
Appendix D, "PCI Configuration Space Map," presents the generic layout of the PCI Configuration
Header for all PCI compliant devices. It also contains a table showing the PCI bus mapping of the
ZT 8905's on-board devices.
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CONTENTS
CHAPTER 1. INTRODUCTION ............................................................................................................. 1
PRODUCT DEFINITION........................................................................................................... 1
Stand Alone.................................................................................................................. 1
STD 32 Single Master.................................................................................................. 2
STD 32 Multiple Master (STAR SYSTEM)................................................................... 2
FEATURES OF THE ZT 8905................................................................................................... 2
DEVELOPMENT CONSIDERATIONS...................................................................................... 3
FUNCTIONAL BLOCKS............................................................................................................ 4
STD 32 Bus Interface................................................................................................... 5
Pentium Processors..................................................................................................... 5
Memory and I/O Addressing......................................................................................... 6
PCI Local Bus............................................................................................................... 6
Serial I/O....................................................................................................................... 6
Interrupts......................................................................................................................7
Counter/Timers............................................................................................................. 7
DMA.............................................................................................................................. 7
Watchdog Timer........................................................................................................... 7
Real-Time Clock........................................................................................................... 8
Keyboard Controller...................................................................................................... 8
IEEE® 1284 Parallel Port/Printer Interface .................................................................. 8
Speaker Interface......................................................................................................... 9
Optional IDE Interface.................................................................................................. 9
CHAPTER 2. GETTING STARTED..................................................................................................... 11
UNPACKING........................................................................................................................... 11
WHAT'S IN THE BOX?........................................................................................................... 11
SYSTEM REQUIREMENTS.................................................................................................... 11
MEMORY CONFIGURATION................................................................................................. 12
I/O CONFIGURATION ............................................................................................................ 13
CONNECTOR CONFIGURATION.......................................................................................... 15
JUMPER DESCRIPTIONS...................................................................................................... 16
ZT 8905 SETUP...................................................................................................................... 16
System Configuration Overview................................................................................. 17
Operating System Installation..................................................................................... 19
CHAPTER 3. STD 32 BUS INTERFACE............................................................................................. 21
STD 32 BACKGROUND ......................................................................................................... 21
STD-80 PERIPHERAL SUPPORT.......................................................................................... 21
Address Multiplexing .................................................................................................. 21
Interrupts.................................................................................................................... 22
I/O Expansion............................................................................................................. 22
DMA Slave Support.................................................................................................... 22
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Contents
STD 32 BUS COMPATIBILITY................................................................................................22
Standard Architecture.................................................................................................22
Extended Architecture.................................................................................................23
Multiprocessing...........................................................................................................23
STD 32 Compliance Levels ........................................................................................23
STD BUS INTERRUPTS .........................................................................................................24
Maskable Interrupts ....................................................................................................24
Non-Maskable Interrupts ............................................................................................26
RESET.....................................................................................................................................26
MULTIPLE MASTER AND INTELLIGENT I/O.........................................................................26
Multiple Master............................................................................................................27
Intelligent I/O...............................................................................................................27
Multiple Master Vs. Intelligent I/O...............................................................................28
Multiple Master System Requirements.......................................................................28
Multiple Master Reset.................................................................................................30
CHAPTER 4. INTERRUPT CONTROLLER.........................................................................................31
INTERRUPT SOURCES..........................................................................................................33
PROGRAMMABLE REGISTERS ............................................................................................33
Initialization Registers (ICW1-ICW4)..........................................................................34
Initialization Register ICW1..................................................................................35
Initialization Register ICW2..................................................................................35
Initialization Register ICW3..................................................................................35
Initialization Register ICW4..................................................................................36
Operational Registers (OCW1-OCW3) ......................................................................36
Operational Register OCW1 ................................................................................36
Operational Register OCW2 ................................................................................37
Operational Register OCW3 ................................................................................38
Status Registers (IRR, ISR, IPR)................................................................................38
Status Register IRR..............................................................................................38
Status Register ISR..............................................................................................39
Status Register IPR..............................................................................................39
Extended Mode Register ............................................................................................40
ADDITIONAL INFORMATION.................................................................................................40
CHAPTER 5. COUNTER/TIMERS.......................................................................................................41
PROGRAMMABLE REGISTERS ............................................................................................42
Count Registers and Count Latch...............................................................................42
Status Register ...........................................................................................................43
Control Register..........................................................................................................44
General Control Register......................................................................................44
Count Latch Control Register...............................................................................44
Multiple Latch Control Register ............................................................................45
ADDITIONAL INFORMATION.................................................................................................45
CHAPTER 6. DMA CONTROLLER .....................................................................................................47
ZT 8905 SPECIFICS................................................................................................................47
PROGRAMMABLE REGISTERS ............................................................................................48
Address Register ........................................................................................................50
Count Register............................................................................................................50
Status Register ...........................................................................................................51
Command Register.....................................................................................................51
Write Request Register...............................................................................................52
Write Single Mask Register ........................................................................................52
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Contents
Write Mode Register .................................................................................................. 53
DMA Extended Mode Register................................................................................... 53
Clear Byte Register .................................................................................................... 54
Clear Master Register ................................................................................................ 54
Clear Mask Register................................................................................................... 54
Write Mask Register................................................................................................... 54
DMA Page Register.................................................................................................... 55
DMA Extended Page Register ................................................................................... 55
ADDITIONAL INFORMATION................................................................................................. 55
CHAPTER 7. REAL-TIME CLOCK......................................................................................................57
PROGRAMMABLE REGISTERS............................................................................................ 57
Register A................................................................................................................... 58
Register B................................................................................................................... 58
Register C .................................................................................................................. 59
Register D .................................................................................................................. 59
ADDITIONAL INFORMATION................................................................................................. 59
CHAPTER 8. SERIAL CONTROLLER................................................................................................ 61
ZT 8905 SPECIFICS...............................................................................................................61
Address Mapping ....................................................................................................... 61
Interrupt Selection ...................................................................................................... 62
Handshake Signals .................................................................................................... 62
Serial Channel Interface............................................................................................. 62
PROGRAMMABLE REGISTERS............................................................................................ 62
Baud Rate Divisors..................................................................................................... 63
Divisor Latch LSB and MSB....................................................................................... 64
Interrupt Control Register........................................................................................... 64
Interrupt Status Register ............................................................................................ 65
Line Control Register.................................................................................................. 65
Line Status Register................................................................................................... 66
Modem Control Register ............................................................................................ 66
Modem Status Register.............................................................................................. 67
ADDITIONAL INFORMATION................................................................................................. 67
CHAPTER 9. IEEE-1284 PARALLEL PORT INTERFACE................................................................. 69
PARALLEL PORT CONFIGURATION OPTIONS................................................................... 69
ADDRESS MAPPING.............................................................................................................. 70
INTERRUPT SELECTION ...................................................................................................... 70
DMA SELECTION...................................................................................................................70
PROGRAMMABLE REGISTERS............................................................................................ 70
Line Printer Data Register.......................................................................................... 70
Line Printer Status Register ....................................................................................... 71
Line Printer Control Register...................................................................................... 71
ADDITIONAL INFORMATION................................................................................................. 72
CHAPTER 10. OPTIONAL IDE INTERFACE...................................................................................... 73
HARD DISK MOUNTING........................................................................................................ 73
ENABLING THE ON-BOARD IDE CONTROLLER................................................................. 73
SINGLE BOARD APPLICATIONS.......................................................................................... 73
STAR SYSTEM APPLICATIONS............................................................................................ 74
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Contents
CHAPTER 11. SYSTEM REGISTERS.................................................................................................75
PROGRAMMABLE REGISTERS ............................................................................................75
System Register 0.......................................................................................................75
System Register 1.......................................................................................................76
CHAPTER 12. WATCHDOG TIMER....................................................................................................77
WATCHDOG TIMER OPERATION.........................................................................................77
ADDITIONAL INFORMATION.................................................................................................77
CHAPTER 13. PCI MEZZANINE LOCAL BUS....................................................................................79
PCI OPERATION FREQUENCY.............................................................................................79
ADDITIONAL INFORMATION.................................................................................................79
CHAPTER 14. PROGRAMMABLE LED..............................................................................................81
APPENDIX A. BOARD CONFIGURATION..........................................................................................83
BIOS SETUP OVERVIEW.......................................................................................................83
ZT 8905-Specific SETUP Options ..............................................................................85
JUMPER OPTIONS AND LOCATIONS ..................................................................................85
JUMPER CROSS-REFERENCE TABLE.................................................................................87
JUMPER DESCRIPTIONS......................................................................................................87
W1A, W1B (CMOS RAM Erase) ................................................................................87
W1C (Boot From On-Board Flash Device).................................................................87
W1D (Reserved).........................................................................................................88
W1E (Reserved).........................................................................................................88
W1F (Temporary Master to ZT 8911).........................................................................88
W2, W3 (Reserved)....................................................................................................88
CUTTABLE TRACE OPTIONS AND LOCATIONS.................................................................88
CT1, CT2 (Frontplane DMA).......................................................................................89
APPENDIX B. SPECIFICATIONS........................................................................................................91
ELECTRICAL AND ENVIRONMENTAL..................................................................................91
Absolute Maximum Ratings........................................................................................91
DC Operating Characteristics.....................................................................................93
Battery Backup Characteristics...................................................................................93
STD Bus Loading Characteristics...............................................................................94
MECHANICAL .........................................................................................................................96
Card Dimensions and Weight.....................................................................................96
Connectors..................................................................................................................97
P/E (STD-80/STD 32 Bus) ...................................................................................98
J1 (L2 Cache Module)..........................................................................................99
J2 (Fan Connector) ..............................................................................................99
J3 (PCI Local Bus Interface) ..............................................................................100
J4 (VGA Transition Connector)..........................................................................101
J5 (Multi-I/O Connector).....................................................................................101
J6 (Floppy Disk Controller Interface)..................................................................103
J7 (IDE Hard Disk Interface)..............................................................................103
Cable.........................................................................................................................104
APPENDIX C. CUSTOMER SUPPORT.............................................................................................105
TECHNICAL/SALES ASSISTANCE......................................................................................105
REVISION HISTORY.............................................................................................................105
RELIABILITY..........................................................................................................................106
RETURNING FOR SERVICE................................................................................................107
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Contents
ZIATECH 5+5 WARRANTY.................................................................................................. 107
Five-Year Limited Warranty...................................................................................... 107
Special Extended Warranty Option.......................................................................... 108
Life Support Policy.................................................................................................... 108
APPENDIX D. PCI CONFIGURATION SPACE MAP........................................................................ 109
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Contents
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TABLES
Pentium Processor Comparison............................................................................................................. 5
Typical DRAM Configurations .............................................................................................................. 12
Connector Assignments....................................................................................................................... 15
Interrupt Controller Register Addressing.............................................................................................. 33
Counter/Timer Operating Modes.......................................................................................................... 42
Counter/Timer Register Addressing..................................................................................................... 42
Slave DMA I/O Port Addressing........................................................................................................... 49
DMA Page I/O Port Addressing............................................................................................................ 49
DMA Extended Page (A24-31) I/O Port Addressing ............................................................................ 49
Real-Time Clock Register Addressing ................................................................................................. 57
Serial Controller Register Addressing .................................................................................................. 62
Baud Rate Divisors Table..................................................................................................................... 63
Pentium Processors Maximum Ambient Temperatures....................................................................... 92
STD Bus Loading, P Connector ........................................................................................................... 94
STD Bus Loading, E Connector ........................................................................................................... 95
Connector Assignments....................................................................................................................... 97
J2 Fan Connector Pinout...................................................................................................................... 99
J3 PCI Local Bus Connector Pinout................................................................................................... 100
(For Revision A Boards and Higher)................................................................................................... 100
J4 VGA Transition Connector Pinout ................................................................................................. 101
J5 Multi-I/O Connector Pinout ............................................................................................................ 102
J7 IDE Hard Disk Connector Pinout................................................................................................... 103
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Tables
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ILLUSTRATIONS
Functional Block Diagram ...................................................................................................................... 4
J5 Multi-I/O Connector............................................................................................................................ 8
Memory Address Map .......................................................................................................................... 13
I/O Address Map................................................................................................................................... 14
Connector Locations...................................................................................................................... 15, 97
Socket T6C Location............................................................................................................................ 16
BIOS SETUP Utility: Screen 1....................................................................................................... 18, 84
BIOS SETUP Utility: Screen 2....................................................................................................... 18, 84
STD Bus Polled Interrupt Structure...................................................................................................... 25
STD Bus Vectored Interrupt Structure.................................................................................................. 25
Non-Maskable Interrupt Structure........................................................................................................ 26
Multiple Master Architecture................................................................................................................. 27
Intelligent I/O Architecture.................................................................................................................... 28
Socket T6C Location............................................................................................................................ 29
Interrupt Architecture............................................................................................................................ 32
Interrupt Initialization Programming...................................................................................................... 34
Initialization Register ICW1 .................................................................................................................. 35
Initialization Register ICW2 .................................................................................................................. 35
Master Initialization Register ICW3...................................................................................................... 35
Slave Initialization Register ICW3 ........................................................................................................ 35
Initialization Register ICW4 .................................................................................................................. 36
Operational Register OCW1................................................................................................................. 36
Operational Register OCW2................................................................................................................. 37
Operational Register OCW3................................................................................................................. 38
Status Register IRR.............................................................................................................................. 38
Status Register ISR.............................................................................................................................. 39
Status Register IPR.............................................................................................................................. 39
Extended Mode Register...................................................................................................................... 40
Counter/Timer Architecture.................................................................................................................. 41
Count Register High Byte..................................................................................................................... 43
Count Register Low Byte...................................................................................................................... 43
Status Register..................................................................................................................................... 43
General Control Register...................................................................................................................... 44
Count Latch Control Register............................................................................................................... 44
Multiple Latch Control Register ............................................................................................................ 45
DMA Architecture ................................................................................................................................. 48
Address Register (8-bit I/O).................................................................................................................. 50
Address Register (16-bit I/O)................................................................................................................ 50
Count Register...................................................................................................................................... 50
Status Register..................................................................................................................................... 51
Command Register .............................................................................................................................. 51
Write Request Register........................................................................................................................ 52
Write Single Mask Register.................................................................................................................. 52
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Illustrations
Write Mode Register.............................................................................................................................53
DMA Extended Mode Register .............................................................................................................53
Clear Byte Register...............................................................................................................................54
Clear Master Register...........................................................................................................................54
Clear Mask Register .............................................................................................................................54
Write Mask Register .............................................................................................................................54
DMA Page Register ..............................................................................................................................55
DMA Extended Page Register..............................................................................................................55
Register A .............................................................................................................................................58
Register B .............................................................................................................................................58
Register C.............................................................................................................................................59
Register D.............................................................................................................................................59
Divisor Latch LSB..................................................................................................................................64
Divisor Latch MSB.................................................................................................................................64
Interrupt Control Register......................................................................................................................64
Interrupt Status Register.......................................................................................................................65
Line Control Register ............................................................................................................................65
Line Status Register..............................................................................................................................66
Modem Control Register.......................................................................................................................66
Modem Status Register ........................................................................................................................67
Line Printer Data Register.....................................................................................................................70
Line Printer Status Register..................................................................................................................71
Line Printer Control Register.................................................................................................................71
System Register 0.................................................................................................................................75
System Register 1.................................................................................................................................76
WatchDog Timer Architecture ..............................................................................................................77
DOS Factory Default Jumper Configuration .........................................................................................86
Customer Jumper Configuration...........................................................................................................86
Cuttable Trace Locations......................................................................................................................89
ZT 8905 Key Parts................................................................................................................................91
Ambient Temperature Vs. Pentium Processor Case Temperature......................................................92
Board Dimensions.................................................................................................................................96
P/E Connector.......................................................................................................................................98
ZT 90205 Rev. 0 Multi-I/O Cable........................................................................................................104
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CHAPTER 1. INTRODUCTION
This chapter provides a brief introduction to the ZT 8905. It includes a product definition, a list of
product features, a functional block diagram, and a description of each block. Unpacking information
and installation instructions are found in Chapter 2, "Getting Started."
PRODUCT DEFINITION
The term ZT 8905 is used throughout this manual to reference both the ZT 8905 and the ZT 8906,
except where otherwise noted. Specific differences between the two are explicitly stated. Refer to
Appendix B for specifications.
ZT 8905
The ZT 8905 is a highly integrated, single board computer that is factory configured to operate with
the Pentium® (P54C) family of microprocessors. The board meets the needs of a wide range of
industrial control and processing applications by operating stand alone, as a single master in an
STD 32® architecture, or as a permanent or temporary master in an STD 32 STAR SYSTEM™
architecture. High speed peripheral operation is provided by an on-board PCI expansion interface.
ZT 8906
The ZT 8906 is physically a ZT 8905 with a three-slot CompactPCI™ enclosure attached to it. This
enclosure allows high-speed PCI peripherals to be used as a processing core, yet allows access to
the STD 32 Bus architecture for I/O available on that bus structure.
All other features of the ZT 8906 are identical to the ZT 8905 unless otherwise noted in this manual.
The following topics discuss stand-alone, STD 32 single master, and STD 32 multiple master (STAR
SYSTEM) operation.
Stand Alone
The ZT 8905 does not require an STD bus backplane to operate. The ZT 8905 is able to operate
stand-alone in many applications because of the large selection of the most commonly needed
peripheral devices. On-board peripheral devices include:
•2 or 4 Mbyte Flash file system for disk support •Counter/timers
•PCI local bus expansion port (CompactPCI compliant) •Watchdog timer
•Optional IDE hard disk interface •Real-time clock
•Keyboard controller
•Serial I/O
•Speaker interface
•Interrupt controllers
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Chapter 1. Introduction
2
STD 32 Single Master
The ZT 8905 supports additional memory and I/O through the STD 32 bus. Both Standard
Architecture (8- and 16-bit) and Extended Architecture (8-, 16-, and 32-bit) transfer types are
dynamically supported through the STD 32 interface. Jumperless configuration of interrupt, DMA, and
STD 32 bus memory and I/O space is configured through the BIOS SETUP utility. See the section
"ZT 8905 SETUP" in Chapter 2 for more information.
STD 32 Multiple Master (STAR SYSTEM)
The ZT 8905 is configurable to operate in a multiple master architecture as a Permanent Master or a
Temporary Master. With this architecture, up to seven ZT 8905 boards share STD bus memory and
I/O resources. The Permanent Master provides the system clock and reset function and also
provides the pull-up signals for the open-collector signals on the STD 32 bus. The Permanent Master
is also responsible for initializing shared memory and other system I/O on behalf of any Temporary
Masters. The STAR BIOS manages all of the system initialization.
FEATURES OF THE ZT 8905
•STD 32 bus compatible
•PCI compatible local bus (CompactPCI compliant)
•Single and multiple master operation
•Pentium processor CPUs to 200 MHz
•Numeric coprocessor support (Pentium)
•16 Kbytes of CPU cache (expandable with L2 cache)
•Optional IDE hard disk interface (local to ZT 8905)
•8, 16, 32, or 48 Mbytes of DRAM memory
•2 Mbytes of Flash memory (expandable to 4 Mbytes)
•Optional 32-bit PCI local bus peripheral support (through CompactPCI)
--Super VGA (640x480x16M through 1280x1024x64K)
--Contact Ziatech for additional peripherals
•Standard AT® peripherals include:
--Two enhanced interrupt controllers (8259)
--Three counter/timers (one 8254)
--Real-time clock/CMOS RAM (146818)
--Two enhanced DMA controllers (8237)
--8042 compatible keyboard controller
•Centronics printer port (ECP/EPP compatible)
•Two 16C550 RS-232 serial ports
•Single stage watchdog timer
•Speaker interface
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Chapter 1. Introduction
3
•On-board high efficiency 3.3 V DC-DC converter
•Push-button reset
•Software programmable LED
•DC power monitors (3.3 V and 5 V)
•Compatible with the following software: MS-DOS®, OS/2®, UNIX®, QNX®, VRTX32®, Windows™
3.1 and 3.11, Windows 95, and Windows NT
•DOS and STAR BIOS options
•STD 32 bus standard 4.5" x 6.5" board format
•+5 V-only operation (fan/heatsink requires +12 V)
•Burned in at 55° Celsius and tested to guarantee reliability
•Five-year warranty
DEVELOPMENT CONSIDERATIONS
Ziatech offers two software development systems for ZT 8905 applications: DOS and the STD 32
STAR SYSTEM.
Ziatech DOS is Microsoft's MS-DOS residing on the ZT 8905. The DOS system provides a
development platform similar to a PC, enabling applications to be developed quickly. DOS includes
support for many of the ZT 8905 peripherals and is supported by a large number of development
tools such as program editors, compilers, assemblers, and debuggers. Refer to the Ziatech system
manual for configuration and operating instructions.
The STD 32 STAR SYSTEM is the DOS platform operating on more than one master in a single
STD bus system. Each master includes local memory, local I/O, and the DOS operating system.
Each master is capable of sharing STD bus memory and I/O, such as fixed disks, floppy disks, and
video. Refer to the STAR SYSTEM operating manual for configuration and operating instructions.
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