Ziatech Corporation ZT 8907 Instructions for use

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ZT 8907
Single Board Computer
with IntelDX4™ Microprocessor
Hardware User Manual

ÛZIATECH 2
CONTENTS
MANUAL ORGANIZATION.......................................................................................................................... 6
1. INTRODUCTION ...................................................................................................................................... 8
PRODUCT DEFINITION.................................................................................................................. 8
STAND-ALONE OPERATION ............................................................................................ 8
STD-80 OR STD 32 SINGLE MASTER ARCHITECTURE ................................................ 9
STD 32 MULTIPLE MASTER ARCHITECTURE................................................................ 9
FEATURES ...................................................................................................................................... 9
DEVELOPMENT CONSIDERATIONS .......................................................................................... 10
FUNCTIONAL BLOCKS ................................................................................................................ 11
STD BUS INTERFACE ..................................................................................................... 12
486SX/DX4 PROCESSORS............................................................................................. 13
MEMORY AND I/O ADDRESSING .................................................................................. 13
PCI BUS VIDEO ............................................................................................................... 13
SERIAL I/O ....................................................................................................................... 14
PARALLEL I/O .................................................................................................................. 14
INTERRUPTS ................................................................................................................... 14
COUNTER/TIMERS.......................................................................................................... 14
DMA .................................................................................................................................. 15
WATCHDOG TIMER ........................................................................................................ 15
REAL-TIME CLOCK ......................................................................................................... 15
KEYBOARD CONTROLLER ............................................................................................ 15
PARALLEL PRINTER PORT INTERFACE ...................................................................... 15
SPEAKER INTERFACE.................................................................................................... 16
AC POWER-FAIL PROTECTION..................................................................................... 16
OPTIONAL HARD DISK INTERFACE.............................................................................. 16
OPTIONAL FLOPPY DISK INTERFACE.......................................................................... 16
2. GETTING STARTED .............................................................................................................................. 17
UNPACKING.................................................................................................................................. 17
SYSTEM REQUIREMENTS .......................................................................................................... 17
MEMORY CONFIGURATION........................................................................................................ 18
I/O CONFIGURATION ................................................................................................................... 19
CONNECTORS ............................................................................................................................. 22
JUMPER DESCRIPTIONS ............................................................................................................ 22
REMOVING THE ZPM MEZZANINE CARD ................................................................................. 22
SETUP ........................................................................................................................................... 22
BIOS SETUP SCREENS .................................................................................................. 23
SYSTEM CONFIGURATION OVERVIEW ....................................................................... 23
OPERATING SYSTEM INSTALLATION .......................................................................... 24
3. STD BUS INTERFACE........................................................................................................................... 26
STD-80 AND STD 32 OPERATION .............................................................................................. 26
STD 32 OPERATION........................................................................................................ 26
STD-80 BUS COMPATIBILITY...................................................................................................... 27
ADDRESS MULTIPLEXING ............................................................................................. 27
INTERRUPTS ................................................................................................................... 27
I/O EXPANSION ............................................................................................................... 27
EXTERNAL MASTERS AND DMA SLAVES.................................................................... 27
STD 32 BUS COMPATIBILITY...................................................................................................... 28
COMPLIANCE LEVELS.................................................................................................... 28
STD BUS INTERRUPTS ............................................................................................................... 29
MASKABLE INTERRUPTS............................................................................................... 29
NON-MASKABLE INTERRUPTS ..................................................................................... 31

Contents
ÛZIATECH 3
RESET ........................................................................................................................................... 31
MULTIPLE MASTER AND INTELLIGENT I/O............................................................................... 32
MULTIPLE MASTER ........................................................................................................ 32
INTELLIGENT I/O ............................................................................................................. 33
MULTIPLE MASTER VS. INTELLIGENT I/O ................................................................... 34
MULTIPLE MASTER SYSTEM REQUIREMENTS .......................................................... 34
MULTIPLE MASTER SYSTEM RESET ........................................................................... 35
4. INTERRUPT CONTROLLER ................................................................................................................. 36
INTERRUPT SOURCES................................................................................................................ 38
PROGRAMMABLE REGISTERS .................................................................................................. 39
ADDITIONAL INFORMATION ....................................................................................................... 39
5. COUNTER/TIMERS................................................................................................................................ 40
PROGRAMMABLE REGISTERS .................................................................................................. 42
ADDITIONAL INFORMATION ....................................................................................................... 43
6. DMA CONTROLLER.............................................................................................................................. 44
DMA CHANNELS .......................................................................................................................... 45
OPERATING MODES.................................................................................................................... 46
DMA SLAVE OPERATION ............................................................................................... 47
PROGRAMMABLE REGISTERS .................................................................................................. 48
7. REAL-TIME CLOCK............................................................................................................................... 50
PROGRAMMABLE REGISTERS .................................................................................................. 50
ADDITIONAL INFORMATION ....................................................................................................... 51
8. SERIAL CONTROLLER......................................................................................................................... 52
PROGRAMMABLE REGISTERS .................................................................................................. 53
ADDITIONAL INFORMATION ....................................................................................................... 53
9. PARALLEL PRINTER PORT INTERFACE ........................................................................................... 54
PARALLEL PRINTER PORT CONFIGURATION OPTIONS ........................................................ 54
ADDRESS MAPPING .................................................................................................................... 54
INTERRUPT SELECTION .............................................................................................................55
PROGRAMMABLE REGISTERS .................................................................................................. 55
ADDITIONAL INFORMATION ....................................................................................................... 55
10. PARALLEL I/O ..................................................................................................................................... 56
FUNCTIONAL DESCRIPTION ...................................................................................................... 56
OUTPUT LATCH .............................................................................................................. 57
OUTPUT BUFFER............................................................................................................ 57
INPUT BUFFER................................................................................................................ 58
DEBOUNCE CONTROL LOGIC....................................................................................... 58
EVENT SENSE DETECTION LOGIC............................................................................... 58
PROGRAMMABLE REGISTERS .................................................................................................. 59
PORT DATA REGISTERS................................................................................................ 61
WRITE INHIBIT / BANK ADDRESS REGISTER.............................................................. 61
PORT EVENT SENSE REGISTER .................................................................................. 62
EVENT SENSE MANAGE REGISTER............................................................................. 63
BANK ADDRESS REGISTER .......................................................................................... 64
DEBOUNCE CONFIGURE REGISTER ........................................................................... 65
DEBOUNCE DURATION REGISTER (PORTS 0-3) ........................................................ 65
DEBOUNCE DURATION REGISTER (PORTS 4-5) ........................................................ 66
DEBOUNCE CLOCK REGISTER..................................................................................... 66
BANK SELECT REGISTER.............................................................................................. 67
11. SYSTEM REGISTERS ......................................................................................................................... 68
PROGRAMMABLE REGISTERS .................................................................................................. 68
SYSTEM REGISTER 1..................................................................................................... 68

Contents
ÛZIATECH 4
SYSTEM REGISTER 2..................................................................................................... 69
SYSTEM REGISTER 3..................................................................................................... 70
ADDITIONAL INFORMATION ....................................................................................................... 70
12. WATCHDOG TIMER ............................................................................................................................ 71
WATCHDOG TIMER OPERATION ............................................................................................... 71
ADDITIONAL INFORMATION ....................................................................................................... 72
13. PCI MEZZANINE LOCAL BUS ............................................................................................................ 73
PCI OPERATION FREQUENCY ................................................................................................... 73
ADDITIONAL INFORMATION ....................................................................................................... 73
14. PROGRAMMABLE LED ...................................................................................................................... 74
15. AC POWER-FAIL ................................................................................................................................. 76
16. MEMORY MODULE SOCKET (U17) ................................................................................................... 78
BIOS RECOVERY ......................................................................................................................... 78
USER STATIC RAM ...................................................................................................................... 79
STAR SYSTEM VIDEO EMULATION SRAM................................................................................ 80
17. OPTIONAL IDE INTERFACE............................................................................................................... 81
HARD DISK MOUNTING............................................................................................................... 81
SELECTING IDE OPERATION TYPE........................................................................................... 81
STAR SYSTEM APPLICATIONS .................................................................................................. 82
SINGLE BOARD APPLICATIONS................................................................................................. 82
18. OPTIONAL LOCAL FLOPPY DISK INTERFACE ............................................................................... 83
A. BOARD CONFIGURATION................................................................................................................... 84
BIOS SETUP OVERVIEW .............................................................................................................84
ZT 8907-SPECIFIC SETUP OPTIONS ............................................................................ 86
JUMPER OPTIONS AND LOCATIONS ........................................................................................ 86
JUMPER DESCRIPTIONS ............................................................................................................ 88
W1 (MULTIPLE MASTER INTERRUPT).......................................................................... 88
W2 (PROM/SRAM SELECTION) ..................................................................................... 89
W3 (CMOS RAM ERASE) ................................................................................................ 90
W4 (SRAM BATTERY BACKUP) ..................................................................................... 90
W5 (LOCAL KEYBOARD DISABLE) ................................................................................ 90
W6, W7 (NON-MASKABLE INTERRUPTS) ..................................................................... 91
W8 (STD BUS ACCESS DISABLE) ................................................................................. 91
W9 (FLASH WRITE PROTECT)....................................................................................... 92
J12 (PORT 80 DECODE) ................................................................................................. 92
RP1, RP2 (PERMANENT MASTER PULLUPS) .............................................................. 92
CUTTABLE TRACE OPTIONS AND LOCATIONS ....................................................................... 93
CT4-CT6 (COUNTER/TIMER CLOCK SOURCES) ......................................................... 95
CT7, CT8 (IRQ15 INPUT SOURCE SELECTION)........................................................... 96
CT16, CT17, CT25, CT29, CT39 (FRONTPLANE DMA CHANNEL SELECTION) ......... 97
CT46, CT47 (BOARD REVISION).................................................................................... 97
CT48 (INTRQ4* STD CONNECTION).............................................................................. 97
CT53 (STD RESET CONFIGURATION) .......................................................................... 98
B. SPECIFICATIONS ................................................................................................................................. 99
ELECTRICAL AND ENVIRONMENTAL ........................................................................................ 99
ABSOLUTE MAXIMUM RATINGS ................................................................................... 99
DC OPERATING CHARACTERISTICS ......................................................................... 100
BATTERY BACKUP CHARACTERISTICS .................................................................... 101
STD-80 COMPATIBILITY ............................................................................................... 101
STD BUS LOADING CHARACTERISTICS .................................................................... 101
MECHANICAL.............................................................................................................................. 104

Contents
ÛZIATECH 5
BOARD DIMENSIONS AND WEIGHT ........................................................................... 104
CONNECTORS .............................................................................................................. 105
STD 32 P/E CONNECTOR............................................................................................. 107
CABLES .......................................................................................................................... 122
C. DIGITAL I/O ASIC SYSTEM SETUP CONSIDERATIONS................................................................. 127
PREVENTING SYSTEM LATCHUP............................................................................................ 127
POWER SUPPLY SEQUENCE MISMATCH.................................................................. 128
SIGNAL LEVEL MISMATCH .......................................................................................... 130
PROTECTING CMOS INPUTS ................................................................................................... 131
RISE TIMES.................................................................................................................... 131
INDUCTIVE COUPLING................................................................................................. 132
ADDITIONAL INFORMATION ..................................................................................................... 133
D. PCI CONFIGURATION SPACE MAP ................................................................................................. 134
E. ZT 8907 VS. ZT 8902: TECHNICAL DIFFERENCES ......................................................................... 136
ZT 8907 NEW FEATURES .......................................................................................................... 136
ZT 8907 MECHANICAL ISSUES................................................................................................. 136
ZT 8907 PROGRAMMING ISSUES ............................................................................................ 138
ZT 260 AND ZT 310 ENCLOSURES........................................................................................... 138
F. CUSTOMER SUPPORT....................................................................................................................... 139
TECHNICAL/SALES ASSISTANCE ............................................................................................ 139
RELIABILITY................................................................................................................................ 139
RETURNING FOR SERVICE ...................................................................................................... 139
ZIATECH WARRANTY ................................................................................................................ 140
TRADEMARKS ............................................................................................................................ 141

ÛZIATECH 6
MANUAL ORGANIZATION
This manual describes the operation and use of the ZT 8907 Single Board Computer
with IntelDX4™ Microprocessor. The following summarizes the focus of each major
section in this manual.
Chapter 1, "Introduction," introduces the key features of the ZT 8907. It includes a
product definition, a list of product features, a functional block diagram, and a
description of each block.
Chapter 2, "Getting Started," provides a summary of the information needed to install
and configure your ZT 8907.
Chapter 3, "STD Bus Interface," presents a detailed description of the ZT 8907
interface to the STD-80 and STD 32 bus architectures. The topics discussed include
compatibility, interrupt structure, and multiple master operation.
Chapter 4, "Interrupt Controller," describes the two Intel-compatible 8259 cascaded
interrupt controllers. This chapter summarizes the interrupt sources and the interrupt
controllers' register addressing.
Chapter 5, "Counter/Timers," discusses the six programmable counter/timers. It
includes a diagram of the counter/timer architecture, and a summary of the operating
modes and the programmable registers.
Chapter 6, "DMA Controller," provides an overview of ZT 8907 DMA architecture and
briefly describes the DMA controller programmable registers.
Chapter 7, "Real-Time Clock," lists the major features of the real-time clock and briefly
describes the real-time clock programmable registers.
Chapter 8, "Serial Controller," discusses operation of the two serial ports and briefly
describes the programmable registers.
Chapter 9, "Parallel Printer Port Interface," describes the different modes for the
Centronics-compatible printer interface. Address mapping, interrupt selection, and
programmable registers are also discussed.
Chapter 10, "Parallel I/O," discusses the general operation of the six parallel ports and
the functional blocks of the parallel I/O. It also provides register descriptions and
illustrations.
Chapter 11, "System Registers," provides register descriptions and illustrations as
well as a brief overview of the three System registers used to control and monitor a
variety of functions on the ZT 8907.

Manual Organization
ÛZIATECH 7
Chapter 12, "Watchdog Timer," explains operation of the watchdog timer and includes
code for arming and strobing the timer.
Chapter 13, "PCI Mezzanine Local Bus," introduces the features of the PCI bus
interface that allows the CPU high speed access to PCI mezzanine peripherals.
Chapter 14, "Programmable LED," provides code for turning the LED on and off.
Chapter 15, "AC Power-Fail," explains AC power-fail detection.
Chapter 16, "Memory Module Socket (U17)," explains the various functions of socket
U17 including the optional static RAM that can be used to hold critical system
information in the event of power loss.
Chapter 17, "Optional IDE Interface," provides details on the optional high speed local
IDE disk drive interface.
Chapter 18, "Optional Local Floppy Disk Interface," provides details on the optional
local floppy disk drive interface.
Appendix A, "Board Configuration," describes the jumpers and cuttable traces on the
ZT 8907. This appendix details factory default settings as well as information to tailor
your board to a specific application.
Appendix B, "Specifications," contains the electrical, environmental, and mechanical
specifications for the ZT 8907. This appendix also provides illustrations of cables and
connector locations, and tables showing connector pin assignments.
Appendix C, "Digital I/O ASIC System Setup Considerations," offers tips for system
configuration to prevent latchup conditions.
Appendix D, "PCI Configuration Space Map," presents the generic layout of the PCI
Configuration Header for all PCI compliant devices. It also contains a table showing the
PCI bus mapping of the ZT 8907's onboard devices.
Appendix E, "ZT 8907 Vs. ZT 8902: Technical Differences," describes the technical
differences between the ZT 8907 and the ZT 8902 single board computers. It includes
information to help existing ZT 8902 customers adapt their applications to the ZT 8907.
Appendix F, "Customer Support," offers technical assistance and warranty
information, and the necessary information should you need to return your ZT 8907 for
repair.

ÛZIATECH 8
1. INTRODUCTION
This chapter provides a brief introduction to the ZT 8907. It includes a product definition,
a list of product features, and descriptions of each of the ZT 8907's functional blocks.
Reference unpacking information and installation instructions are found in Chapter 2,
"Getting Started."
PRODUCT DEFINITION
ZT 8907
The ZT 8907 is a highly integrated, single board computer that is factory configured to
operate with a 100 MHz i486™ IntelDX4™ microprocessor. (Contact Ziatech for support
of other 486 microprocessor configurations). The board meets the needs of a wide
range of industrial control and processing applications by operating stand alone, as a
single master in an STD 32®architecture, or as a permanent or temporary master in an
STD 32 architecture.
ZT 89LT07
The ZT 89LT07, a low temperature version with an extended operating range for harsh
environments, is now available on a build-to-order basis. The ZT 8907 operating range
of 0º to +70º C is extended in the ZT 89LT07 to -40º +70º C. Contact Ziatech for details.
Stand-Alone Operation
The ZT 8907 does not require an STD bus backplane to operate. The ZT 8907 is able to
operate stand alone in many applications because of the large selection of the most
commonly needed peripheral devices. Peripheral devices include:
•Parallel I/O
•Counter/timers
•Real-time clock
•Watchdog timer
•Speaker interface
•Keyboard controller
•Interrupt controllers
•AC/DC power-fail detection
•Optional local PCI video support (VGA/Flat-Panel)
•Optional static RAM memory with battery backup

1. Introduction
ÛZIATECH 9
•Bi-directional multi-mode printer interface
•Optional local high speed IDE disk drive
•Serial I/O (two 16550 compatible ports)
•Optional local floppy drive interface
•Flash file system (up to 4 Mbytes)
•COM1/COM2 (16550 compatible)
STD-80 or STD 32 Single Master Architecture
The ZT 8907 supports additional memory and I/O through the STD bus. In an STD-80
architecture, all 16-bit data transfers are automatically reduced to 8-bit transfers for
complete backwards compatibility with STD-80 boards. In an STD 32 architecture, the
data transfers are dynamically adjusted to support 8-bit and 16-bit boards.
See Chapter 3, "STD Bus Interface," for a detailed description of the ZT 8907 interface
to the STD bus architecture.
STD 32 Multiple Master Architecture
The ZT 8907 can be configured to operate in a multiple master architecture as a
permanent master or a temporary master. With this architecture, up to seven ZT 8907
boards share STD bus memory and I/O resources.
See Chapter 3, "STD Bus Interface," for a detailed description of the ZT 8907 interface
to the STD bus architecture.
FEATURES
•STD 32 bus compatible
•Occupies single STD bus slot
•Single and multiple master operation
•25 to 100 MHz 486SX/DX4 operation
•Numeric coprocessor support (486DX4)
•8 Kbytes of CPU cache (16 Kbytes on DX4)
•4, 8, 16, or 32 Mbytes of DRAM memory (EDO)
•2 or 4 Mbytes of flash memory
•Optional 32-bit PCI bus video support
•Standard AT®peripherals include: