Ziatech Corporation ZT 8907 Instructions for use

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ZT 8907
Single Board Computer
with IntelDX4™ Microprocessor
Hardware User Manual

ÛZIATECH 2
CONTENTS
MANUAL ORGANIZATION.......................................................................................................................... 6
1. INTRODUCTION ...................................................................................................................................... 8
PRODUCT DEFINITION.................................................................................................................. 8
STAND-ALONE OPERATION ............................................................................................ 8
STD-80 OR STD 32 SINGLE MASTER ARCHITECTURE ................................................ 9
STD 32 MULTIPLE MASTER ARCHITECTURE................................................................ 9
FEATURES ...................................................................................................................................... 9
DEVELOPMENT CONSIDERATIONS .......................................................................................... 10
FUNCTIONAL BLOCKS ................................................................................................................ 11
STD BUS INTERFACE ..................................................................................................... 12
486SX/DX4 PROCESSORS............................................................................................. 13
MEMORY AND I/O ADDRESSING .................................................................................. 13
PCI BUS VIDEO ............................................................................................................... 13
SERIAL I/O ....................................................................................................................... 14
PARALLEL I/O .................................................................................................................. 14
INTERRUPTS ................................................................................................................... 14
COUNTER/TIMERS.......................................................................................................... 14
DMA .................................................................................................................................. 15
WATCHDOG TIMER ........................................................................................................ 15
REAL-TIME CLOCK ......................................................................................................... 15
KEYBOARD CONTROLLER ............................................................................................ 15
PARALLEL PRINTER PORT INTERFACE ...................................................................... 15
SPEAKER INTERFACE.................................................................................................... 16
AC POWER-FAIL PROTECTION..................................................................................... 16
OPTIONAL HARD DISK INTERFACE.............................................................................. 16
OPTIONAL FLOPPY DISK INTERFACE.......................................................................... 16
2. GETTING STARTED .............................................................................................................................. 17
UNPACKING.................................................................................................................................. 17
SYSTEM REQUIREMENTS .......................................................................................................... 17
MEMORY CONFIGURATION........................................................................................................ 18
I/O CONFIGURATION ................................................................................................................... 19
CONNECTORS ............................................................................................................................. 22
JUMPER DESCRIPTIONS ............................................................................................................ 22
REMOVING THE ZPM MEZZANINE CARD ................................................................................. 22
SETUP ........................................................................................................................................... 22
BIOS SETUP SCREENS .................................................................................................. 23
SYSTEM CONFIGURATION OVERVIEW ....................................................................... 23
OPERATING SYSTEM INSTALLATION .......................................................................... 24
3. STD BUS INTERFACE........................................................................................................................... 26
STD-80 AND STD 32 OPERATION .............................................................................................. 26
STD 32 OPERATION........................................................................................................ 26
STD-80 BUS COMPATIBILITY...................................................................................................... 27
ADDRESS MULTIPLEXING ............................................................................................. 27
INTERRUPTS ................................................................................................................... 27
I/O EXPANSION ............................................................................................................... 27
EXTERNAL MASTERS AND DMA SLAVES.................................................................... 27
STD 32 BUS COMPATIBILITY...................................................................................................... 28
COMPLIANCE LEVELS.................................................................................................... 28
STD BUS INTERRUPTS ............................................................................................................... 29
MASKABLE INTERRUPTS............................................................................................... 29
NON-MASKABLE INTERRUPTS ..................................................................................... 31

Contents
ÛZIATECH 3
RESET ........................................................................................................................................... 31
MULTIPLE MASTER AND INTELLIGENT I/O............................................................................... 32
MULTIPLE MASTER ........................................................................................................ 32
INTELLIGENT I/O ............................................................................................................. 33
MULTIPLE MASTER VS. INTELLIGENT I/O ................................................................... 34
MULTIPLE MASTER SYSTEM REQUIREMENTS .......................................................... 34
MULTIPLE MASTER SYSTEM RESET ........................................................................... 35
4. INTERRUPT CONTROLLER ................................................................................................................. 36
INTERRUPT SOURCES................................................................................................................ 38
PROGRAMMABLE REGISTERS .................................................................................................. 39
ADDITIONAL INFORMATION ....................................................................................................... 39
5. COUNTER/TIMERS................................................................................................................................ 40
PROGRAMMABLE REGISTERS .................................................................................................. 42
ADDITIONAL INFORMATION ....................................................................................................... 43
6. DMA CONTROLLER.............................................................................................................................. 44
DMA CHANNELS .......................................................................................................................... 45
OPERATING MODES.................................................................................................................... 46
DMA SLAVE OPERATION ............................................................................................... 47
PROGRAMMABLE REGISTERS .................................................................................................. 48
7. REAL-TIME CLOCK............................................................................................................................... 50
PROGRAMMABLE REGISTERS .................................................................................................. 50
ADDITIONAL INFORMATION ....................................................................................................... 51
8. SERIAL CONTROLLER......................................................................................................................... 52
PROGRAMMABLE REGISTERS .................................................................................................. 53
ADDITIONAL INFORMATION ....................................................................................................... 53
9. PARALLEL PRINTER PORT INTERFACE ........................................................................................... 54
PARALLEL PRINTER PORT CONFIGURATION OPTIONS ........................................................ 54
ADDRESS MAPPING .................................................................................................................... 54
INTERRUPT SELECTION .............................................................................................................55
PROGRAMMABLE REGISTERS .................................................................................................. 55
ADDITIONAL INFORMATION ....................................................................................................... 55
10. PARALLEL I/O ..................................................................................................................................... 56
FUNCTIONAL DESCRIPTION ...................................................................................................... 56
OUTPUT LATCH .............................................................................................................. 57
OUTPUT BUFFER............................................................................................................ 57
INPUT BUFFER................................................................................................................ 58
DEBOUNCE CONTROL LOGIC....................................................................................... 58
EVENT SENSE DETECTION LOGIC............................................................................... 58
PROGRAMMABLE REGISTERS .................................................................................................. 59
PORT DATA REGISTERS................................................................................................ 61
WRITE INHIBIT / BANK ADDRESS REGISTER.............................................................. 61
PORT EVENT SENSE REGISTER .................................................................................. 62
EVENT SENSE MANAGE REGISTER............................................................................. 63
BANK ADDRESS REGISTER .......................................................................................... 64
DEBOUNCE CONFIGURE REGISTER ........................................................................... 65
DEBOUNCE DURATION REGISTER (PORTS 0-3) ........................................................ 65
DEBOUNCE DURATION REGISTER (PORTS 4-5) ........................................................ 66
DEBOUNCE CLOCK REGISTER..................................................................................... 66
BANK SELECT REGISTER.............................................................................................. 67
11. SYSTEM REGISTERS ......................................................................................................................... 68
PROGRAMMABLE REGISTERS .................................................................................................. 68
SYSTEM REGISTER 1..................................................................................................... 68

Contents
ÛZIATECH 4
SYSTEM REGISTER 2..................................................................................................... 69
SYSTEM REGISTER 3..................................................................................................... 70
ADDITIONAL INFORMATION ....................................................................................................... 70
12. WATCHDOG TIMER ............................................................................................................................ 71
WATCHDOG TIMER OPERATION ............................................................................................... 71
ADDITIONAL INFORMATION ....................................................................................................... 72
13. PCI MEZZANINE LOCAL BUS ............................................................................................................ 73
PCI OPERATION FREQUENCY ................................................................................................... 73
ADDITIONAL INFORMATION ....................................................................................................... 73
14. PROGRAMMABLE LED ...................................................................................................................... 74
15. AC POWER-FAIL ................................................................................................................................. 76
16. MEMORY MODULE SOCKET (U17) ................................................................................................... 78
BIOS RECOVERY ......................................................................................................................... 78
USER STATIC RAM ...................................................................................................................... 79
STAR SYSTEM VIDEO EMULATION SRAM................................................................................ 80
17. OPTIONAL IDE INTERFACE............................................................................................................... 81
HARD DISK MOUNTING............................................................................................................... 81
SELECTING IDE OPERATION TYPE........................................................................................... 81
STAR SYSTEM APPLICATIONS .................................................................................................. 82
SINGLE BOARD APPLICATIONS................................................................................................. 82
18. OPTIONAL LOCAL FLOPPY DISK INTERFACE ............................................................................... 83
A. BOARD CONFIGURATION................................................................................................................... 84
BIOS SETUP OVERVIEW .............................................................................................................84
ZT 8907-SPECIFIC SETUP OPTIONS ............................................................................ 86
JUMPER OPTIONS AND LOCATIONS ........................................................................................ 86
JUMPER DESCRIPTIONS ............................................................................................................ 88
W1 (MULTIPLE MASTER INTERRUPT).......................................................................... 88
W2 (PROM/SRAM SELECTION) ..................................................................................... 89
W3 (CMOS RAM ERASE) ................................................................................................ 90
W4 (SRAM BATTERY BACKUP) ..................................................................................... 90
W5 (LOCAL KEYBOARD DISABLE) ................................................................................ 90
W6, W7 (NON-MASKABLE INTERRUPTS) ..................................................................... 91
W8 (STD BUS ACCESS DISABLE) ................................................................................. 91
W9 (FLASH WRITE PROTECT)....................................................................................... 92
J12 (PORT 80 DECODE) ................................................................................................. 92
RP1, RP2 (PERMANENT MASTER PULLUPS) .............................................................. 92
CUTTABLE TRACE OPTIONS AND LOCATIONS ....................................................................... 93
CT4-CT6 (COUNTER/TIMER CLOCK SOURCES) ......................................................... 95
CT7, CT8 (IRQ15 INPUT SOURCE SELECTION)........................................................... 96
CT16, CT17, CT25, CT29, CT39 (FRONTPLANE DMA CHANNEL SELECTION) ......... 97
CT46, CT47 (BOARD REVISION).................................................................................... 97
CT48 (INTRQ4* STD CONNECTION).............................................................................. 97
CT53 (STD RESET CONFIGURATION) .......................................................................... 98
B. SPECIFICATIONS ................................................................................................................................. 99
ELECTRICAL AND ENVIRONMENTAL ........................................................................................ 99
ABSOLUTE MAXIMUM RATINGS ................................................................................... 99
DC OPERATING CHARACTERISTICS ......................................................................... 100
BATTERY BACKUP CHARACTERISTICS .................................................................... 101
STD-80 COMPATIBILITY ............................................................................................... 101
STD BUS LOADING CHARACTERISTICS .................................................................... 101
MECHANICAL.............................................................................................................................. 104

Contents
ÛZIATECH 5
BOARD DIMENSIONS AND WEIGHT ........................................................................... 104
CONNECTORS .............................................................................................................. 105
STD 32 P/E CONNECTOR............................................................................................. 107
CABLES .......................................................................................................................... 122
C. DIGITAL I/O ASIC SYSTEM SETUP CONSIDERATIONS................................................................. 127
PREVENTING SYSTEM LATCHUP............................................................................................ 127
POWER SUPPLY SEQUENCE MISMATCH.................................................................. 128
SIGNAL LEVEL MISMATCH .......................................................................................... 130
PROTECTING CMOS INPUTS ................................................................................................... 131
RISE TIMES.................................................................................................................... 131
INDUCTIVE COUPLING................................................................................................. 132
ADDITIONAL INFORMATION ..................................................................................................... 133
D. PCI CONFIGURATION SPACE MAP ................................................................................................. 134
E. ZT 8907 VS. ZT 8902: TECHNICAL DIFFERENCES ......................................................................... 136
ZT 8907 NEW FEATURES .......................................................................................................... 136
ZT 8907 MECHANICAL ISSUES................................................................................................. 136
ZT 8907 PROGRAMMING ISSUES ............................................................................................ 138
ZT 260 AND ZT 310 ENCLOSURES........................................................................................... 138
F. CUSTOMER SUPPORT....................................................................................................................... 139
TECHNICAL/SALES ASSISTANCE ............................................................................................ 139
RELIABILITY................................................................................................................................ 139
RETURNING FOR SERVICE ...................................................................................................... 139
ZIATECH WARRANTY ................................................................................................................ 140
TRADEMARKS ............................................................................................................................ 141

ÛZIATECH 6
MANUAL ORGANIZATION
This manual describes the operation and use of the ZT 8907 Single Board Computer
with IntelDX4™ Microprocessor. The following summarizes the focus of each major
section in this manual.
Chapter 1, "Introduction," introduces the key features of the ZT 8907. It includes a
product definition, a list of product features, a functional block diagram, and a
description of each block.
Chapter 2, "Getting Started," provides a summary of the information needed to install
and configure your ZT 8907.
Chapter 3, "STD Bus Interface," presents a detailed description of the ZT 8907
interface to the STD-80 and STD 32 bus architectures. The topics discussed include
compatibility, interrupt structure, and multiple master operation.
Chapter 4, "Interrupt Controller," describes the two Intel-compatible 8259 cascaded
interrupt controllers. This chapter summarizes the interrupt sources and the interrupt
controllers' register addressing.
Chapter 5, "Counter/Timers," discusses the six programmable counter/timers. It
includes a diagram of the counter/timer architecture, and a summary of the operating
modes and the programmable registers.
Chapter 6, "DMA Controller," provides an overview of ZT 8907 DMA architecture and
briefly describes the DMA controller programmable registers.
Chapter 7, "Real-Time Clock," lists the major features of the real-time clock and briefly
describes the real-time clock programmable registers.
Chapter 8, "Serial Controller," discusses operation of the two serial ports and briefly
describes the programmable registers.
Chapter 9, "Parallel Printer Port Interface," describes the different modes for the
Centronics-compatible printer interface. Address mapping, interrupt selection, and
programmable registers are also discussed.
Chapter 10, "Parallel I/O," discusses the general operation of the six parallel ports and
the functional blocks of the parallel I/O. It also provides register descriptions and
illustrations.
Chapter 11, "System Registers," provides register descriptions and illustrations as
well as a brief overview of the three System registers used to control and monitor a
variety of functions on the ZT 8907.

Manual Organization
ÛZIATECH 7
Chapter 12, "Watchdog Timer," explains operation of the watchdog timer and includes
code for arming and strobing the timer.
Chapter 13, "PCI Mezzanine Local Bus," introduces the features of the PCI bus
interface that allows the CPU high speed access to PCI mezzanine peripherals.
Chapter 14, "Programmable LED," provides code for turning the LED on and off.
Chapter 15, "AC Power-Fail," explains AC power-fail detection.
Chapter 16, "Memory Module Socket (U17)," explains the various functions of socket
U17 including the optional static RAM that can be used to hold critical system
information in the event of power loss.
Chapter 17, "Optional IDE Interface," provides details on the optional high speed local
IDE disk drive interface.
Chapter 18, "Optional Local Floppy Disk Interface," provides details on the optional
local floppy disk drive interface.
Appendix A, "Board Configuration," describes the jumpers and cuttable traces on the
ZT 8907. This appendix details factory default settings as well as information to tailor
your board to a specific application.
Appendix B, "Specifications," contains the electrical, environmental, and mechanical
specifications for the ZT 8907. This appendix also provides illustrations of cables and
connector locations, and tables showing connector pin assignments.
Appendix C, "Digital I/O ASIC System Setup Considerations," offers tips for system
configuration to prevent latchup conditions.
Appendix D, "PCI Configuration Space Map," presents the generic layout of the PCI
Configuration Header for all PCI compliant devices. It also contains a table showing the
PCI bus mapping of the ZT 8907's onboard devices.
Appendix E, "ZT 8907 Vs. ZT 8902: Technical Differences," describes the technical
differences between the ZT 8907 and the ZT 8902 single board computers. It includes
information to help existing ZT 8902 customers adapt their applications to the ZT 8907.
Appendix F, "Customer Support," offers technical assistance and warranty
information, and the necessary information should you need to return your ZT 8907 for
repair.

ÛZIATECH 8
1. INTRODUCTION
This chapter provides a brief introduction to the ZT 8907. It includes a product definition,
a list of product features, and descriptions of each of the ZT 8907's functional blocks.
Reference unpacking information and installation instructions are found in Chapter 2,
"Getting Started."
PRODUCT DEFINITION
ZT 8907
The ZT 8907 is a highly integrated, single board computer that is factory configured to
operate with a 100 MHz i486™ IntelDX4™ microprocessor. (Contact Ziatech for support
of other 486 microprocessor configurations). The board meets the needs of a wide
range of industrial control and processing applications by operating stand alone, as a
single master in an STD 32®architecture, or as a permanent or temporary master in an
STD 32 architecture.
ZT 89LT07
The ZT 89LT07, a low temperature version with an extended operating range for harsh
environments, is now available on a build-to-order basis. The ZT 8907 operating range
of 0º to +70º C is extended in the ZT 89LT07 to -40º +70º C. Contact Ziatech for details.
Stand-Alone Operation
The ZT 8907 does not require an STD bus backplane to operate. The ZT 8907 is able to
operate stand alone in many applications because of the large selection of the most
commonly needed peripheral devices. Peripheral devices include:
•Parallel I/O
•Counter/timers
•Real-time clock
•Watchdog timer
•Speaker interface
•Keyboard controller
•Interrupt controllers
•AC/DC power-fail detection
•Optional local PCI video support (VGA/Flat-Panel)
•Optional static RAM memory with battery backup

1. Introduction
ÛZIATECH 9
•Bi-directional multi-mode printer interface
•Optional local high speed IDE disk drive
•Serial I/O (two 16550 compatible ports)
•Optional local floppy drive interface
•Flash file system (up to 4 Mbytes)
•COM1/COM2 (16550 compatible)
STD-80 or STD 32 Single Master Architecture
The ZT 8907 supports additional memory and I/O through the STD bus. In an STD-80
architecture, all 16-bit data transfers are automatically reduced to 8-bit transfers for
complete backwards compatibility with STD-80 boards. In an STD 32 architecture, the
data transfers are dynamically adjusted to support 8-bit and 16-bit boards.
See Chapter 3, "STD Bus Interface," for a detailed description of the ZT 8907 interface
to the STD bus architecture.
STD 32 Multiple Master Architecture
The ZT 8907 can be configured to operate in a multiple master architecture as a
permanent master or a temporary master. With this architecture, up to seven ZT 8907
boards share STD bus memory and I/O resources.
See Chapter 3, "STD Bus Interface," for a detailed description of the ZT 8907 interface
to the STD bus architecture.
FEATURES
•STD 32 bus compatible
•Occupies single STD bus slot
•Single and multiple master operation
•25 to 100 MHz 486SX/DX4 operation
•Numeric coprocessor support (486DX4)
•8 Kbytes of CPU cache (16 Kbytes on DX4)
•4, 8, 16, or 32 Mbytes of DRAM memory (EDO)
•2 or 4 Mbytes of flash memory
•Optional 32-bit PCI bus video support
•Standard AT®peripherals include:

1. Introduction
ÛZIATECH 10
!–Two interrupt controllers (8259)
!–Three counter/timers (one 8254)
!–Real-time clock/CMOS RAM (146818 compatible)
!–Two DMA controllers (8237)
•Three additional user counter/timers (second 8254)
•24-point digital I/O (compatible with Opto 22 racks and Ziatech's ZT 2226 rack) with
event sense capability
•Bi-directional multi-mode printer interface (Centronics/Extended Mode)
•Two RS-232 serial ports
•Single stage watchdog timer
•Speaker interface
•Push-button reset
•Software programmable LED
•AC/DC power monitor
•Optional static RAM memory with battery backup
•Optional local high speed IDE disk drive (requires one extra slot)
•Optional local floppy drive interface (requires one extra slot, contact Ziatech)
•Compatible with MS-DOS®, QNX®, VxWorks®, Windows®3.1, Windows 95, and
other PC-compatible operating systems
•STD DOS and STAR BIOS options
•STD bus standard 4.5" x 6.5" board format
•+5 V only operation
•Five-year warranty
DEVELOPMENT CONSIDERATIONS
Ziatech offers DOS and STD 32 STAR SYSTEM™ software development systems for
ZT 8907 applications. DOS is Microsoft's MS-DOS residing on the ZT 8907. The DOS
system provides a development platform similar to a PC, enabling applications to be
developed quickly. DOS includes support for many of the ZT 8907's peripherals and is
supported by a large number of development tools such as program editors, compilers,
assemblers, and debuggers. Refer to the Ziatech Industrial BIOS for CompactPCI and
STD 32 Systems software manual on Ziatech's web site http://www.ziatech.com.

1. Introduction
ÛZIATECH 11
The STD 32 STAR SYSTEM is the DOS platform operating on more than one master in
a single STD bus system. Each master includes local memory, local I/O, and the DOS
operating system. Each master is capable of sharing STD bus memory and I/O, such as
fixed disks, floppy disks, and video. Refer to the STAR SYSTEM operating manual for
configuration and operating instructions.
Ziatech also offers software development kits for QNX®and VxWorks®operating
systems. Contact Ziatech for details or view Ziatech's web site at
http://www.ziatech.com/.
FUNCTIONAL BLOCKS
The Functional Block Diagram figure of the ZT 8907 is on the following page. The
blocks correspond to topics remaining in this chapter.
The following topics, not represented on the diagram, are also in this chapter:
•Keyboard Controller
•Speaker Interface
•Optional Floppy Disk Interface

1. Introduction
ÛZIATECH 12
Functional Block Diagram
®
ZT 8907
Counter/
Timer I/O
Interrupt
Inputs
Centronics
Port
24-Point
Parallel I/O Two 16C550
Serial Ports
AC/DC
Power Detect
25 to
100 MHz
486 CPU
8 KB
Cache/
16KB
Cache
(DX4)
Dynamic
RAM
(up to
32 Mbytes)
Flash
Memory
(up to
4 Mbytes)
PCI
Local Bus
Expansion
IDE
Subsystem
Counter/Timers
Watchdog
Timer
Interrupt
Controllers
Bus Interface
(Single and Multiple Master Operation)
DMA
Controllers
Battery-Backed
SRAM (128 Kbytes)
Battery
Real-Time
Clock
ZT8907
STD Bus Interface
In an STD 32 system, data transfers are dynamically sized for either 8 bits or 16 bits.
STD 32 compatible memory and I/O boards are dynamically sensed to determine the
width of the data transfer.
In addition to 16-bit data transfers, the STD 32 system provides the platform needed for
multiple master operation. In a multiple master system, up to seven ZT 8907 boards
share STD bus resources with a fixed or rotating priority granted by an external bus
arbiter, such as the ZT 89CT39. If used, the ZT 89CT39 must be Revision D or higher.
See Chapter 3, "STD Bus Interface," for a detailed description of the ZT 8907 interface
to the STD bus architecture.

1. Introduction
ÛZIATECH 13
486SX/DX4 Processors
The ZT 8907 supports the 486SX-25, 486SX-33, and 486DX4-100 processors. The
processors differ in operating speeds and hardware support of floating point operations,
as shown in the following table.
Processor Operating Speed Supports Floating
Point Operations
486SX-25 25 MHz No
486SX-33 33 MHz No
486DX4-100 33 MHz external, 100 MHz internal Yes
Note: The 486DX4-100 is a 3.3 V processor. This reduces the energy needed by the
CPU as well as the waste heat generated during operation. The ZT 8907 is equipped
with a highly efficient 3.3 V power source for the CPU and the DRAM memory.
Memory and I/O Addressing
The ZT 8907 includes two 72-pin SO-DIMM sockets that support up to 32 Mbytes of
EDO DRAM. The ZT 8907 also supports flash memory soldered directly on the board.
Memory operations up to 32 Mbytes that are not decoded by local memory devices are
directed to the STD bus. Data transfers are dynamically adjusted to support standard
architecture boards with an 8-bit or 16-bit data path.
The ZT 8907 also includes many I/O peripherals required for industrial control
applications. I/O operations not decoded by local I/O devices are directed to the
STD bus. The STD bus I/O expansion signal, IOEXP, is supported to limit the
addressing redundancy of I/O boards decoding fewer than 16 bits of address. Data
transfers are dynamically adjusted to support standard architecture boards with an 8-bit
or 16-bit data path.
PCI Bus Video
The ZT 8907 supports both STD bus and local PCI bus video adapters. For STD bus
video, Ziatech offers video boards that support VGA and flat panel displays. For local
bus video, Ziatech offers zPM adapters that plug directly onto the ZT 8907's PCI
mezzanine local bus interface connector (J13).
PCI bus video is up to 700% faster than STD bus video because the data transfers
occur at CPU speed (up to 33 MHz) and bus width (up to 32 bits). For space-
constrained applications, use of zPM adapters has the advantage of not requiring the
additional card cage slot that STD bus video boards would need. Refer to Chapter 13,
"PCI Mezzanine Local Bus," for more information.

1. Introduction
ÛZIATECH 14
Serial I/O
The ZT 8907 includes two PC-compatible serial ports. The serial ports are implemented
with a 5 V charge pump technology to eliminate the need for a ±12 V supply. Both serial
ports include a complete set of handshaking and modem control signals, maskable
interrupt generation, and data transfer rates up to 115.2 Kbaud.
The serial ports are configured as DTE and are available through 10-pin frontplane
connectors (J3 COM2 and J4 COM1). Optional cables interface the frontplane
connectors to standard 9-pin D-shell connectors (male). For more on the operation of
the two serial ports, see Chapter 8, "Serial Controller."
Parallel I/O
The ZT 8907 includes three 8-bit parallel I/O ports for a total of 24 parallel I/O lines.
Each line is programmable as an input or an output with readback. All three ports
include event sense capability where a positive or negative transition on the input will
generate an onboard interrupt.
All inputs also feature a programmable debounce circuit. The outputs sink 12 mA and
do not glitch during power up or power down. The 24 lines are available through a 50-
pin frontplane connector (J5). Optional cables interface the frontplane connector to
an 8-, 16-, or 24-position I/O module mounting rack, such as Ziatech's ZT 2226 24-
Channel I/O Mounting Rack or those offered by Opto 22. See Chapter 10, "Parallel I/O,"
for more information.
Interrupts
The ZT 8907's two interrupt controllers provide a total of 15 interrupt inputs. Interrupt
controller features include support for level-triggered and edge-triggered inputs, fixed
and rotating priorities, and individual input masking.
Interrupt sources include counter/timers, serial I/O, real-time clock, keyboard, printer,
hard disk, floppy disk and multiple master communications. There are also five
frontplane and five backplane interrupt sources. See Chapter 4, "Interrupt Controller,"
for more information.
Counter/Timers
Six counter/timers are included on the ZT 8907. Operating modes supported by the
counter/timers include interrupt on count, frequency divider, square wave generator,
software triggered, hardware triggered, and one shot.
Three of the counter/timers are dedicated to supporting local devices. Three additional
counter/timers are available through a 10-pin frontplane connector (J2). See Chapter 5,
"Counter/Timers," for more information.

1. Introduction
ÛZIATECH 15
DMA
The ZT 8907's two DMA controllers provide a total of four DMA channels for data
transfers between STD bus I/O and local memory. The DMA channels support STD bus
DMA slaves by managing the data transfers between the slaves and local memory.
Additional features of the DMA channels include auto initialization, address increment or
decrement, and software DMA requests.
DMA channel 2, is an 8-bit channel available on the backplane through STD bus
BUSRQ* and BUSAK*. Channel 2 is primarily used for floppy disk expansion. Three
additional DMA channels are available through a 10-pin frontplane connector (J6).
Each of the three frontplane DMA channels can be independently configured for 8-bit or
16-bit operation. These are designated as DMA0/5, DMA1/6 and DMA 3/7. DMA
channels 0, 1 and 3 are 8-bit channels. DMA channels 5, 6 and 7 are 16-bit DMA
channels. See Chapter 6, "DMA Controller," for more information.
Watchdog Timer
The watchdog timer optionally monitors system operation. If the watchdog timer is
enabled it must be strobed at least every 500 ms. Failure to strobe the watchdog timer
within this time period will result in a system reset. See Chapter 12, "Watchdog Timer,"
for more information.
Real-Time Clock
The real-time clock performs timekeeping functions and includes 128 bytes of battery-
backed CMOS RAM. Timekeeping features include an alarm function, a maskable
periodic interrupt, and a 100-year calendar. See Chapter 7, "Real-Time Clock," and
Chapter 16, "Memory Module Socket (U17)," for more information.
Keyboard Controller
The ZT 8907 includes a PC/AT®keyboard controller that operates when a zPM PCI bus
video adapter is installed (in connectors J11 and J13). The keyboard and VGA video
signals are available at connector J7. An optional cable is available through Ziatech.
Parallel Printer Port Interface
The ZT 8907 includes a PC/AT printer interface for connection to a Centronics™-
compatible printer. The printer interface is available through a 20-pin frontplane
connector (J9). An optional cable is available from Ziatech to interface the frontplane
connector to a standard 25-pin female D connector. For more information, see
Chapter 9, "Parallel Port Printer Interface."

1. Introduction
ÛZIATECH 16
Speaker Interface
The ZT 8907 supports an external speaker through a 2-pin frontplane connector (J8).
AC Power-Fail Protection
With the addition of an AC transformer, the ZT 8907 monitors AC power to permit an
orderly shutdown during a power failure. When AC power falls below an acceptable
operating range, a non-maskable interrupt is generated to notify the CPU of an
impending power failure. When the application software receives this notification, it
saves critical data before the CPU is reset.
Connection to the low voltage AC (24 V nom.) is provided through a 2-pin frontplane
connector (J10). See Chapter 15, "AC Power-Fail," for more information.
Optional Hard Disk Interface
The ZT 8907 supports an optional local IDE hard disk interface. The interface does not
depend on the STD bus, permitting the ZT 8907 to boot from a localized operating
system. This feature is especially useful in multiprocessing applications that require
more than one operating system. See Chapter 17, "Optional IDE Interface," for more
information.
Optional Floppy Disk Interface
An optional floppy disk interface is also available on the front of the board. This is
designed for higher volume applications requiring a single board solution without a card
cage. For all other applications, a ZT 8954 Low Profile Floppy Disk Controller provides a
more modular solution. See Chapter 18, "Optional Local Floppy Disk Interface," for
more information.

ÛZIATECH 17
2. GETTING STARTED
This chapter summarizes the information needed to make the ZT 8907 operational.
Please read this chapter before attempting to use the board.
UNPACKING
Please check the shipping carton for damage. If the shipping carton and contents are
damaged, notify the carrier and Ziatech for an insurance settlement. Retain the shipping
carton and packing material for inspection by the carrier. Save the anti-static bag for
storing or returning the ZT 8907.
Do not return any product to Ziatech without a Return Material Authorization (RMA)
number. "Customer Support," Appendix F, explains the procedure for obtaining an RMA
number from Ziatech.
Warning: Like all equipment utilizing MOS devices, the boards must
be protected from static discharge. Never remove any of the
socketed parts except at a static-free workstation. Use the anti-static
bag shipped with the ZT 8907 to handle the boards.
SYSTEM REQUIREMENTS
The ZT 8907 is designed for use with or without an STD bus backplane. The ZT 8907 is
electrically, mechanically, and functionally compatible with both the STD 32 Bus
Specification (ZT MSTD32) for STD bus applications. An STD 32 system is required for
16-bit data transfers to other STD bus boards and for multiple master operation.
Note: If installing the ZT 8907 in an STD 32 card cage with the ZT 8920 32-Bit Memory
System, the ZT 8920 should be installed as close to the end as possible. In backplanes
with 20 or more slots, install it in slot 17 or higher. Refer to Ziatech's ZT 8920 32-Bit
Memory System hardware manual for further information. This online manual is in
Adobe Acrobat format. To view this file, you need Acrobat Reader, which can be
downloaded from the web site http://www.adobe.com.
Ziatech recommends vertical mounting and the use of a fan to meet the airflow
requirements shown in the "Airflow Requirements" figure below. Refer to Appendix B,
"Specifications," for additional specifications.

2. Getting Started
ÛZIATECH 18
Airflow Requirements
15 25 35 45 55 65 75 80
Convection
100
200
300
400
500
(ft/min)
DX (33)
SX (25)
DX2(66)
Ambient Air Temp ( C)
H
E
A
T
S
I
N
K
A
I
R
V
E
L
O
C
I
T
Y
DX (33)
DX2(50)
Industrial
DX4(100)
ZT8907F02-01
MEMORY CONFIGURATION
The ZT 8907 can address up to 128 Mbytes of memory. The address space is divided
between memory local to the board and memory on the STD bus. Any memory not
reserved or occupied by a local memory device is available for STD bus expansion.
During local memory operations, the STD bus is held static to decrease system
electrical noise and power consumption.
STD bus memory is transferred at a rate of up to 1 Mbyte/second for 8-bit data and
2 Mbytes/second for 16-bit data. The ZT 8907 supports the STD bus wait request
signal, WAITRQ*, to interface to memory boards with longer access time requirements
than those defined by the STD 32 specifications.
The ZT 8907 is populated with several memory devices. Local DRAM plugs into one or
two 72-pin SO-DIMM (small outline-dual inline memory module) sockets. Each SO-
DIMM socket supports 4, 8, or 16 Mbytes of DRAM for a total of 32 Mbytes onboard.
Local flash memory is soldered directly to the board.
There is space for one or two 2 Mbyte flash devices for a total of 4 Mbytes onboard. A
socket is provided for an optional static RAM device (128 Kbytes) that may be battery
backed. For more information, see Chapter 16, "Memory Module Socket (U17)". The
memory address map is shown in the "Memory Address Map" illustration below.

2. Getting Started
ÛZIATECH 19
Memory Address Map
Flash #1
Local (2Mbyte)
Reserved
Local DRAM
or STD
Local DRAM
BIOS Shadow
PCI or SRAM or STD
PCI or STD
PCI
Memory
STD
Local DRAM
or STD
PCI or STD
PCI or STD
PCI or STD
Local DRAM
FFFF FFFFh
FFC0 0000h
0800 0000h
0200 0000h
0100 0000h
0080 0000h
0010 0000h
000E 0000h
000D 8000h
F800 0000h
FFE0 0000h
000D 0000h
000C 8000h
000C 0000h
000A 0000h
Flash #2
Local (2Mbyte)
(4Gbyte)
(4Gbyte-128Mbyte)
(32Mbyte)
(16Mbyte)
(8Mbyte)
(1Mbyte)
(896Kbyte)
(864Kbyte)
(832Kbyte)
(128Mbyte)
(4Gbyte-2Mbyte)
(800Kbyte)
(768Kbyte)
(640Kbyte)
0
(4Gbyte-4Mbyte)
ZT8907
I/O CONFIGURATION
The ZT 8907 addresses up to 64 Kbytes of I/O using a 16-bit I/O address. The address
space is divided between I/O local to the board and I/O on the STD bus. Any I/O space
not reserved or occupied by a local I/O device is available for STD bus expansion.
During local I/O operations, the STD bus is held static to decrease system electrical
noise and power consumption.
Local and STD bus I/O data is transferred at a rate of up to 1 Mbyte/second for 8-bit
data and 2 Mbytes/second for 16-bit data. The ZT 8907 supports the STD bus wait
request signal, WAITRQ*, to interface to I/O boards with longer access time
requirements than those defined by the STD 32 specifications. The STD bus I/O