Ziatech Corporation ZT 89CT04 Instructions for use

ZT 89CT04
Single Board 386 EX Computer
ZT 8904
ZT 8903
Hardware User Manual

 2
CONTENTS
MANUAL ORGANIZATION.....................................................................................................................6
1. INTRODUCTION .................................................................................................................................8
PRODUCT DEFINITION .............................................................................................................8
ZT 8904..........................................................................................................................9
ZT 89CT04.....................................................................................................................9
ZT 8903..........................................................................................................................9
STAND ALONE..............................................................................................................9
STD 32 SINGLE MASTER..............................................................................................9
STD 32 MULTIPLE MASTER..........................................................................................9
FEATURES...............................................................................................................................10
DEVELOPMENT CONSIDERATIONS.......................................................................................11
FUNCTIONAL BLOCKS............................................................................................................11
STD BUS INTERFACE.................................................................................................11
386 EX CPU.................................................................................................................12
MEMORY AND I/O ADDRESSING ...............................................................................13
LOCAL BUS VIDEO......................................................................................................13
SERIAL I/O...................................................................................................................13
IEEE 1284 PARALLEL PORT.......................................................................................14
PARALLEL I/O..............................................................................................................14
INTERRUPTS...............................................................................................................14
TIMERS........................................................................................................................15
DMA.............................................................................................................................15
WATCHDOG TIMER ....................................................................................................15
REAL-TIME CLOCK .....................................................................................................15
KEYBOARD CONTROLLER.........................................................................................16
AC POWER-FAIL PROTECTION..................................................................................16
2. GETTING STARTED.........................................................................................................................17
UNPACKING.............................................................................................................................17
SYSTEM REQUIREMENTS......................................................................................................17
MEMORY CONFIGURATION....................................................................................................17
SYSTEM RAM - 16-BIT PSEUDO STATIC RAM...........................................................17
I/O CONFIGURATION...............................................................................................................19
CONNECTOR CONFIGURATION.............................................................................................20
JUMPER DESCRIPTIONS........................................................................................................21
SETUP......................................................................................................................................21
SYSTEM CONFIGURATION OVERVIEW.....................................................................21
3. STD BUS INTERFACE......................................................................................................................23
STD 32 OPERATION................................................................................................................23
STD 32 OPERATION....................................................................................................23
STD 32 BUS COMPATIBILITY..................................................................................................24
COMPLIANCE LEVELS................................................................................................24
STD BUS INTERRUPTS...........................................................................................................24
MASKABLE INTERRUPTS...........................................................................................25
NON-MASKABLE INTERRUPTS..................................................................................26
RESET......................................................................................................................................27
MULTIPLE MASTER AND INTELLIGENT I/O............................................................................27
MULTIPLE MASTER ....................................................................................................27
INTELLIGENT I/O.........................................................................................................28
SYSTEM REQUIREMENTS..........................................................................................29
MULTIPLE MASTER RESET........................................................................................30

Contents
 3
4. INTERRUPT CONTROLLER.............................................................................................................31
PROGRAMMABLE REGISTERS...............................................................................................31
INTERRUPT ARCHITECTURE INITIALIZATION REGISTERS (ICW1-ICW4)................34
OPERATIONAL REGISTERS (OCW1-OCW3)..............................................................36
STATUS REGISTERS (IRR, ISR, IPR) .........................................................................37
ADDITIONAL INFORMATION...................................................................................................38
5. COUNTER/TIMERS...........................................................................................................................39
PROGRAMMABLE REGISTERS...............................................................................................41
COUNT REGISTERS AND COUNT LATCH .................................................................41
STATUS REGISTER ....................................................................................................42
CONTROL REGISTER.................................................................................................43
ADDITIONAL INFORMATION...................................................................................................44
6. DMA CONTROLLER.........................................................................................................................45
INTEL 386 EX INTERNAL ARCHITECTURE.............................................................................45
DMA IMPLEMENTATION..........................................................................................................47
DMA TRANSFER CYCLES...........................................................................................48
I/O MAPPING...............................................................................................................48
DMA CONTROLLER OPERATION ...........................................................................................48
PROGRAMMING A DMA CHANNEL............................................................................49
FLY-BY AND TWO-CYCLE BUS CYCLES....................................................................49
386 EX DMA CONTROLLER REGISTERS ...............................................................................50
PIN MUX CONFIGURATION........................................................................................51
PERIPHERAL CONNECTIONS AND MASK.................................................................53
CHANNEL 0 REQUESTOR ADDRESS REGISTERS....................................................53
CHANNEL 1 REQUESTOR ADDRESS REGISTERS....................................................55
CHANNEL 0 TARGET ADDRESS REGISTERS ...........................................................56
CHANNEL 1 TARGET ADDRESS REGISTERS ...........................................................58
CHANNEL 0 BYTE COUNT REGISTERS.....................................................................59
CHANNEL 1 BYTE COUNT REGISTERS.....................................................................61
DMA STATUS REGISTER............................................................................................62
DMA COMMAND REGISTERS.....................................................................................63
DMA MODE REGISTERS.............................................................................................64
DMA SOFTWARE REQUEST REGISTER....................................................................65
DMA SINGLE CHANNEL MASK REGISTER................................................................66
DMA GROUP CHANNEL MASK...................................................................................66
DMA BUS SIZE REGISTER..........................................................................................66
DMA CHAINING REGISTER ........................................................................................67
DMA INTERRUPT ENABLE REGISTER.......................................................................68
DMA INTERRUPT STATUS REGISTER.......................................................................68
DMA OVERFLOW ENABLE REGISTER.......................................................................69
7. REAL-TIME CLOCK..........................................................................................................................70
PROGRAMMABLE REGISTERS...............................................................................................70
REGISTER A................................................................................................................72
REGISTER B................................................................................................................73
REGISTER C................................................................................................................73
REGISTER D................................................................................................................74
ADDITIONAL INFORMATION...................................................................................................74
8. SERIAL CONTROLLER....................................................................................................................75
ZT 8904 SPECIFICS.................................................................................................................75
ADDRESS MAPPING...................................................................................................76
INTERRUPT SELECTION ............................................................................................76
HANDSHAKE SIGNALS...............................................................................................76
RS-485 OPERATION....................................................................................................77
SERIAL CHANNEL INTERFACE..................................................................................77

Contents
 4
PROGRAMMABLE REGISTERS...............................................................................................78
BAUD RATE DIVISORS ...............................................................................................78
DIVISOR LATCH LSB AND MSB..................................................................................79
INTERRUPT CONTROL REGISTER ............................................................................80
INTERRUPT STATUS REGISTER................................................................................81
LINE CONTROL REGISTER ........................................................................................82
LINE STATUS REGISTER............................................................................................83
MODEM CONTROL REGISTER...................................................................................83
MODEM STATUS REGISTER......................................................................................84
ADDITIONAL INFORMATION...................................................................................................84
9. CENTRONICS PRINTER INTERFACE..............................................................................................85
PROGRAMMABLE REGISTERS...............................................................................................85
LINE PRINTER DATA REGISTER................................................................................85
LINE PRINTER STATUS REGISTER............................................................................85
LINE PRINTER CONTROL REGISTER........................................................................86
ADDITIONAL INFORMATION...................................................................................................86
10. PARALLEL I/O................................................................................................................................87
FUNCTIONAL DESCRIPTION ..................................................................................................87
OUTPUT LATCH..........................................................................................................88
OUTPUT BUFFER........................................................................................................88
INPUT BUFFER............................................................................................................89
PROGRAMMABLE REGISTERS...............................................................................................89
16C50A STANDARD OPERATING MODE ...................................................................89
16C50A ENHANCED OPERATING MODE...................................................................90
11. SYSTEM REGISTERS.....................................................................................................................96
PROGRAMMABLE REGISTERS...............................................................................................96
ADDITIONAL INFORMATION...................................................................................................98
12. WATCHDOG TIMER .......................................................................................................................99
WATCHDOG TIMER OPERATION ...........................................................................................99
PROGRAMMABLE REGISTERS.............................................................................................100
WATCHDOG TIMER CLEAR REGISTER...................................................................101
WATCHDOG TIMER STATUS REGISTER.................................................................101
WATCHDOG TIMER COUNTER REGISTERS...........................................................102
WATCHDOG TIMER RELOAD REGISTERS..............................................................103
ADDITIONAL INFORMATION.................................................................................................103
13. LOCAL BUS VIDEO......................................................................................................................104
14. NUMERIC DATA PROCESSOR....................................................................................................105
15. PROGRAMMABLE LED................................................................................................................106
16. AC POWER FAIL ..........................................................................................................................108
A. JUMPER CONFIGURATIONS ........................................................................................................109
JUMPER OPTIONS ................................................................................................................109
JUMPER DESCRIPTIONS..........................................................................................111
B. SPECIFICATIONS..........................................................................................................................116
ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS.....................................................116
ABSOLUTE MAXIMUM RATINGS..............................................................................116
DC OPERATING CHARACTERISTICS.......................................................................116
BATTERY BACKUP CHARACTERISTICS..................................................................117
STD BUS LOADING CHARACTERISTICS .................................................................117
MECHANICAL SPECIFICATIONS...........................................................................................120
CARD DIMENSIONS AND WEIGHT...........................................................................120
CONNECTORS..........................................................................................................121

Contents
 5
CONNECTOR DESCRIPTIONS .................................................................................123
CABLES.....................................................................................................................133
C. PIA SYSTEM SETUP CONSIDERATIONS .....................................................................................139
PREVENTING SYSTEM LATCHUP ........................................................................................139
POWER SUPPLY SEQUENCE MISMATCH...............................................................140
SIGNAL LEVEL MISMATCH.......................................................................................142
PROTECTING CMOS INPUTS ...............................................................................................143
RISE TIMES...............................................................................................................143
INDUCTIVE COUPLING.............................................................................................144
ADDITIONAL INFORMATION.................................................................................................145
D. CUSTOMER SUPPORT..................................................................................................................146
TECHNICAL/SALES ASSISTANCE.........................................................................................146
RELIABILITY...........................................................................................................................146
RETURNING FOR SERVICE..................................................................................................146
ZIATECH WARRANTY............................................................................................................147
TRADEMARKS.......................................................................................................................148