Ziatech Corporation ZT 89CT04 Instructions for use

ZT 89CT04
Single Board 386 EX Computer
ZT 8904
ZT 8903
Hardware User Manual

 2
CONTENTS
MANUAL ORGANIZATION.....................................................................................................................6
1. INTRODUCTION .................................................................................................................................8
PRODUCT DEFINITION .............................................................................................................8
ZT 8904..........................................................................................................................9
ZT 89CT04.....................................................................................................................9
ZT 8903..........................................................................................................................9
STAND ALONE..............................................................................................................9
STD 32 SINGLE MASTER..............................................................................................9
STD 32 MULTIPLE MASTER..........................................................................................9
FEATURES...............................................................................................................................10
DEVELOPMENT CONSIDERATIONS.......................................................................................11
FUNCTIONAL BLOCKS............................................................................................................11
STD BUS INTERFACE.................................................................................................11
386 EX CPU.................................................................................................................12
MEMORY AND I/O ADDRESSING ...............................................................................13
LOCAL BUS VIDEO......................................................................................................13
SERIAL I/O...................................................................................................................13
IEEE 1284 PARALLEL PORT.......................................................................................14
PARALLEL I/O..............................................................................................................14
INTERRUPTS...............................................................................................................14
TIMERS........................................................................................................................15
DMA.............................................................................................................................15
WATCHDOG TIMER ....................................................................................................15
REAL-TIME CLOCK .....................................................................................................15
KEYBOARD CONTROLLER.........................................................................................16
AC POWER-FAIL PROTECTION..................................................................................16
2. GETTING STARTED.........................................................................................................................17
UNPACKING.............................................................................................................................17
SYSTEM REQUIREMENTS......................................................................................................17
MEMORY CONFIGURATION....................................................................................................17
SYSTEM RAM - 16-BIT PSEUDO STATIC RAM...........................................................17
I/O CONFIGURATION...............................................................................................................19
CONNECTOR CONFIGURATION.............................................................................................20
JUMPER DESCRIPTIONS........................................................................................................21
SETUP......................................................................................................................................21
SYSTEM CONFIGURATION OVERVIEW.....................................................................21
3. STD BUS INTERFACE......................................................................................................................23
STD 32 OPERATION................................................................................................................23
STD 32 OPERATION....................................................................................................23
STD 32 BUS COMPATIBILITY..................................................................................................24
COMPLIANCE LEVELS................................................................................................24
STD BUS INTERRUPTS...........................................................................................................24
MASKABLE INTERRUPTS...........................................................................................25
NON-MASKABLE INTERRUPTS..................................................................................26
RESET......................................................................................................................................27
MULTIPLE MASTER AND INTELLIGENT I/O............................................................................27
MULTIPLE MASTER ....................................................................................................27
INTELLIGENT I/O.........................................................................................................28
SYSTEM REQUIREMENTS..........................................................................................29
MULTIPLE MASTER RESET........................................................................................30

Contents
 3
4. INTERRUPT CONTROLLER.............................................................................................................31
PROGRAMMABLE REGISTERS...............................................................................................31
INTERRUPT ARCHITECTURE INITIALIZATION REGISTERS (ICW1-ICW4)................34
OPERATIONAL REGISTERS (OCW1-OCW3)..............................................................36
STATUS REGISTERS (IRR, ISR, IPR) .........................................................................37
ADDITIONAL INFORMATION...................................................................................................38
5. COUNTER/TIMERS...........................................................................................................................39
PROGRAMMABLE REGISTERS...............................................................................................41
COUNT REGISTERS AND COUNT LATCH .................................................................41
STATUS REGISTER ....................................................................................................42
CONTROL REGISTER.................................................................................................43
ADDITIONAL INFORMATION...................................................................................................44
6. DMA CONTROLLER.........................................................................................................................45
INTEL 386 EX INTERNAL ARCHITECTURE.............................................................................45
DMA IMPLEMENTATION..........................................................................................................47
DMA TRANSFER CYCLES...........................................................................................48
I/O MAPPING...............................................................................................................48
DMA CONTROLLER OPERATION ...........................................................................................48
PROGRAMMING A DMA CHANNEL............................................................................49
FLY-BY AND TWO-CYCLE BUS CYCLES....................................................................49
386 EX DMA CONTROLLER REGISTERS ...............................................................................50
PIN MUX CONFIGURATION........................................................................................51
PERIPHERAL CONNECTIONS AND MASK.................................................................53
CHANNEL 0 REQUESTOR ADDRESS REGISTERS....................................................53
CHANNEL 1 REQUESTOR ADDRESS REGISTERS....................................................55
CHANNEL 0 TARGET ADDRESS REGISTERS ...........................................................56
CHANNEL 1 TARGET ADDRESS REGISTERS ...........................................................58
CHANNEL 0 BYTE COUNT REGISTERS.....................................................................59
CHANNEL 1 BYTE COUNT REGISTERS.....................................................................61
DMA STATUS REGISTER............................................................................................62
DMA COMMAND REGISTERS.....................................................................................63
DMA MODE REGISTERS.............................................................................................64
DMA SOFTWARE REQUEST REGISTER....................................................................65
DMA SINGLE CHANNEL MASK REGISTER................................................................66
DMA GROUP CHANNEL MASK...................................................................................66
DMA BUS SIZE REGISTER..........................................................................................66
DMA CHAINING REGISTER ........................................................................................67
DMA INTERRUPT ENABLE REGISTER.......................................................................68
DMA INTERRUPT STATUS REGISTER.......................................................................68
DMA OVERFLOW ENABLE REGISTER.......................................................................69
7. REAL-TIME CLOCK..........................................................................................................................70
PROGRAMMABLE REGISTERS...............................................................................................70
REGISTER A................................................................................................................72
REGISTER B................................................................................................................73
REGISTER C................................................................................................................73
REGISTER D................................................................................................................74
ADDITIONAL INFORMATION...................................................................................................74
8. SERIAL CONTROLLER....................................................................................................................75
ZT 8904 SPECIFICS.................................................................................................................75
ADDRESS MAPPING...................................................................................................76
INTERRUPT SELECTION ............................................................................................76
HANDSHAKE SIGNALS...............................................................................................76
RS-485 OPERATION....................................................................................................77
SERIAL CHANNEL INTERFACE..................................................................................77

Contents
 4
PROGRAMMABLE REGISTERS...............................................................................................78
BAUD RATE DIVISORS ...............................................................................................78
DIVISOR LATCH LSB AND MSB..................................................................................79
INTERRUPT CONTROL REGISTER ............................................................................80
INTERRUPT STATUS REGISTER................................................................................81
LINE CONTROL REGISTER ........................................................................................82
LINE STATUS REGISTER............................................................................................83
MODEM CONTROL REGISTER...................................................................................83
MODEM STATUS REGISTER......................................................................................84
ADDITIONAL INFORMATION...................................................................................................84
9. CENTRONICS PRINTER INTERFACE..............................................................................................85
PROGRAMMABLE REGISTERS...............................................................................................85
LINE PRINTER DATA REGISTER................................................................................85
LINE PRINTER STATUS REGISTER............................................................................85
LINE PRINTER CONTROL REGISTER........................................................................86
ADDITIONAL INFORMATION...................................................................................................86
10. PARALLEL I/O................................................................................................................................87
FUNCTIONAL DESCRIPTION ..................................................................................................87
OUTPUT LATCH..........................................................................................................88
OUTPUT BUFFER........................................................................................................88
INPUT BUFFER............................................................................................................89
PROGRAMMABLE REGISTERS...............................................................................................89
16C50A STANDARD OPERATING MODE ...................................................................89
16C50A ENHANCED OPERATING MODE...................................................................90
11. SYSTEM REGISTERS.....................................................................................................................96
PROGRAMMABLE REGISTERS...............................................................................................96
ADDITIONAL INFORMATION...................................................................................................98
12. WATCHDOG TIMER .......................................................................................................................99
WATCHDOG TIMER OPERATION ...........................................................................................99
PROGRAMMABLE REGISTERS.............................................................................................100
WATCHDOG TIMER CLEAR REGISTER...................................................................101
WATCHDOG TIMER STATUS REGISTER.................................................................101
WATCHDOG TIMER COUNTER REGISTERS...........................................................102
WATCHDOG TIMER RELOAD REGISTERS..............................................................103
ADDITIONAL INFORMATION.................................................................................................103
13. LOCAL BUS VIDEO......................................................................................................................104
14. NUMERIC DATA PROCESSOR....................................................................................................105
15. PROGRAMMABLE LED................................................................................................................106
16. AC POWER FAIL ..........................................................................................................................108
A. JUMPER CONFIGURATIONS ........................................................................................................109
JUMPER OPTIONS ................................................................................................................109
JUMPER DESCRIPTIONS..........................................................................................111
B. SPECIFICATIONS..........................................................................................................................116
ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS.....................................................116
ABSOLUTE MAXIMUM RATINGS..............................................................................116
DC OPERATING CHARACTERISTICS.......................................................................116
BATTERY BACKUP CHARACTERISTICS..................................................................117
STD BUS LOADING CHARACTERISTICS .................................................................117
MECHANICAL SPECIFICATIONS...........................................................................................120
CARD DIMENSIONS AND WEIGHT...........................................................................120
CONNECTORS..........................................................................................................121

Contents
 5
CONNECTOR DESCRIPTIONS .................................................................................123
CABLES.....................................................................................................................133
C. PIA SYSTEM SETUP CONSIDERATIONS .....................................................................................139
PREVENTING SYSTEM LATCHUP ........................................................................................139
POWER SUPPLY SEQUENCE MISMATCH...............................................................140
SIGNAL LEVEL MISMATCH.......................................................................................142
PROTECTING CMOS INPUTS ...............................................................................................143
RISE TIMES...............................................................................................................143
INDUCTIVE COUPLING.............................................................................................144
ADDITIONAL INFORMATION.................................................................................................145
D. CUSTOMER SUPPORT..................................................................................................................146
TECHNICAL/SALES ASSISTANCE.........................................................................................146
RELIABILITY...........................................................................................................................146
RETURNING FOR SERVICE..................................................................................................146
ZIATECH WARRANTY............................................................................................................147
TRADEMARKS.......................................................................................................................148

 6
MANUAL ORGANIZATION
The ZT 8904 family of products includes the ZT 8904, ZT 89CT04, and ZT 8903
products. The ZT 8904 is a highly integrated 386 EX single board computer which can
be operated as a stand alone, as a single master in an STD 32 architecture, or as a
permanent or temporary master in an STD 32 architecture.
All features of the ZT 8903 and ZT 8904 are the same, except that the ZT 8903 includes
fewer features. The ZT 8903 is a more economical version of the ZT 8904 because of
fewer features are included.
All features of the ZT 8904 and ZT 89CT04 are the same except for the temperature
variations. The ZT 8904 has an operating temperature range from 0º to 65º C, but the
ZT 89CT04 extends the operating temperature range from -40º to +85º C.
Chapter 1, "Introduction", provides a brief introduction to the ZT 8904. It includes a
product definition, a list of product features, a functional block diagram, a description of
each block, and a diagram locating the major components of the board.
Chapter 2, "Getting Started", summarizes the information needed to make the
ZT 8904 operational. Read this chapter before attempting to use the board.
Chapter 3, "STD Bus Interface", discusses the STD 32 architecture and its effect on
the operation of the ZT 8904.
Chapter 4, "Interrupt Controller", includes information on two Intel-compatible 8259
cascaded interrupt controllers that provide a programmable interface between interrupt-
generating peripherals and the CPU.
Chapter 5, "Counter/Timers", includes information on one Intel-compatible 8254
device with a total of three programmable counter/timers.
Chapter 6, "DMA Controller", includes information regarding the DMA controller which
is contained within the 386 EX microprocessor.
Chapter 7, "Real-Time Clock", includes information on the Motorola®-compatible
146818 real-time clock including the major features.
Chapter 8, "Serial Controller", discusses operation of the four ZT 8904 serial ports and
provides descriptions of the two software-configurable serial port registers included on
the ZT 8904.
Chapter 9, "Centronics Printer Interface", includes information on the bidirectional
printer interface which fully supports a Centronics-compatible printer.
Chapter 10, "Parallel I/O", discusses the six 8-bit parallel ports for a total of 48 I/O
signals. The general operation of the six parallel ports is explained in this chapter.

Manual Organization
 7
Chapter 11, "System Registers", discusses the three system registers used to control
and monitor a variety of functions on the ZT 8904.
Chapter 12, "Watchdog Timer", lists the major features of the watchdog timer which
monitors the ZT 8904 operation and takes corrective action if the system fails to function
as programmed.
Chapter 13, "Local BUS Video", includes information on the local bus interface which
permits high speed peripherals direct access to the CPU bus.
Chapter 14, "Numeric Data Processor", discusses how the numeric data processor
extends the CPU instruction set to include trigonometric, logarithmic, and exponential
functions.
Chapter 15, "Programmable LED", discusses the ZT 8904's two Light-Emitting Diodes
(LEDs).
Chapter 16, "AC Power Fail", includes information on the AC power-fail detection as a
means for giving the application advanced warning of an impending power failure.
Appendix A, "Jumper Configurations", demonstrations how the ZT 8904 offers
several options tailoring the operation of the board to requirements of specific
applications. The "Jumper Cross Reference" table is included.
Appendix B, "Specifications", describes the electrical, environmental, and mechanical
specifications of the ZT 8904. It includes illustrations of the board dimensions, the P/E
connector pinouts, and cables commonly used with the ZT 8904. Also shown are tables
listing the pin assignments for the ZT 8904's 10 connectors.
Appendix C, "PIA System Setup Considerations", discusses the 16C50A Parallel
Interface Adapter (PIA) device used on the ZT 8904. It is designed by Ziatech to offer
bidirectional I/O signals with or without event sense capability.
Appendix D, "Customer Support", offers technical assistance information for this
product, and also the necessary information should you need to return a Ziatech
product.

 8
1. INTRODUCTION
This chapter provides a brief introduction to the ZT 8904. It includes a product definition,
a list of product features, a functional block diagram, a description of each block, and a
diagram locating the major components of the board. Unpacking information and
installation instructions are included in Chapter 2, "Getting Started."
Math Coprocessor
Option
Intel
386 EX
TM

Integrated IDE
Subsystem

STD 32 and
STD-compatible
Local Bus
Video Option
AC/DC Power-Fail
Detection
Push-button reset
24 points of
Digital I/O
4 serial ports
1 parallel port
-2 RS-232
-2 RS-232/485
128 Kbyte SRAM
+5V operation
1 or 5 Mbyte
Pseudo Static RAM
1,2,or 4 Mbytes
Flash
ÛZIATECH
Major Components
PRODUCT DEFINITION
The ZT 8904 family of products includes the ZT 8904, ZT 89CT04, and ZT 8903
products. The following topics describe these products. Using the ZT 8904 without the
STD bus, as a single bus master, and as an STD 32®multiple master are also
discussed.

1. Introduction
 9
ZT 8904
The ZT 8904 is a highly integrated 386 EX single board computer. The board meets the
needs of a wide range of industrial control and processing applications by operating
stand alone, as a single master in an STD 32 architecture, or as a permanent or
temporary master in an STD 32 architecture.
ZT 89CT04
The ZT 89CT04 extends the ZT 8904 operating temperature range from 0 to 65º C to
-40º to +85º C. Except for the temperature variations, all other features of the ZT 8904
and ZT 89CT04 are the same. Unless explicitly stated otherwise, all references in this
manual to the ZT 8904 include the ZT 89CT04.
ZT 8903
The ZT 8903 is a more economical board that includes all the features of the ZT 8904
except those listed below. Unless explicitly stated otherwise, all references in this
manual to the ZT 8904 include the ZT 8903 as well.
•ZT 8904 supports an IDE drive option not available on the ZT 8903
•ZT 8904 supports a multiprocessing option not available on the ZT 8903
•ZT 8904 includes RS-485 support not available on the ZT 8903
•ZT 8904 includes four serial ports and the ZT 8903 includes two
•ZT 8904 includes 128 Kbytes of battery-backed RAM not available on the ZT 8903
Stand Alone
The ZT 8904 does not require an STD bus backplane to operate. The ZT 8904 is able to
operate stand-alone in many applications because of the large selection of the most
commonly needed peripheral devices. A power connector location and four mounting
holes are available for stand-alone operation.
STD 32 Single Master
The ZT 8904 supports additional memory and I/O through the STD bus. In an STD 32
architecture, data transfers are dynamically adjusted to support 8-bit and 16-bit boards.
STD 32 Multiple Master
The ZT 8904 can be configured to operate as a permanent master or as a temporary
master in a multiple master architecture. With this architecture, up to seven ZT 8904
boards share STD bus memory and I/O resources. The ZT 8903 does not support
multiple master operation.

1. Introduction
 10
FEATURES
•STD 32 compatible
•STD 32 multiprocessing option (not supported by ZT 8903)
•25 MHz Intel®386 EX CPU
•Numeric data processor socket
•Optional local bus video support
•128 Kbyte battery-backed Static RAM (not supported by ZT 8903)
•1, 2, or 4 Mbytes of Flash memory
•1 or 5 Mbytes of RAM memory
•Standard AT®peripherals include:
- Interrupt controllers (8259)
- Counter/timers (8254)
- Real-time clock/CMOS RAM (146818)
- DMA controller (8237)
•Additional AT®peripherals include:
- Two RS-232 serial channels
- Two RS-232/485 DMA capable serial channels (not supported by ZT 8903)
- IEEE 1284 parallel port (Centronics, ECP, EPP)
- Optional IDE disk drive (not supported by ZT 8903)
•24-point digital I/O with interrupt driven event sense and programmable debounce
•Two stage watchdog timer
•Pushbutton reset
•Software programmable LED
•AC/DC power monitor
•+5 V-only operation (Local charge pump for RS-232 and Flash programming)
•Compatible with the following software: MS-DOS®, OS/2®, UNIX®, QNX®, VRTX32®,
and Windows®3.1
•STD bus standard 4.5" x 6.5" board format
•DOS or STAR BIOS options
•Burned in at 55º Celsius and tested to guarantee reliability
•Five year warranty

1. Introduction
 11
DEVELOPMENT CONSIDERATIONS
Ziatech offers a variety of software options for ZT 8904 applications. These options
include STD ROM, STAR BIOS, and Ziatech's Industrial BIOS. Contact the Ziatech for
additional options.
STD ROM allows programmers to develop ROM-based applications without the use of
an operating system. STD ROM connects the ZT 8904 to an IBM-compatible personal
computer through a high speed serial link. The computer is used as a development
station to create, download, and debug applications written in assembly, C, and other
popular programming languages. The Paradigm Systems DEBUG/RT used during the
debug phase includes source level debugging, single step execution, breakpoints and
watchpoints.
The Ziatech Industrial BIOS provides the standard MS-DOS environment and services
in Flash memory on the ZT 8904. Ziatech Industrial BIOS provides standard support for
common peripherals and is supported by many third party development tools such as
program editors, compilers, assemblers, and debuggers. Refer to the Ziatech system
manual for configuration and operating instructions.
STAR BIOS is the DOS platform operating on more than one master in a single
STD bus system. Each master supports the Ziatech Industrial BIOS operating
environment and is capable of sharing STD bus memory and I/O, such as fixed disks,
floppy disks, and video. Refer to the STD 32 STAR SYSTEM™ operating manual for
configuration and operating instructions. The STAR BIOS is not available for the
ZT 8903.
FUNCTIONAL BLOCKS
The "Functional Block Diagram" on the next page illustrates the board's major functional
blocks. A description of the board's features and functional blocks is listed found in the
following topics.
STD Bus Interface
The ZT 8904 operates in STD 32 systems. In an STD 32 system, data transfers are
dynamically sized for either 8 bits or 16 bits. STD 32 compatible memory and I/O boards
are dynamically sensed to determine the width of the data transfer.
In addition to 16-bit data transfers, the STD 32 system provides the platform needed for
multiple master operation. In a multiple master system, up to seven ZT 8901, ZT 8902,
or ZT 8904 boards share STD bus resources with a fixed or rotating priority granted by
an external bus arbiter, such as the ZT 89CT39. The ZT 8903 does not support multiple
master operation.
See Chapter 3, "STD Bus Interface" for more information.

1. Introduction
 12
386 EX CPU
The ZT 8904 supports the Intel 386 EX CPU operating at 25 MHz. The 386 EX is a fully
static 32-bit CPU core integrated with standard PC peripherals. Integrated peripherals
include serial controller, interrupt controller, DMA controller, counter/timers, and
watchdog timer. The 386 EX supports a 64 Mbyte memory address space and a
64 Kbyte I/O address space.
24-Point
Digital I/O
Interrupt
Inputs
Two RS-232 and
Two RS-232/485
Serial Ports
Centronics Port
(ECP, EPP)
AC/DC
Power Detect
ZT 8904
25MHz 386 EX
CPU
®
Bus Interface
(Single and Multiple Master Operation)
Timers Watchdog
Timer
DMA
Controllers Interrupt
Controllers
Flash
Memory
(1, 2, or 4
Mbytes)
Pseudo
Static
RAM
(1 or 5
Mbytes)
Optional 387SX
Math Coprocessor
Battery-Backed
SRAM (128 Kbytes)
Battery
Real-Time
Clock
5V to 12V
Flash V
PP
Generator
Local Bus
Video
Expansion
IDE
Subsystem
Functional Block Diagram

1. Introduction
 13
Memory and I/O Addressing
The ZT 8904 includes 1 Mbyte of system RAM, 1, 2, or 4 Mbytes of Flash, and
128 Kbytes of battery-backed RAM. The battery-backed RAM is not available on the
ZT 8903. System RAM can be expanded from 1 Mbyte to 5 Mbytes with the addition of
an optional memory module. Memory operations up to 16 Mbytes that are not decoded
by local memory devices are directed to the STD bus.
Data transfers are dynamically adjusted to support standard architecture STD bus
memory boards with an 8-bit or 16-bit data path. The memory architecture selected for
the Ziatech Industrial BIOS architecture is shown in the "Memory Address Map" in
Chapter 2.
The ZT 8904 also includes many I/O peripherals required for industrial control
applications. I/O operations up to 64 Kbytes not decoded by local I/O devices are
directed to the STD bus. The STD bus I/O expansion signal, IOEXP, is supported to
limit the addressing redundancy of I/O boards decoding fewer than 16 bits of address.
Data transfers are dynamically adjusted to support standard architecture STD bus I/O
boards with an 8-bit or 16-bit data path. A20 is located at port 92h. Set bit 1 to 1 for
disable, 0 for enable. The I/O map architecture selected for the Ziatech Industrial BIOS
architecture is shown in the "I/O Address Map".
Local Bus Video
The ZT 8904 supports both STD bus and local bus video adapters. For STD bus video,
Ziatech offers video boards that support VGA and flat panel displays. For local bus
video, Ziatech offers zVID adapters that plug directly onto the ZT 8904 J6 local bus
connector. Local bus video is up to 300% faster than STD bus video because the data
transfers occur at the CPU operating speed of 25 MHz. For space-constrained
applications, the zVID offerings have the added advantage of not requiring the
additional card cage slot needed by the STD bus offerings.
Serial I/O
The ZT 8903 includes two RS-232 serial ports. The ZT 8904 and ZT 89CT04 include
four RS-232 serial ports, two of which can be software configured for RS-485 operation.
COM1 and COM2 are 16C450 compatible UARTs. COM3 and COM4 are 16C550
compatible UARTS. All of the serial ports include a complete set of handshaking and
modem control signals, maskable interrupt generation, and data transfer rates up to
115 Kbaud, and are implemented with a 5 V charge pump technology to eliminate the
need for a ±12 V supply.
The 386 EX multiplexes COM2 data and handshake signals with DMA signals. This
results in the loss of COM2 handshake if STD bus DMA is used and the complete loss
of COM2 if local printer or serial DMA is used. This selection is controlled with jumpers
W24 through W27 and BIOS configuration.

1. Introduction
 14
The serial ports are configured as DTE and are available through the J1 80-pin
frontplane connector. Optional cables convert the serial port interface to standard 9-pin
D-shell connectors. The ZT 90200 cable provides the serial interface for the ZT 8904
and ZT 89CT04. The ZT 90203 cable provides the serial interface for the ZT 8903. A
null-modem option is required to convert the DTE configuration to DCE.
See Chapter 8, "Serial Controller" for more information.
IEEE 1284 Parallel Port
The ZT 8904 includes an IEEE 1284 parallel port for supporting Centronics, EPP, and
ECP devices. The parallel port interface is available through the J1 80-pin frontplane
connector. An optional cable converts the parallel port interface to a standard 25-pin D-
shell connector. The ZT 90200 cable provides the parallel interface for the ZT 8904 and
ZT 89CT04. The ZT 90203 cable provides the parallel interface for the ZT 8903.
See Chapter 9, "Centronics Printer Interface" for more information.
Parallel I/O
The ZT 8904 includes three 8-bit parallel I/O ports for a total of 24 parallel I/O lines.
Each line is programmable as an input or an output with readback. The outputs sink
12 mA and do not glitch during power cycles. The 24 lines, available through the J4 50-
pin frontplane connector, also support software programmable signal debounce and
event sense interrupt generation.
An optional cable (ZT 90072 Digital I/O Cable) connects the parallel I/O interface to an
8, 16, or 24 position I/O module mounting rack, such as Ziatech's ZT 2226 24-Channel
I/O Mounting Rack or those offered by Opto 22®.
See Chapter 10, "Parallel I/O" for more information.
Interrupts
Two interrupt controllers provide a total of 15 interrupt inputs. Interrupt controller
features include support for level-triggered and edge-triggered inputs, fixed and rotating
priorities, and individual input masking. Interrupt sources include counter/timers, serial
I/O, parallel I/O, real-time clock, keyboard, printer, optional IDE drive, and multiple
master communications. There are also three frontplane and four STD bus interrupt
sources. Frontplane interrupts are available via connector J2.
See Chapter 4, "Interrupt Controller" for more information.

1. Introduction
 15
Timers
Three timers are included on the ZT 8904. Operating modes supported by the timers
include interrupt on count, frequency divider, square wave generator, software
triggered, hardware triggered, and one shot. The number of counter/timers available to
the application programmer depends on the operating system.
For example, the Ziatech MS DOS operating system uses timer 0 to generate system
tick and timer 2 to control the speaker. Timer 1 is available to the application.
See Chapter 5, "Counter/Timers" for more information.
DMA
One DMA controller provides two DMA channels for data transfers between local or
system I/O and local memory. DMA channel 0 supports both 8-bit and 16-bit STD bus
DMA slaves. The primary use for STD bus DMA is floppy disk expansion. Optionally,
DMA channel 0 supports the local 1284 parallel port or combines with DMA channel 1 to
support one of the local serial ports.
See Chapter 6, "DMA Controller" for more information.
Watchdog Timer
The two-stage watchdog timer optionally monitors system operation. Failure to strobe
the first stage within a programmable time period results in a non-maskable interrupt.
Failure of the non-maskable interrupt service routine to restart the watchdog results in a
stage two reset.
See Chapter 12, "Watchdog Timer" for more information.
Real-Time Clock
The real-time clock performs timekeeping functions and includes more than 200 bytes
of general-purpose battery-backed CMOS RAM.
Timekeeping features include an alarm function, a maskable periodic interrupt, and a
100-year calendar.
CMOS RAM available to the application programmer depends on the operating system.
For example, the Ziatech MS DOS operating system uses the CMOS RAM to store
configuration parameters.
See Chapter 7, "Real-Time Clock" for more information.

1. Introduction
 16
Keyboard Controller
The ZT 8904 includes a PC/AT®keyboard controller that operates when the zVID local
bus video adapter is installed. The keyboard connector is located on the zVID adapter.
AC Power-Fail Protection
With the addition of an AC transformer (connected to connector J3), the ZT 8904
monitors AC power to permit an orderly shutdown during a power failure. When AC
power falls below an acceptable operating range, a non-maskable interrupt is generated
to notify the CPU of an impending power failure. When the application software receives
this notification, it saves critical data before the CPU is reset.
See Chapter 16, "AC Power Fail," for more information.

 17
2. GETTING STARTED
This chapter summarizes the information needed to make the ZT 8904 operational.
Read this chapter before attempting to use the board.
UNPACKING
Please check the shipping carton for damage. If the shipping carton and contents are
damaged, notify the carrier and Ziatech for an insurance settlement. Retain the shipping
carton and packing material for inspection by the carrier. Save the anti-static bag for
storing or returning the ZT 8904.
Do not return any product to Ziatech without a Return Material Authorization (RMA)
number. Refer to Appendix D, "Customer Support," which explains the procedure for
obtaining an RMA number from Ziatech.
Warning: Like all equipment utilizing MOS devices, the boards must
be protected from static discharge. Never remove any of the
socketed parts except at a static-free workstation. Use the anti-static
bag shipped with your order to handle the boards.
SYSTEM REQUIREMENTS
The ZT 8904 is designed for use with or without an STD bus backplane. The ZT 8904 is
electrically, mechanically, and functionally compatible with the STD 32 Bus Specification
(ZT MSTD32) for STD bus applications. An STD 32 system is required for 16-bit data
transfers to other STD bus boards and for multiple master operation. The ZT 8903 does
not support multiple master operation.
Ziatech recommends vertical mounting and the use of a fan to provide the required
airflow. Refer to Appendix B, "Specifications," for additional specifications.
MEMORY CONFIGURATION
The ZT 8904 addresses 64 Mbytes of memory using a 26-bit memory address. The
memory map is programmable through the CPU chip select registers. The memory
architecture selected for the Ziatech Industrial BIOS architecture is shown in the
"Memory Address Map" figure. The ZT 8904 memory map includes several types of
memory.
System RAM - 16-bit pseudo static RAM
•Video RAM - located on the STD bus or zVID memory board
•Video BIOS - 16-bit pseudo static RAM shadowed from video board

2. Getting Started
 18
•Local RAM Drive - 8-bit battery-backed RAM (not available on the ZT 8903) paged
for 128 Kbytes
•System BIOS - 16-bit pseudo static RAM shadowed from Flash #0
•Extended RAM - Optional 16-bit pseudo static RAM module
•Flash #0 - 8-bit Flash
•Flash #1 - Optional 8-bit Flash
•STD bus Expansion - 8-bit or 16-bit expansion memory
•Reserved - Not available
STD bus expansion memory is transferred at a rate of up to 1 Mbyte/second for 8-bit
data and 1.5 Mbytes/second for 16-bit data. The ZT 8904 supports the STD bus wait
request signal, WAITRQ*, to interface to memory boards with longer access time
requirements than those defined by zero wait state STD 32 specifications. During local
memory operations, the STD bus is held static to decrease system electrical noise and
power consumption.
The ZT 8904 supports 128 Kbyte battery backed RAM (BRAM) devices. BRAM is paged
into the system memory map in 64 Kbyte increments at 0xD0000h through 0xDFFFFh.
Paging is performed by writing specific values to bits D4, D3 and D2 of System Register
0 (0X7Bh). BRAM pages are selected as follows:
•Write XXXX111Xh to select BRAM page 0
•Write XXXX110Xh to select BRAM page 1
If larger BRAM devices are installed, use sequential codes to select subsequent pages
in the memory map. Note that specific BRAM pages are used by both the Ziatech Single
Master BIOS and by the STAR System BIOS. The Ziatech Technical Support Group
can provide example code for using ZT 8904 BRAM.

2. Getting Started
 19
180000h-3FFFFFh
140000h-17FFFFh
100000h-13FFFFh
080000h-0FFFFFh
050000h-07FFFFh
010000h-04FFFFh
00E000h-00FFFFh
00D000h-00DFFFh
00C800h-00CFFFh
00C000h-00C7FFh
00A000h-00BFFFh
000000h-009FFFh
RESERVED
FLASH #0
FLASH #1
STD BUS EXPANSION
RESERVED
EXTENDED RAM
SYSTEM BIOS
LOCAL RAM DRIVE
STD BUS EXPANSION
VIDEO BIOS
VIDEO RAM
SYSTEM RAM
STD BUS EXPANSION
EXPANSION MODULE
Memory Address Map
I/O CONFIGURATION
The ZT 8904 addresses up to 64 Kbytes of I/O using a 16-bit I/O address. The I/O map
is programmable through the CPU configuration registers. The I/O map architecture
selected for the Ziatech Industrial BIOS architecture is shown in the "I/O Address Map"
figure following.
STD bus expansion I/O is transferred at a rate of up to 1 Mbyte/second for 8-bit data
and 1.5 Mbytes/second for 16-bit data. The ZT 8904 supports the STD bus wait request
signal, WAITRQ*, to interface to I/O boards with longer access time requirements than
those defined by zero wait state STD 32 specifications. The STD bus I/O expansion
signal, IOEXP, is also supported. The IOEXP signal is automatically driven low over the
I/O address range FC00h to FFFFh. Application software should use this address range
to access STD bus I/O boards decoding IOEXP and fewer than 16 bits of address to
prevent the board from being redundantly mapped throughout the 64 Kbyte I/O address
space. During local I/O operations, the STD bus is held static to decrease system
electrical noise and power consumption.

2. Getting Started
 20
F900h-FFFFh
F800h-F8FFh
F500h-F7FFh
F4D0h-F4FFh
F4C0h-F4CFh
F400h-F4BFh
F100h-F3FFh
F000h-F0FFh
03F8h-03FFh
03F6h-03F7h
02E8h-02EFh
02F8h-02FFh
02F0h-02F7h
02E0h-02E7h
0280h-02DFh
0278h-027Fh
0270h-0277h
026Eh-026Fh
0200h-026Dh
01F8h-01FFh
01F0h-01F7h
0100h-01EFh
00F0h-00FFh
00A2h-00EFh
00A0h-00A1h
0094h-009Fh
0092h-0093h
0090h-0091h
0080h-008Fh
0078h-007Fh
0070h-0077h
0068h-006Fh
0060h-0067h
0044h-005Fh
0040h-0043h
0024h-003Fh
0022h-0023h
0020h-0021h
0010h-001Fh
0000h-000Fh
03F0h-03F5h
AVAILABLE
CPU CONFIGURATION
AVAILABLE
CPU CONFIGURATION
WATCHDOG
CPU CONFIGURATION
AVAILABLE
COM1
IDE
RESERVED
AVAILABLE
COM2
RESERVED
COM4
COM3
RESERVED
PRINTER (IEEE 1284)
RESERVED
CPU CONFIGURATION
RESERVED
AVAILABLE
IDE
AVAILABLE
COPROCESSOR
AVAILABLE
INTERRUPT #2
AVAILABLE
CPU CONFIGURATION
AVAILABLE
DMA PAGE REGS
PARALLEL I/O
REAL TIME CLOCK
RESERVED
KEYBOARD
AVAILABLE
COUNTER / TIMERS
AVAILABLE
CPU CONFIGURATION
INTERRUPT #1
AVAILABLE
DMA
AVAILABLE
CPU CONFIGURATION
0400-05FFh
0300h-03EFh
AVAILABLE
RESERVED
0700-EFFFh
0600h-06FFh
I/O Address Map
CONNECTOR CONFIGURATION
The following figure shows the locations and assignments of connectors J1 - J8. See
"Connectors" in Appendix B for information on connector pin assignments and cabling.