Ziatech Corporation ZT 8952 Instructions for use

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Integrated Drive Electronics
(IDE) Interfaces
ZT 8952
ZT 8953
Hardware User Manual
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CONTENTS
MANUAL ORGANIZATION.....................................................................................................................4
1. INTRODUCTION .................................................................................................................................5
FEATURES.................................................................................................................................6
IDE HARD DISK.............................................................................................................6
BUS INTERFACE LOGIC...............................................................................................6
INTERRUPTS.................................................................................................................7
2. GETTING STARTED...........................................................................................................................8
UNPACKING...............................................................................................................................8
SYSTEM REQUIREMENTS........................................................................................................8
PHYSICAL REQUIREMENTS.........................................................................................8
POWER REQUIREMENTS.............................................................................................8
INSTALLATION...........................................................................................................................9
16-BIT VS. 8-BIT STD 32 TRANSFERS..........................................................................9
DISABLING THE ZT 8952 CONTROLLER......................................................................9
INTERRUPT SELECTIONS............................................................................................9
IDE DIAGNOSTIC ........................................................................................................10
3. OPERATIONAL OVERVIEW.............................................................................................................12
FREQUENTLY ASKED QUESTIONS........................................................................................12
STD BUS COMPATIBILITY.......................................................................................................16
CPU AND STD BUS INTERFACE.............................................................................................16
DATA TRANSFERS......................................................................................................16
MEMORY..................................................................................................................................16
I/O.............................................................................................................................................17
INTERRUPTS...........................................................................................................................18
DIRECT MEMORY ACCESS (DMA)..........................................................................................18
IDE REGISTERS ......................................................................................................................19
4. IDE INTERFACE ...............................................................................................................................20
IDE INTERFACE REGISTERS..................................................................................................20
DATA REGISTER.........................................................................................................20
ERROR REGISTER......................................................................................................20
WRITE PRECOMPENSATION REGISTER...................................................................21
SECTOR COUNT REGISTER......................................................................................21
SECTOR NUMBER REGISTER....................................................................................22
CYLINDER LOW REGISTER........................................................................................22
CYLINDER HIGH REGISTER.......................................................................................22
DRIVE/HEAD REGISTER.............................................................................................23
STATUS REGISTER ....................................................................................................24
COMMAND REGISTER................................................................................................25
ALTERNATE STATUS REGISTER...............................................................................27
DIGITAL OUTPUT REGISTER .....................................................................................27
DRIVE ADDRESS REGISTER......................................................................................28
5. IDE COMMAND DESCRIPTIONS......................................................................................................30
CORE COMMANDS..................................................................................................................30
OPERATIONS DESCRIPTION..................................................................................................38
RESET.........................................................................................................................38
BSY OPERATION ........................................................................................................38
DATA RETRY ALGORITHM.........................................................................................39
HEADER RETRY ALGORITHM....................................................................................40
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Contents
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ERROR REPORTING...............................................................................................................40
A. JUMPER CONFIGURATIONS ..........................................................................................................42
JUMPER OPTIONS ..................................................................................................................42
JUMPER DESCRIPTIONS........................................................................................................45
W1................................................................................................................................45
W2................................................................................................................................46
W3-W7.........................................................................................................................47
W11-W15 .....................................................................................................................48
W10A, W10B................................................................................................................48
W8................................................................................................................................49
W9................................................................................................................................49
B. SPECIFICATIONS............................................................................................................................50
REQUIREMENTS.........................................................................................................51
STD BUS LOADING CHARACTERISTICS ...................................................................51
MECHANICAL...........................................................................................................................54
CARD DIMENSIONS AND WEIGHT.............................................................................54
CONNECTORS............................................................................................................54
C. GLOSSARY......................................................................................................................................59
COMMAND CODES..................................................................................................................59
TERMINOLOGY........................................................................................................................60
D. CUSTOMER SUPPORT....................................................................................................................62
TECHNICAL/SALES ASSISTANCE...........................................................................................62
RELIABILITY.............................................................................................................................62
RETURNING FOR SERVICE....................................................................................................62
ZIATECH WARRANTY..............................................................................................................63
TRADEMARKS.........................................................................................................................63
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MANUAL ORGANIZATION
This manual describes the operation and use of the ZT 8952/8953. The term ZT 8952 is
used throughout the manual to reference both the ZT 8952 and the ZT 8953, except
where otherwise noted. Specific differences between the two are explicitly stated. Refer
to Appendix B for specifications.
Chapter 1, "Introduction," offers an overview of the ZT 8952. It includes a product
definition, a listing of product features, a functional block diagram, and a brief
description of each block. This chapter is most interesting to those comparing the
features of the ZT 8952 against the needs of a specific application.
Chapter 2, "Getting Started," summarizes the information essential to getting your
ZT 8952 operational. This includes system requirements and memory and I/O mapping.
In many cases, this information is all that is needed to begin using the ZT 8952.
Chapter 3, "Operational Overview," presents answers to some frequently asked
questions and a detailed description of the ZT 8952 interface to STD 32 bus structures.
Other topics discussed include memory, I/O, interrupt structure, and direct memory
access.
Chapter 4, "IDE Interface," discusses Integrated Drive Electronics (IDE) interface
registers.
Chapter 5, "IDE Command Descriptions," describes various commands performed via
the IDE command block.
Appendix A, "Jumper Configurations," describes the jumpers included on the
ZT 8952 to allow you to custom-configure your board.
Appendix B, "Specifications," contains the electrical, mechanical, and environmental
specifications for the ZT 8952.
Appendix C, "Glossary," lists the command codes and defines important terms and
acronyms used in this manual.
Appendix D, "Customer Support," offers a product revision history, technical support
information, and instructions for returning the ZT 8952 if service is necessary.
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1. INTRODUCTION
This chapter provides a brief introduction to the ZT 8952/8953 IDE Interface and
Mounting Board. It includes a product definition, a listing of product features, a
functional block diagram, and a description of each block. Unpacking information and
installation instructions are in Chapter 2, "Getting Started."
The term ZT 8952 is used throughout this manual to reference both the ZT 8952 and
the ZT 8953, except where otherwise noted.
The ZT 8952 is an Integrated Drive Electronics (IDE) interface for the STD 32 buses
that support PC-AT technology disk drives. The ZT 8952 also serves as a mechanical
mounting board for the drive, allowing for a modular plug-in unit for the STD bus. The
ZT 8952 supports 2½ inch disk drives, while the ZT 8953 supports 3½ drives, both
mounted directly to the board. The ZT 8952 is also available with no drive mounted
(ZT 8952-0) for applications that require remote mounting of the drive. Cables are
restricted to 18 inches in length from controller to drive. The ZT 8952 will support up to
two drives.
Mechanically, the ZT 8952 is compatible with the STD 32 Bus Specification. The
ZT 8952 supports 8 MHz and 5 MHz STD-80 timings, as well as STD 32 transfers. Both
8-bit and 16-bit transfers are supported under STD 32. The ZT 8952 will support up to
four Mbytes/second transfer rates on the backplane (one word every four 8-MHz
cycles.) The actual transfer rate will vary with the host CPU and drive used.
The PC-AT IDE interface is a 16-bit interface only when transferring data through the
01F0h data register. The ZT 8952 supports full 16-bit transfers for STD 32 processors.
For 8-bit processors, the ZT 8952 will byte pack and unpack the 16-bit IDE transfer to
provide 8-bit STD bus transfers. All signals are fully buffered between the STD bus and
the IDE interface. The IDE interrupt may be jumpered to drive INTRQ*, INTRQ1*,
INTRQ2* (CNTRL*), INTRQ3*, IRQx (STD 32), or one of five frontplane interrupts.
Some versions of Ziatech's STD DOS require the use of interrupts.
Onboard logic may be disabled for direct access to the IDE drive via the interface cable.
This is useful for accessing data from a board that already has an IDE interface (such
as the ZT 8910). The ZT 8952 will support an IDE drive of any capacity. The Ziatech
BIOS supports all drives sold by Ziatech. Contact Ziatech for BIOS support on drives
not supplied by Ziatech.
The ZT 8952 decodes I/O addresses 1F0h-1F7h and 3F6h-3F7h. All 16 bits of I/O
address are decoded to avoid contention at alias addresses.
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1. Introduction
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FEATURES
•STD 32 bus compatible
•PC-AT compatible register set
•4 Mbytes/second backplane transfer rate
•Integrated 2½ inch support (ZT 8952)
•Integrated 3½ inch support (ZT 8953)
•Standalone (non-integrated) support (ZT 8952-0)
•Frontplane interrupt capability
•16-bit/8-bit dynamic data transfer capability
•Burned in at 55º Celsius and tested
•STD 32 compliance
I/O Slave: SA16, SA8 - I, IXL, IXP
•Two-year warranty
The figure "Functional Block Diagram" illustrates the functional blocks of the ZT 8952. A
description of each block follows.
IDE Hard Disk
Either a 2½ inch drive (ZT 8952) or a 3½ inch drive may be mounted directly to the
interface to provide a compact, modular unit for STD applications. The drive may also
be remotely mounted and cabled. The cable length is restricted to 18 inches. The
interface is available via a 2 mm right angle female header or a 0.1 inch right angle
male header.
Bus Interface Logic
The ZT 8952 supports both 16-bit and 8-bit data transfers on the STD bus by packing
and unpacking the 16-bit IDE data on behalf of the IDE drive. For 16-bit STD 32 CPUs
the ZT 8952 will provide 16-bit data directly, allowing the maximum transfer rate of
4 Mbytes/second.
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1. Introduction
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Interrupts
The IDE interface normally drives an interrupt to the BIOS for data ready status. This
interrupt may be jumpered to either INTRQ*, INTRQ1*, INTRQ2* (CNTRL*), INTRQ3*,
or IRQx on the backplane. Alternatively, one of five frontplane interrupts may be
selected to provide interrupt support.
2- 1/2 in. or 3- 1/2 in.
IDE Hard Disk
Bus Interface Logic
Interrupts
16-Bit
ZT 8952/53
8- or
16-Bit
Interrupts
Functional Block Diagram
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2. GETTING STARTED
This chapter summarizes features of the ZT 8952 and ZT 8953. Since most features of
the two boards are identical, the term ZT 8952 is used for simplicity. Where features
differ, the specific product number is used. Read this chapter and Chapter 3,
"Operational Overview", before you use the board.
UNPACKING
Be sure to check the shipping carton for damage. If the shipping carton and contents
are damaged, notify the carrier and Ziatech for an insurance settlement. Retain the
original shipping carton and packing material for inspection by the carrier. Save the anti-
static bag for storing or returning the ZT 8952.
Do not return any product to Ziatech without a Return Material Authorization (RMA)
Number. Appendix D, "Customer Support", explains the procedure for obtaining an
RMA number from Ziatech.
Caution: Like all equipment utilizing MOS devices, the ZT 8952 must
be protected from static discharge. Never remove any of the socketed
parts except at a static-free workstation. Use the anti-static bag shipped
with the ZT 8952 to handle the board.
SYSTEM REQUIREMENTS
The ZT 8952 is designed for use in an STD bus application. The board is therefore
mechanically and electrically compatible with the STD 32 bus specifications.
Physical Requirements
ZT 8952 requires between one and three slots depending upon the size drive mounted
on the board. ZT 8953 requires between two and four slots depending upon the drive
used. See Appendix B, "Specifications", for specific drive requirements.
Power Requirements
Power required by the ZT 8952 and ZT 8953 is dependent upon the type of drive
interfaced to, since power for the drive is supplied by the controller board.
•The base board without drive requires 320 mA typical, 470 mA maximum at +5 V
•ZT 8952 with drive (for example, ZT 8952-40) requires only +5 V
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2. Getting Started
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•ZT 8953 with integrated drive (for example, ZT 8953-50) requires both +5 V and
+12 V for the drive
See Appendix B, "Specifications", for specific drive requirements.
Ziatech recommends vertical mounting for applications in which a fan is not used.
Horizontal mounting requires a minimum air flow of 30 cubic feet/minute passing over
the surface of the board.
INSTALLATION
If the ZT 8952 or ZT 8953 is used as an integrated unit you need only insert it into the
card cage. For non-integrated usage the drive needs to be mounted and a cable run
between the ZT 8952-0 and the drive. Be sure that the interfacing cable is no longer
than 18 inches.
The ZT 8952 is supported by Ziatech BIOS version 3.2 or greater on CPU boards that
do not have an onboard IDE interface (for example, ZT 8910).
The ZT 8952 includes several jumper options that tailor the operation of the board to
specific application requirements. The following jumper configurations are suggested.
These configurations will vary depending upon the application.
16-Bit Vs. 8-Bit STD 32 Transfers
Jumper W2 controls whether or not the board looks at BHE* on the backplane. This
jumper must be installed for BHE* to be decoded and 16-bit transfers to take place in
STD 32 backplanes with 16-bit processors (SA16). In an 8-bit backplane W2 should be
removed because STD-80 CPUs drive BHE* (MEMEX) in non-standard fashion. W2
must be installed for SA16 CPU boards (for example, ZT 8902 or ZT 8911).
Disabling the ZT 8952 Controller
You can disable the logic on the ZT 8952 by removing W9. This procedure may be
useful for diagnostic/debugging purposes.
Interrupt Selections
Jumpers W3-W7 and W11-W15 select which, if any, interrupt the IDE interface can
drive to the STD bus. W3-W7 select one of five frontplane interrupts, while W11-W15
select the backplane interrupt to be driven. The ZT 8902, ZT 8911, and all STD 32
STAR SYSTEMS require W15 to be installed.
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2. Getting Started
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IDE Diagnostic
Some IDE drives feature an internal diagnostic for use when two drives are daisy
chained. Both drives execute this diagnostic. The slave drive then indicates to the
master a successful completion of the diagnostic.
Jumper W8 lets you drive the signal low for any master that needs this default. No drive
currently shipped by Ziatech requires installation of this jumper.
Jumper Requirements—16-Bit Transfers
Installed: W1, W2, W5, W9, W10A
Not installed: W3, W4, W6,W7, W8,W10B, W11,W12,W13,W14,W15
This configuration selects 16-bit transfers and does not drive any backplane interrupt.
W5 is loaded to select FP5*, but some versions of STD DOS will use alternative
selections. If you need an interrupt, remove the jumper from W5 and use it to select the
desired interrupt. The ZT 8902, ZT 8911, and all STAR SYSTEMS require W15 to be
installed.
Jumper Requirements—8-Bit Transfers
Installed: W1, W5, W9, W10A
Not installed: W2, W3, W4,W6, W7, W8, W10B, W11, W12,W13, W14, W15
This configuration does not allow the ZT 8952 to respond to BHE*. Use this
configuration when installing this board in non-STD 32 card cages. Some CPU cards
drive BHE* (STD-80 MEMEX) in non-standard ways and will cause the board to
misalign data. For this reason we recommend that W2 be removed in 8-bit CPU
systems or in STD-80 backplanes.
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2. Getting Started
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STD 32 Compliance
STD 32 peripherals are required to meet certain compliance standards. This allows the
system integrators to match capabilities among different manufacturers' boards.
The ZT 8952 has the following STD 32 compliance:
I/O Slave: SA16, SA8 - I, IXL, IXP
Definitions:
•SA16: STD-80 style 16-bit transfers
•SA8: STD-80 style 8-bit transfers
•I: Drives INTRQ*, INTRQ1*, INTRQ2* (CNTRL*), INTRQ3*
•IXL: Drives IRQx active low
•IXP: Drives IRQx with positive active edge
STD 32 peripheral boards are available from a variety of manufacturers.
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3. OPERATIONAL OVERVIEW
This chapter presents an operational overview of the hardware for ZT 8952. The board's
functions are described in detail, and answers are provided for some commonly asked
questions.
Other topics discussed in this chapter include:
•Using the ZT 8952 in an STD DOS application
•Using the ZT 8952 in 8-bit and 16-bit mode
•How the ZT 8952 I/O is mapped into the STD I/O space
•Drive interfacing
FREQUENTLY ASKED QUESTIONS
Is ZT 8952 compatible with STD 32?
Yes. ZT 8952 meets timing requirements for STD 32 bus structures. STD 32 is a
superset of STD-80.
What is the IDE Interface?
IDE stands for Integrated Drive Electronics. IDE applies to PC-AT style controllers and
to any other drive using front end logic to manage the physical media. This logic
improves performance by relieving an external controller's need to manage the physical
media. While the AT style IDE drive is the most popular interface, other drives are
available for other standards. "IDE drive", as used in this context, is an AT style IDE
drive.
The IDE interface is a 16-bit interface for the IBM AT. How does ZT 8952 allow
operation within the STD bus and with 8-bit CPUs?
ZT 8952 uses control logic to convert from the STD bus to the IDE interface. Byte
packing and unpacking is done for the IDE interface during transfers to and from the
STD bus. The first byte in 8-bit CPU data writes is buffered, then written to the drive
when the second (odd) byte is transferred. The logic latches the odd byte of the 16-bit
read, while returning the even byte. The latched data is returned on the next read to the
odd byte location.
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3. Operational Overview
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Does the ZT 8952 support full 16-bit transfers?
Yes. When used in an STD 32 backplane with a 16-bit CPU board such as the ZT 8901,
ZT 8952 performs 16-bit transfers during the data transfer phase of a disk read or write.
16-bit transfers allow backplane transfers of up to 4 Mbytes/second. Only 8-bit transfers
are performed within older STD-80 series backplanes, or with 8-bit processors.
Can I use ZT 8952 with a CPU such as ZT 8910, which has a built in IDE
controller?
Yes. You can use ZT 8952 for hard disk service if it is possible to disable the IDE
controller on board the CPU (as with ZT 8910). Most of these CPUs need IRQ14
asserted by the off-board IDE controller. IRQ14 must then be routed to the appropriate
address so that the CPU card can service the interrupt. This is not supported by STD
DOS. Contact Ziatech for configuring the ZT 8952 in this manner.
What types of IDE drives can the ZT 8952 interface to?
The ZT 8952 has two connector locations for interfacing. The first, J1, is a 0.1 inch
center, right angle header that is used to cable to 3½ inch drives via a standard 0.050
inch ribbon cable. This is the type of cable found inside the typical PC-AT clone. The
second connector location, J2, allows for either a female, right angle, 2 mm connector
for direct drive mounting or a header style 2 mm cable used to cable to a remote drive
via a 1 mm ribbon cable 2½ inch drives use the 2 mm connector. The connector used
depends upon the connector type used by the drive.
Ziatech BIOS versions greater than 4.0 support a configurable drive parameter option
(called USER). This option allows the BIOS to immediately support new drives by
entering the exact number of cylinders, heads, and sectors.
Do I need to low-level format the IDE drive?
No, this is not recommended. The IDE concept isolates the user from the drive
interface. Manufacturers may occasionally take advantage of this to squeeze higher
capacity out of the drive. This is often done by varying the rotational speed of the drive
for different tracks; more data can be packed in outer tracks by slowing the disk down
for outside tracks. If a low-level format is issued the drive will typically zero the data and
return a completed status rather than actually put down new format data. Most
manufacturers do not recommend that their drive be low-level formatted.
How does the IDE drive differ from what I have in my PC-AT at home?
From a software standpoint the IDE drive behaves in identical fashion. The same tools
used to set up a "normal" AT hard disk are used for the ZT 8952-IDE combination.
FDISK is used to partition the drive. DOS FORMAT is used to format and enter the
system information into the hard disk. Do not confuse the DOS FORMAT utility with the
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3. Operational Overview
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low-level formatting provided by the manufacturer. DOS FORMAT verifies sectors,
writes out directory information, and the like. See the preceding question above.
How do I select which drive in a two-drive system is Drive C: or Drive D:?
FDISK is used to partition each drive. In a two-drive system, the primary DOS partition
on Drive 0 will be designated drive C:. The primary partition on Drive 1 will be
designated drive D:. Drive letters are then first sequentially allocated to the remaining
logical drives in the logical partition of Drive 0. The remaining logical drives on Drive 1
are then assigned sequential drive letters. For example, consider a two-drive system
composed of four logical drives on each physical drive. A total of eight logical drives are
distributed as follows.
Drive C: Fixed Disk 0 Primary Partition
Drive D: Fixed Disk 1 Primary Partition
Drive E: Fixed Disk 0 Extended Partition
Drive F: Fixed Disk 0 Extended Partition
Drive G: Fixed Disk 0 Extended Partition
Drive H: Fixed Disk 1 Extended Partition
Drive I: Fixed Disk 1 Extended Partition
Drive J: Fixed Disk 1 Extended Partition
Drive C: is assigned to the primary partition in a single drive system. The FDISK
process determines partition size, maximum being 33 Mbytes for DOS version 3.3 and
below. Newer DOS versions allow larger partitions.
What are the shock and vibration specifications for IDE drives?
Because shock and vibration specifications often differ between models and between
manufacturers, presenting a generic specification for all IDE drives would be
misleading. In general, 2½ inch drives fare better than do their 3½ inch counterparts,
mainly because of their smaller mass and more compact design. Please call Ziatech if
you need specifications for a particular drive.
Should I FDISK and FORMAT the disk when I receive the ZT 8952 as an integrated
unit?
All drives are already FDISKed and FORMATted when you receive them. If bought as a
system component the drive has been tested at the system level. The size of the
partitions on larger drives, however, may not be tailored to your particular needs.
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3. Operational Overview
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Ziatech recommends that you FDISK and FORMAT the disk in order to avoid any
ambiguity with this issue.
How do I install a second drive to the system?
For ZT 8952-X users (for example, ZT 8952-40) it is not possible to install a second
drive because the system lacks a cable mechanism.
For ZT 8953-X users (for example, ZT 8953-50) a number of modifications are needed.
A new power cable must be extended to the second drive. Jumpers on the existing drive
must be changed from default for setup as master, and on the new drive for setup as
slave. These jumpers differ depending on the drive manufacturer. We recommend that
you contact Ziatech for drive-specific configurations for a two-drive system.
In general, a higher capacity drive is more cost effective than two drives in a
master/slave arrangement. A single drive will generally require less power and have a
better Mean Time Between Failure.
The ZT 8952 does not work with my old revision (prior to Rev. A.2) ZT 8950 Floppy
Disk Controller. Why?
Since the ZT 8952 and ZT 8950 share I/O register 3F7h, the ZT 8950 was revised to
A.2 to allow correct operation with the ZT 8952. Be sure your ZT 8950 is Revision A.2 or
greater.
I recently received revision 0.2 boards with a new jumper that was not present on
revision 0 or 0.1 boards. What is W15 for?
W15 adds the capability to drive INTRQ3* on the STD 32 backplane. Your ZT 8902 or
ZT 8911 processor board uses INTRQ3* by default for the hard disk interrupt.
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3. Operational Overview
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STD BUS COMPATIBILITY
The ZT 8952 is compatible with Version 1.2 of the STD 32 Bus Specification , a superset
of the STD-80 Series Bus Specification.
CPU AND STD BUS INTERFACE
The ZT 8952 interfaces two standards, the IDE interface and the STD bus. In addition to
signal reformatting, ZT 8952 also performs byte packing and unpacking for 8-bit CPUs
when transferring to and from the 16-bit only IDE interface. A state machine handles
this transfer in dynamic fashion. In 16-bit STD 32 card cages ZT 8952 will perform 16-bit
data transfers directly to and from the IDE drive and the STD 32 bus. 16-bit transfers
allow a maximum data transfer rate of 4 Mbytes/second, assuming four clocks per
transfer, or 3.2 Mbytes/second with five clocks per transfer.
Data Transfers
The ZT 8952 performs both 8-bit and 16-bit transfers as defined by the host processor.
All transfers are eight bits except to I/O address 1F0h, which causes the ZT 8952 to
drive the signal IO16* low. This informs the CPU that a 16-bit transfer is desired. If the
CPU is a 16-bit processor such as the ZT 8901, and the system is an STD 32 system,
the processor will drive BHE* low. This indicates to ZT 8952 that a high data byte is
being transferred during this cycle.
For 8-bit processors or for 16-bit processors used in older 8-bit backplanes it is
recommended that W2 be removed so that BHE* is not used. BHE* was formerly a
STD-80 signal called MEMEX that was not clearly defined. Some processors either
drive this signal low or allow it to be driven via a parallel port bit. Since ZT 8952
interprets this signal for data size, an 8-bit transfer would be misinterpreted as a 16-bit
transfer should BHE* be driven low. W2 should be installed when the ZT 8952 is used in
an STD 32 backplane with a 16-bit processor. W2 may be left installed when used with
an 8-bit processor that always drives BHE* (the old MEMEX signal) high.
MEMORY
The ZT 8952 does not occupy any part of the memory map.
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3. Operational Overview
 17
I/O
The ZT 8952 decodes two address ranges within the I/O map. The primary address
range used is 1F0h-1F7h and the secondary is 3F6h-3F7h. Note that use with the
ZT 8950 Floppy Disk Controller requires that the ZT 8950 be Revision A.2 or greater.
This is because both the ZT 8952/8953 and the ZT 8950 share register 3F7h.
HCS1*
HCS0*
Task File Registers
1F0h
1F7h
3F6h
3F7h
FFFFh
0
I/O Map
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3. Operational Overview
 18
INTERRUPTS
ZT 8952 can drive one of four backplane interrupts or one of five frontplane interrupts
with the IDE interrupt. Any systems shipped that require interrupt usage will contain the
appropriate interrupt jumper loaded by the system integrator. The "Interrupt Structure"
figure below illustrates the possible interrupt selections. ZT 8902 and ZT 8911 systems
should have W15 installed.
Interrupt
Logic W7
W6
W5
W4
W3
2 FP1*
4 FP3*
6 FP5*
8 FP6*
10 FP7*
J 3
W11
W12
W13
W14
E47
P37
P44
P50
INTRQ1*
INTRQ*
INTRQ2*
(CNTRL*)
+
W1
Note:W1 and W5
are default in.
IRQx
W15
E67
INTRQ3*
Interrupt Structure
DIRECT MEMORY ACCESS (DMA)
The ZT 8952 and IDE interface do not require Direct Memory Access (DMA) services
from any host.
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3. Operational Overview
 19
IDE REGISTERS
The IDE Interface is composed of 10 register locations. Eight of these are decoded at
1F0h-1F7h, with the remaining two at 3F6h and 3F7h. The "I/O Register Addresses and
Functions" table below defines all of the register addresses and functions for these I/O
locations.
I/O Register Addresses and Functions
I/O PORT I/O READ I/O WRITE
ADDRESS FUNCTION FUNCTION
1F0h†Data Register Data Register
1F1h Error Register Write Precompensation Reg.
1F2h Sector Count Sector Count
1F3h Sector Number Sector Number
1F4h Cylinder Low Cylinder Low
1F5h Cylinder High Cylinder High
1F6h SDH Register SDH Register
1F7h Status Register Command Register
3F6h Alt. Status Reg. Digital Output Register
3F7‡Drive Address Reg. Not Used
These registers are described in greater detail in Chapter 4, "IDE Interface."
†16-bit transfer
‡3F7h is shared with the floppy disk interface
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