2
CONTENTS
MANUAL ORGANIZATION.....................................................................................................................4
1. INTRODUCTION .................................................................................................................................5
FEATURES.................................................................................................................................6
IDE HARD DISK.............................................................................................................6
BUS INTERFACE LOGIC...............................................................................................6
INTERRUPTS.................................................................................................................7
2. GETTING STARTED...........................................................................................................................8
UNPACKING...............................................................................................................................8
SYSTEM REQUIREMENTS........................................................................................................8
PHYSICAL REQUIREMENTS.........................................................................................8
POWER REQUIREMENTS.............................................................................................8
INSTALLATION...........................................................................................................................9
16-BIT VS. 8-BIT STD 32 TRANSFERS..........................................................................9
DISABLING THE ZT 8952 CONTROLLER......................................................................9
INTERRUPT SELECTIONS............................................................................................9
IDE DIAGNOSTIC ........................................................................................................10
3. OPERATIONAL OVERVIEW.............................................................................................................12
FREQUENTLY ASKED QUESTIONS........................................................................................12
STD BUS COMPATIBILITY.......................................................................................................16
CPU AND STD BUS INTERFACE.............................................................................................16
DATA TRANSFERS......................................................................................................16
MEMORY..................................................................................................................................16
I/O.............................................................................................................................................17
INTERRUPTS...........................................................................................................................18
DIRECT MEMORY ACCESS (DMA)..........................................................................................18
IDE REGISTERS ......................................................................................................................19
4. IDE INTERFACE ...............................................................................................................................20
IDE INTERFACE REGISTERS..................................................................................................20
DATA REGISTER.........................................................................................................20
ERROR REGISTER......................................................................................................20
WRITE PRECOMPENSATION REGISTER...................................................................21
SECTOR COUNT REGISTER......................................................................................21
SECTOR NUMBER REGISTER....................................................................................22
CYLINDER LOW REGISTER........................................................................................22
CYLINDER HIGH REGISTER.......................................................................................22
DRIVE/HEAD REGISTER.............................................................................................23
STATUS REGISTER ....................................................................................................24
COMMAND REGISTER................................................................................................25
ALTERNATE STATUS REGISTER...............................................................................27
DIGITAL OUTPUT REGISTER .....................................................................................27
DRIVE ADDRESS REGISTER......................................................................................28
5. IDE COMMAND DESCRIPTIONS......................................................................................................30
CORE COMMANDS..................................................................................................................30
OPERATIONS DESCRIPTION..................................................................................................38
RESET.........................................................................................................................38
BSY OPERATION ........................................................................................................38
DATA RETRY ALGORITHM.........................................................................................39
HEADER RETRY ALGORITHM....................................................................................40
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