4DSP FMC204 User manual

UM008 FMC204 User Manual r1.14
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FMC204
User Manual
4DSP LLC, USA
Email: suppo[email protected]
This document is the property of 4DSP LLC and may not be copied nor communicated to a
third party without the written permission of 4DSP LLC.
© 4DSP LLC 2014

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Revision History
Date
Revision
Revision
2010-07-19
Initial release
1.0
2010-09-20
Added details about programming the FMC204,
including SPI timing waveforms.
Added FMC signal description in the Appendix.
Added CPLD register definition in the Appendix.
1.1
2010-10-03
Text corrections in pin list.
1.2
2010-10-12
Update address. Update block diagram
1.3
2011-01-03
Text corrections
1.4
2011-03-01
Added MICTOR connector references
1.5
2011-03-09
Added coax connector type specification
1.6
2011-04-14
Added FMC connector type specification.
Updated trigger input specification.
1.7
2011-08-01
Update external clock/reference input level.
1.8
2011-01-10
Added I2C pins to the pin-out table.
Updated some performance numbers.
1.9
2012-10-17
Added changes between revision 1 and revision 2
boards
1.10
2013-08-21
Corrected the directions in Table 9.
1.11
2013-09-16
Updated Figure 1 and Table 3 - CPLD I/O Voltage
Levels to 2.5V or VADJ
1.12
2014-03-06
Changed input power level of external reference
1.13
2014-04-14
Revised some descriptions and fixed typos
1.14

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Table of Contents
1Acronyms and related documents ............................................................................. 4
1.1 Acronyms................................................................................................................ 4
1.2 Related Documents................................................................................................. 4
2General description..................................................................................................... 5
3Installation ................................................................................................................... 6
3.1 Requirements and handling instructions.................................................................. 6
3.2 LVDS requirements................................................................................................. 6
4Design .......................................................................................................................... 7
4.1 Physical specifications ............................................................................................ 7
4.1.1 Board Dimensions............................................................................................ 7
4.1.2 Front panel coax inputs.................................................................................... 7
4.1.3 Front panel HDMI I/O....................................................................................... 7
4.1.4 (LV)TTL I/O...................................................................................................... 7
4.2 Electrical specifications........................................................................................... 8
4.2.1 EEPROM ......................................................................................................... 8
4.2.2 JTAG................................................................................................................ 8
4.2.3 FMC HPC......................................................................................................... 8
4.3 Main characteristics................................................................................................10
4.4 Analog output channels..........................................................................................10
4.5 External clock input................................................................................................10
4.6 External trigger/sync input......................................................................................11
4.7 Clock Tree..............................................................................................................11
4.7.1 Control............................................................................................................12
4.8 Multi-Gigabit Transceivers......................................................................................12
4.9 Power supply..........................................................................................................14
4.10 Synchronizing multiple cards ..............................................................................15
5Controlling the FMC204..............................................................................................16
5.1 Architecture............................................................................................................16
5.2 SPI Programming...................................................................................................17
6Environment................................................................................................................19
6.1 Temperature ..........................................................................................................19
6.2 Monitoring..............................................................................................................19
6.3 Cooling...................................................................................................................20
6.3.1 Convection cooling..........................................................................................20
6.3.2 Conduction cooling..........................................................................................20
7Safety...........................................................................................................................20
8EMC .............................................................................................................................20
9Warranty......................................................................................................................21
Appendix A HPC pin-out FMC204.................................................................................22
Appendix B CPLD Register map...................................................................................25

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1 Acronyms and related documents
1.1 Acronyms
ADC
Analog-to-Digital Converter
DDR
Double Data Rate
EPROM
Erasable Programmable Read-Only Memory
FBGA
Fineline Ball Grid Array
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Gate Array
JTAG
Join Test Action Group
LED
Light Emitting Diode
LVTTL
Low Voltage Transistor Logic level
LSB
Least Significant Bit(s)
LVDS
Low Voltage Differential Signaling
MGT
Multi-Gigabit Transceiver
MSB
Most Significant Bit(s)
PCB
Printed Circuit Board
PLL
Phase-Locked Loop
PSSR
Power Supply Rejection Ratio
Table 1: Glossary
1.2 Related Documents
FPGA Mezzanine Card (FMC) standard ANSI/VITA 57.1-2010
Datasheet DAC5682Z, TI
Datasheet AD9517-3, Analog Devices
Datasheet ADT7411 Rev B, Analog Devices

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2 General description
The FMC204 is a quad-channel D/A FMC. The FMC204 provides four 16-bit D\A channels
that enable simultaneous sampling at a maximum rate of 1 Gsps. The sample clock can be
supplied externally through a coax connection or by an internal clock source (optionally
locked to an external reference). A trigger input for customized sampling control is also
available.
The FMC204 daughter card is mechanically and electrically compliant to the FMC standard
(ANSI/VITA 57.1). The card has a high-pin count (HPC) connector, front panel I/O, and can
be used in a conduction-cooled or conventional air-cooled environment.
The FMC204 allows flexible control of clock source, sampling frequency, and calibration
through a SPI communication bus. The FMC204 card is equipped with power supply and
temperature monitoring with several power-down modes to switch off unused functions to
reduce system level power and heat. The FMC204 is well-suited for software defined radio
(SDR), battery, or other low power source applications. It is ideal for airborne applications
where power demand affects mission range and on-station mission time.
DAC A
FMC High-pin Count 400-pins
LVDS
Board
Monitoring
LVDS Clock [1]
Clock / Sync
Tree
DAC B
D/A: DAC5682Z
16-bit @ 1 Gsps
DAC C
DAC D
LVDS Data [16]
LVDS Clock [1]
LVDS Data [16]
Board
Control
I2C
D/A: DAC5682Z
16-bit @ 1 Gsps
Clock /
Reference
Trigger /
Sync
EEPROM
x
1
/
x
2
x
1
/
x
2
LVDS Clock [1]
MGT [4]
LVDS Trigger [1] Tx [5]
MICTOR 38-pins
Multi Gigabit Transceiver
(optional on revision 1)
MICTOR 38-pins
Multi Gigabit Transceiver
(optional on revision 1)
HDMI
LVTTL [4]
Status & Control
LVDS Sync [1]
1:2
Rx [5]
Tx [5]
Rx [5]
2.5V / Vadj level single
ended [4]
Figure 1: FMC204 block diagram

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3 Installation
3.1 Requirements and handling instructions
The FMC204 daughter card must be installed on a carrier card compliant to the FMC
standard.
The FMC carrier card must support the high-pin count connector (HPC 400-pins).
The carrier card must support VADJ/VIO_B voltage of +2.5V (LVDS support) for
FMC204 revision 1. The carrier card can support VADJ/VIO_B voltage range of 1.65V
to 3.3V for FMC204 revision 2, but typically VADJ will be 1.8V or 2.5V for LVDS
operation.
Do not flex the card.
Prevent electrostatic discharges by observing ESD precautions when handling the
card.
3.2 LVDS requirements
Each D/A device has an independent DDR LVDS data bus. When a D/A device is operated
in single-channel mode, the full rate of 1Gsps is supported. The digital transfer rate can be
lowered by enabling the interpolation (x2 or x4) in the D/A devices. When the D/A devices
are operated in dual-channel mode, the maximum data rate without interpolation is 500
Msps. 1Gsps can be achieved using the times 2 interpolation in the D/A devices.

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4 Design
4.1 Physical specifications
4.1.1 Board Dimensions
The FMC204 card complies with the FMC standard known as ANSI/VITA 57.1. The card is a
single-width, conduction-cooled mezzanine module (with region 1 and front panel I/O).
4.1.2 Front panel coax inputs
There are six coax connectors available from the front panel. From top to bottom: 1st analog
output (A), 2nd analog output (B), 3rd analog output (C), 4th analog output (D), clock input
(CL), and trigger input (TR).
Figure 2: Bezel drawing
4.1.3 Front panel HDMI I/O
The 19-pins HDMI connector on the front panel (IO) holds four multi-gigabit transceivers (two
Tx pairs / two Rx pairs) and 4x LVTTL I/O (5V tolerant). Contact 4DSP for other
configurations.
Pin Number
Signal Name
Pin Number
Signal Name
1
DP_M2C_P<0>
20
GND
2
Shield
19
N.C.
3
DP_M2C_N<0>
18
N.C.
4
DP_M2C_P<1>
17
N.C.
5
Shield
16
FRONT_IO<1>
6
DP_M2C_N<1>
15
FRONT_IO<0>
7
DP_C2M_P<2>
14
FRONT_IO<3>
8
Shield
13
FRONT_IO<2>
9
DP_C2M_N<2>
12
DP_C2M_N<3>
10
DP_C2M_P<3>
11
Shield
Table 2: HDMI connector pin out
4.1.4 (LV)TTL I/O
A voltage translator is used for the (LV)TTL signals available on the front panel. The front
side is either 3.3V for LVTTL or 5.0V for TTL (build option). The inputs are 5V tolerant when
powered with 3.3V. The direction is controlled by the CPLD.

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4.2 Electrical specifications
The FMC204 uses high-speed LVDS outputs. Revision 1 boards require +2.5V on VADJ
power supply (supplied by the carrier card). Revision 2 boards can operate with a VADJ
voltage range of 1.65V to 3.3V, but typically VADJ will be 1.8V or 2.5V for LVDS operation.
The voltage on VIO_B pins will be at the same level as VADJ as it is connected directly to
VADJ on the FMC204.
The data converters operate in LVDS mode (clock and data pairs). All other status and
control signals, like serial communication busses, operate at LVCMOS level (VOH = VADJ).
4.2.1 EEPROM
The FMC204 card carries a 2Kbit EEPROM which is accessible from the carrier card through
the I2C bus. The EEPROM is powered by 3P3VAUX. The standby current is only 0.01µA
when SCL and SDA are kept at 3P3VAUX level. These signals may also be left floating since
pull-up resistors are present on the card.
4.2.2 JTAG
The CPLD device is included in the JTAG chain accessible from the FMC connection. The
user should NOT reprogram or erase the CPLD.
4.2.3 FMC HPC
The high-pin count connector has four dedicated LVDS clock pairs and can host up to 80
LVDS (data) pairs. Refer to appendix A for a detailed pin-out.

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# Pairs
# Clock pairs
# Data pairs
LVDS Clock
1
1
LVDS Trigger
1
1
LVDS Sync
1
1
DAC #1
18
LVDS Clock
1
LVDS Sync
1
LVDS Data
16
DAC #2
17
LVDS Clock
1
LVDS Sync
0
LVDS Data
16
2.5V or VADJ Level I/O
routed to CPLD (see board
revision)
0
4
# Total pairs
3
39
Table 3: HPC signal usage
1
1
Signal CLK3_BIDIR_P/N is not connected.

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4.3 Main characteristics
Analog outputs
Number of channels
4
Output voltage range
Max. 1.0Vp-p
Load
50Ω
Connector type
SSMC (AEP 7110-1511-000)
THD
-65dBc
Analog Bandwidth
Max. 500MHz
External Clock/Reference input
Input level
-6dBm to +7dBm
Input impedance
50Ω AC-coupled
Connector type
SSMC (AEP 7110-1511-000)
Input range
10 –100 MHz (reference clock)
100 –1000 MHz (sample clock)
External Trigger/Sync input
Input threshold level
1.25V typical (LVTTL level supported)
Input impedance
2.5kΩDC-coupled
Connector type
SSMC (AEP 7110-1511-000)
Frequency range
Up to 500 MHz
DAC input
Input data width
1x 16-pairs DDR 1Gbps
Data Format
Two’s Complement / Offset binary
FMC connector type
HPC (ASP-134488-01)
Sampling Frequency Range
100 –1000 MHz
Internal Clock/Reference
Format
LVPECL
Frequency Range
100 MHz (reference clock)
100, 125, 200, 250, 500, or 1000 MHz (sample clock)
(Contact 4DSP for customized frequencies)
Table 4 : FMC204 daughter card main characteristics
4.4 Analog output channels
The FMC204 has four single-ended analog outputs that are AC-coupled from the D/A device.
An RF transformer (TC4-1W, 3-800MHz) is used. The analog outputs are designed to drive a
50Ωload. The maximum output voltage range is 1.0VP-P.
4.5 External clock input
The external clock input can be configured in two ways (see also Figure 4):

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1. Sample clock input, connecting to the clock input of the AD9517.
2. Reference clock input, connecting to the reference input of the AD9517.
4.6 External trigger/sync input
The external trigger input can be configured in different ways with custom build options. The
trigger input can be 50Ωterminated to accept most common high-speed signalling standards
like single-ended LVPECL. By default, the 50Ω termination is not mounted to support
LVTTL/LVCMOS and similar input standards. Differential input is also possible using the
coax shield as inverted signal. By default, the input is single-ended and DC-coupled with an
input impedance of approximately 2.5kΩ. The input threshold is approximately 1.25V.
The trigger input can also be used as sync input, synchronizing local A/D converters or
multiple FMC204 cards.
TRIGGER LVDS
DAC #1
RESET
SYNC
SYNCOUT
from FMC
to FMC
DAC #2
SYNC
Analog Out
Analog Out
Figure 3: D/A Synchronization topology
Synchronization of multiple D/A devices in parallel is done through the SYNC input. The
SYNC signal is driven by the FPGA and can be derived from the trigger input. Since the
SYNC input has an internal 100R termination resistor, a 1:2 fan-out buffer is used to connect
a single LVDS signal to both D/A converters.
4.7 Clock Tree
The FMC204 offers a clock architecture that combines flexibility and high performance.
Components have been chosen to minimize jitter and phase noise to reduce degradation of
the data conversion performance. The user may use an external or internal sampling clock.
The clock tree has a PLL and clock distribution section. The PLL ensures locking of the
internal clock to an externally supplied reference. There is an onboard reference which is
used if no external reference is present.
A VCO (998-1001MHz, Z-Communications, CLV1000A-LF) is used as internal clock source
and can connect to the distribution section instead of the external clock input. The distribution
section drives the D/A devices with the LVPECL outputs. One LVDS clock output is
connected to the FMC connector as a reference for the digital data transferred to the D/A
devices.

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Clock
To FMC
VC(X)O
1.0 GHz
XTAL
100MHz
Loop
Filter
DAC 1
DAC 0
RF
Switch
RF
Switch
CLKSRC_SEL0
CLKSRC_SEL1
CLKSRC_SEL2
Π-attn
Figure 4: Clock tree
4.7.1 Control
The clock tree contains two RF switches (ADG918) and requires the following control signals
(driven from the CPLD):
CLKSRC_SEL0 connects the external clock input to the reference input of the
AD9517 or the 2nd RF switch.
CLKSRC_SEL1 connect either the onboard VCXO or the external clock to the clock
input of the AD9510. This signal also controls the VCXO power supply
2
.
CLKSRC_SEL2 enables/disables the onboard reference oscillator.
4.8 Multi-Gigabit Transceivers
Optionally, the FMC connector hosts 10 MGT pairs (10 Tx and 10 Rx pairs). These are
connected to two 38-pins MICTOR headers. The arrangement is such that different
interconnect topologies are supported;
2
The VCXO should be powered down to avoid interference with the external clock when external
clock is used.

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5Rx/5Tx
5Rx/5Tx
5Rx/5Tx
5Rx/5Tx
5Rx/5Tx 5Rx/5Tx 5Rx/5Tx 5Rx/5Tx 5Rx/5Tx 5Rx/5Tx
Figure 5: MGT interconnect topologies
FMC
20,32
10.00
7.12
13.71
FPGA
MICTOR 2
Rx-Tx 5-9
MICTOR 1
Rx-Tx 0-4
TOP VIEW
Figure 6: 4DSP CPCI board stack (slot-to-slot)

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MICTOR 1
MICTOR 2
Pin
Signal
Midplate
Signal
Pin
Pin
Signal
Midplate
Signal
Pin
1
GND
GND
GND
2
1
GND
GND
GND
2
3
TX0_P*
GND
RX0_P*
4
3
RX9_P
GND
TX9_P
4
5
TX0_N*
GND
RX0_N*
6
5
RX9_N
GND
TX9_N
6
7
GND
GND
GND
8
7
GND
GND
GND
8
9
TX1_P*
GND
RX1_P*
10
9
RX8_P
GND
TX8_P
10
11
TX1_N*
GND
RX1_N*
12
11
RX8_N
GND
TX8_N
12
13
GND
GND
GND
14
13
GND
GND
GND
14
15
TX2_P*
GND
RX2_P*
16
15
RX7_P
GND
TX7_P
16
17
TX2_N*
GND
RX2_N*
18
17
RX7_N
GND
TX7_N
18
19
GND
GND
GND
20
19
GND
GND
GND
20
21
TX3_P*
GND
RX3_P*
22
21
RX6_P
GND
TX6_P
22
23
TX3_N*
GND
RX3_N*
24
23
RX6_N
GND
TX6_N
24
25
GND
GND
GND
26
25
GND
GND
GND
26
27
TX4_P
GND
RX4_P
28
27
RX5_P
GND
TX5_P
28
29
TX4_N
GND
RX4_N
30
29
RX5_N
GND
TX5_N
30
31
GND
GND
GND
32
31
GND
GND
GND
32
33
IO0
GND
34
33
IO2
GND
34
35
IO1
GND
36
35
IO3
GND
36
37
GND
GND
GND
38
37
GND
GND
GND
38
Table 5: MGT connector pin out
3
A low phase noise 125MHz XTAL is used as reference clock. A 1:2 LVDS fan-out buffer is
used to feed to reference clock to both connections on the FMC connector.
The pairs marked with * connect to either the MICTOR header or the HDMI connector. The
assembly is determined with 0Ωresistors. A maximum of four pairs can connect to the HDMI
connector. Contact 4DSP for custom configurations.
N.B. These connectors are not available on the FMC204 revision 2.
4.9 Power supply
Power is supplied to the FMC204 card through the FMC connector. The pin current rating is
2.7A, but the overall maximum as specified by the FMC standard is limited according to
Table 6.
3
Signals IO[0:3] connects to the CPLD and has no defined function yet.

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Voltage
# pins
Max Amps
Max Watt
+3.3V
4
3 A
10 W
+12V
2
1 A
12 W
VADJ (+2.5V)
4
4 A
10 W
VIO_B (+2.5V)
2
1.15 A
2.3 W
Table 6: FMC standard power specification
The power provided by the carrier card can be very noisy. Special care is taken with the
power supply generation on the FMC204 card to minimize the effect of power supply noise
on clock generation and data conversion.
Clean analog supply is derived from +12V in two steps for maximum efficiency. The first step
uses a highly efficient switched regulator. The analog supply is derived from this power rail
with low dropout, low noise, high PSRR, and linear regulators. There is additional noise
filtering at several stages in the power supply.
The regulators have sufficient copper area to dissipate the heat in combination with proper
airflow (see section 6.3 Cooling).
Power plane
Typical
Maximum
VADJ
1050 mA
3P3V
105 mA
12P0V
320 mA
3P3VAUX (Operating)
3P3VAUX (Standby)
0.1 mA
0.01 µA
3 mA
1 µA
Table 7a: Typical/Maximum current drawn from FMC204 revision 1
Power plane
Typical
Maximum
VADJ
25 mA
3P3V
880mA
12P0V
320 mA
3P3VAUX (Operating)
3P3VAUX (Standby)
0.1 mA
0.01 µA
3 mA
1 µA
Table 7b: Typical/Maximum current drawn from FMC204 revision 2
The total power consumption is 6.5W.
4.10 Synchronizing multiple cards
Multiple cards can be synchronized if supplied with synchronized clock signals. An external
synchronization signal is also required to align the samples in the digital domain. Refer to
section 4.6 for details about synchronisation.

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FMC204
CLOCK
TRIGGER/SYNC
FMC204
CLOCK
TRIGGER/SYNC
FMC204
CLOCK
TRIGGER/SYNC
Clock generation Fs 50%
Fs/4 25%
Figure 7: Synchronizing multiple cards
5 Controlling the FMC204
5.1 Architecture
The FMC must be controlled from the carrier hardware through a single SPI communication
bus. The SPI communication bus is connected to a CPLD which has the following tasks:
Distribute SPI access from the carrier hardware along the local devices:
- 2x DAC5682Z (D/A converters)
- 1x AD9517 (Clock Tree)
Select clock source based on a SPI command from the carrier hardware
(CLKSRC_SEL).
Select sync source based on a SPI command from the carrier hardware
(SYNCSRC_SEL).
Generate SPI reset for AD9517 (CLK_N_RESET) and both DAC5682Z
(DAC_N_RESET)
Control the direction of the front I/O transceivers (FRONT_IO_DIR).
Control the FAN header power (FAN_N_EN).
Collect local status signals and store them in a register which can be accessed from
the carrier hardware.
Drive a LED according to the level of the status signals.

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CPLD
DAC0_N_CS
DAC1_N_CS
CLK_N_CS
SCLK
SDIO
CLKSRC_SEL[0:2]
SYNCSRC_SEL[0:1]
REFMON
LD
STATUS
VM_N_INT
AND
FMC_TO_CPLD(1)
N_CS
FMC_TO_CPLD(2)
SDIO
FMC_TO_CPLD(0)
SCLK
FMC Side
Local Side
LED
SRC_SEL
REG0
REG1
REG2
Shift register
FMC_TO_CPLD(3)
N_INT
Ctrl
CLK_N_RESET
DAC_N_RESET
FRONT_IO_DIR[0:3]
FAN_N_EN[0:3]
Figure 8: CPLD architecture
Notes:
SDO on the AD9517 and DAC5682Z devices is not connected. SDIO is used
bidirectional (3-wire SPI)
N_PD on the AD9517 is not connected.
N_SYNC on the AD9517 on the revision 1 boards is not connected. On revision 2
boards N_SYNC is connected to the CPLD for future use.
N_RESET on the both DAC5682Z devices is shared.
5.2 SPI Programming
The SPI programmable devices on the FMC204 can be accessed as described in their
datasheet, but each SPI communication cycle needs to be preceded with a preselection byte.
The preselection byte is used by the CPLD to forward the SPI command to the right
destination. The preselection bytes are defined as follows:
- CPLD 0x00
- DAC5682Z #1 0x82
- DAC5682Z #2 0x83
- AD9517 0x84
The CLPD has three internal registers which are described in Appendix B CPLD Register
map. The registers of the other devices are transparently mapped.

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8-bit pre-selection
P6 P5 P4 P3 P2 P1 P0 R/W A6 A5 A4 A3 A2 A1 A0
8-bit instruction 8-bit register data
D7 D6 D5 D4 D3 D3 D1 D0
N_CS
SCLK
SDIO P7
Figure 9: Write instruction to CPLD registers A1:A0
8-bit pre-selection
P6 P5 P4 P3 P2 P1 P0 R/W A6 A5 A4 A3 A2 A1 A0
8-bit instruction 8-bit register data
D7 D6 D5 D4 D3 D3 D1 D0
N_CS
SCLK
SDIO P7
Figure 10: Read instruction to CPLD registers A1:A0
8-bit pre-selection
P6 P5 P4 P3 P2 P1 P0 R/W N1 N0 A4 A3 A2 A1 A0
8-bit instruction 8-bit register data
D7 D6 D5 D4 D3 D3 D1 D0
N_CS
SCLK
SDIO P7
Figure 11: Write instruction to DAC5682Z registers A4:A0
8-bit pre-selection
P6 P5 P4 P3 P2 P1 P0 R/W N1 N0 A4 A3 A2 A1 A0
8-bit instruction 8-bit register data
D7 D6 D5 D4 D3 D3 D1 D0
N_CS
SCLK
SDIO P7
Figure 12: Read instruction to DAC5682Z registers A4:A0
8-bit pre-selection
P6 P5 P4 P3 P2 P1 P0 R/W W1 W0 A12 A11 A10 A9 A8
16-bit instruction 8-bit register data
N_CS
SCLK
SDIO P7 D7 D6 D5 D4 D3 D3 D1 D0A6 A5 A4 A3 A2 A1 A0A7
Figure 13: Write instruction to AD9517 registers A12:A0

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8-bit pre-selection
P6 P5 P4 P3 P2 P1 P0 R/W W1 W0 A12 A11 A10 A9 A8
16-bit instruction 8-bit register data
N_CS
SCLK
SDIO P7 D7 D6 D5 D4 D3 D3 D1 D0A6 A5 A4 A3 A2 A1 A0A7
Figure 14: Read instruction to AD9517 registers A12:A0
6 Environment
6.1 Temperature
Operating temperature:
-40°C to +85°C (Industrial)
Storage temperature:
-40°C to +120°C
6.2 Monitoring
The onboard monitoring may be used to monitor the voltage on the different power rails as
well as the ambient temperature around the monitoring device.
It is recommended that the carrier card and/or host software uses the power-down features if
the temperature is too high. Normal operations can resume once the temperature is within
the operating conditions boundaries.
Parameter:
Device 1
address 1001 000
Formula
On-chip temperature
On-chip AIN0 (VDD)
+3.3V
External AIN1
+3.3V Analog CLK
AIN1 * 2
External AIN2
+1.8V Digital
AIN2
External AIN3
VADJ
AIN3
External AIN4
+2.5V Analog CLK
AIN4
External AIN5
+3.3V Digital
AIN5 * 2
External AIN6
+3.3V
AIN6 * 2
External AIN7
+3.3V VCP
AIN7 * 2
External AIN8
+12V
AIN8 * 7.04
Table 8: Temperature and voltage parameters

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6.3 Cooling
Two different types of cooling are available for the FMC204.
6.3.1 Convection cooling
The air flow provided by the fans of the chassis the FMC204 is enclosed in will dissipate the
heat generated by the on board components. A minimum airflow of 300 LFM is
recommended.
Optionally, low profile FANs can be glued on top of the D/A devices. The card has a FAN
power connection that can be switched on and off under carrier card control (individually
driven from the CPLD).
For standalone operations (such as on a Xilinx development kit), it is highly recommended to
blow air across the FMC to ensure that the temperature of the devices is within the allowed
range. 4DSP’s warranty does not cover boards on which the maximum allowed temperature
has been exceeded.
6.3.2 Conduction cooling
In demanding environments, the ambient temperature inside a chassis could be close to the
operating temperature defined in this document. It is very likely that in these conditions the
junction temperature of power consuming devices will exceed the operating conditions
recommended by the device manufacturers (mostly +85°C).
The FMC204 is designed for maximum heat transfer to conduction-cooled ribs. A customized
cooling frame that connects directly to the surface of the D/A devices is allowed. This
conduction-cooling mechanism should be applied in combination with proper chassis air flow.
Contact 4DSP for detailed mechanical information.
7 Safety
This module presents no hazard to the user.
8 EMC
This module is designed to operate within an enclosed host system built to provide EMC
shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed
within an adequate host system. This module is protected from damage by fast voltage
transients originating from outside the host system which may be introduced through the
system.