Abatron bdiAccess BDI1000 User manual

bdi
RDI
JTAG debug interface for RDI compatible debuggers
ARM7 / ARM9
User Manual
Manual Version 1.10 for BDI1000
© 1999-2003 ABATRON AG

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 2
© Copyright 1999-2003 by ABATRON AG V 1.10
1 Introduction .................................................................................................................................3
1.1 BDI1000.................................................................................................................................3
2 Installation ...................................................................................................................................4
2.1 Connecting the BDI1000 to Target.........................................................................................4
2.1.1 Changing Target Processor Type .................................................................................6
2.1.2 Adaptive Clocking.........................................................................................................7
2.2 Connecting the BDI1000 to Power Supply.............................................................................9
2.2.1 External Power Supply.................................................................................................9
2.2.2 Power Supply from Target System.............................................................................10
2.3 Status LED «MODE»...........................................................................................................11
2.4 Connecting the BDI1000 to Host.........................................................................................12
2.4.1 Serial line communication..........................................................................................12
2.4.2 Ethernet communication ............................................................................................13
2.5 Installation of the Configuration Software............................................................................14
2.6 Configuration .......................................................................................................................15
2.6.1 BDI1000 Setup/Update..............................................................................................15
3 Init List........................................................................................................................................17
3.1 Init CP15 Registers..............................................................................................................19
4 BDI working modes...................................................................................................................21
4.1 Startup Mode.......................................................................................................................23
4.1.1 Startup mode RESET ................................................................................................23
4.1.2 Startup Mode STOP...................................................................................................23
4.1.3 Startup mode RUN.....................................................................................................23
5 Working with RDI Debuggers ...................................................................................................24
5.1 ADW/AXD from ARM Ltd.....................................................................................................24
5.1.1 Configuration..............................................................................................................24
5.1.2 Implementation notes.................................................................................................25
5.2 BDI Direct Commands.........................................................................................................26
5.2.1 Target.Reset...............................................................................................................26
5.2.2 Flash.Setup................................................................................................................27
5.2.3 Flash.Erase................................................................................................................28
5.2.4 Flash.Load .................................................................................................................28
5.2.5 Flash.Idle....................................................................................................................28
5.3 Download to Flash Memory.................................................................................................29
6 Telnet Interface ..........................................................................................................................31
7 Specifications............................................................................................................................32
8 Environmental notice................................................................................................................33
9 Declaration of Conformity (CE)................................................................................................33
10 Warranty...................................................................................................................................34
Appendices
A Troubleshooting........................................................................................................................35
B Maintenance..............................................................................................................................36
C Trademarks................................................................................................................................38

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 3
© Copyright 1999-2003 by ABATRON AG V 1.10
1 Introduction
The BDI1000 adds JTAG based debugging to RDI compatible debuggers (e.g.ADW from ARM Ldt).
With the BDI1000, you control and monitor the microcontroller solely through the stable on-chip de-
bugging services.You won’t waste time and target resources with a software ROM monitor, and you
eliminate the cabling problems typical of ICE’s.This combination runs even when the target system
crashes and allows developers to continue investigating the cause of the crash. A RS232 interface
with a maximum of 115 kBaud and a 10Base-T Ethernet interface is available for the host interface.
The configuration software is used to update the firmware and to configure the BDI1000 so it works
with the RDI compatible debugger.
1.1 BDI1000
The BDI1000 is a processor system in a small box. It implements the interface between the JTAG
pins of the target CPU and a 10Base-T Ethernet / RS232 connector. BDI1000 is powered by a
MC68331, 256Kbyte RAM and a flash memory of 512Kbyte.As a result of consistent implementation
of lasted technology, the BDI1000 is optimally prepared for further enhancements.The firmware and
the programmable logic of the BDI1000 can be updated by the user with a simple Windows based
configuration program.The BDI1000 supports target system voltages from 1.8 up to 5 Volts.
PC Host
RDI
Debugger
BDI1000
AA
AAbb bbaa aattttrr rroo oonn nn AA AAGG GG SS
SSww wwiiiiss ssss ss MM MMaa aadd ddeeee
Target System
JTAG Interface
Ethernet (10 BASE-T)
BDI1000
AA
AAbb bbaa aattttrr rroo oonn nn AA AAGG GG SS
SSww wwiiiiss ssss ss MM MMaa aadd ddeeee
Target System
JTAG Interface
RS232
ARM ARM

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 4
© Copyright 1999-2003 by ABATRON AG V 1.10
2 Installation
2.1 Connecting the BDI1000 toTarget
The enclosed cables to the target system are designed for the ARM Development Boards. In case
where the target system has the same connector layout, the cable (14 pin or 20 pin) can be directly
connected.
In order to ensure reliable operation of the BDI (EMC, runtimes, etc.) the target cable length must not
exceed 20 cm (8").
TARGET A connector signals see table on next page.
!
BDI1000
AA
AAbb bbaa aattttrr rroo oonn nn AA AAGG GG SS
SSww wwiiiiss ssss ss MM MMaa aadd ddeeee
Target System
ARM 1 13
14
2
The green LED «TRGT» marked light up when target is powered up
14 pinTarget
Connector
1 - Vcc Target
2 - GROUND
3 - TRST
4 - GROUND
5 - TDI
6 - NC
7 - TMS
8 - NC
9 - TCK
10 - NC
11 - TDO
12 - RESET
13 - NC
14 - NC
1 - Vcc Target
2 - NC
3 - TRST
4 - NC
5 - TDI
6 - NC
7 - TMS
8 - GROUND
9 - TCK
10 - GROUND
11 - NC
12 - NC
13 - TDO
14 - NC
15 - RESET
16 - NC
17 - NC
18 - NC
19 - NC
20 - NC
20 pin Multi-ICE
Connector
1 19
20
2
BDI TARGET A TARGET B
9 1
10 2
BDI TRGT
MODE

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 5
© Copyright 1999-2003 by ABATRON AG V 1.10
TARGET A Connector Signals
The BDI1000 works also with targets which have no dedicatedTRST pin.For this kind of targets, the
BDI cannot force the target to debug mode immediately after reset.The target always begins execu-
tion of application code until the BDI has finished programming the Debug Control Register.
Pin Name Describtion
1 reserved This pin is currently not used.
2 TRST JTAGTest Reset
This open-drain / push-pull output of the BDI1000 resets the JTAG TAP controller on the
target. Default driver type is open-drain.
3+5 GND System Ground
4 TCK JTAGTest Clock
This output of the BDI1000 connects to the target TCK line.
6 TMS JTAGTest Mode Select
This output of the BDI1000 connects to the target TMS line.
7 RESET This open collector output of the BDI1000 is used to reset the target system.
8 TDI JTAGTest Data In
This output of the BDI1000 connects to the target TDI line.
9 Vcc Target 1.8 – 5.0V:
This is the target reference voltage.It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators.It also controls the output logic
levels to the target.It is normally connected toVdd I/O on the target board.
10 TDO JTAGTest Data Out
This input to the BDI1000 connects to the target TDO line.

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 6
© Copyright 1999-2003 by ABATRON AG V 1.10
2.1.1 ChangingTarget ProcessorType
Before you can use the BDI1000 with an other target processor type (e.g. ARM <--> PPC), a new
setup has to be done (see chapter 2.6 «Configuration»). During this process the target cable must
be disconnected from the target system.The BDI1000 needs to be supplied between 2.5V and 5V
via the POWER connector. For more information see chapter 2.2.1 «External Power Supply».
To avoid data line conflicts, the BDI1000 must be disconnected from the target system while
programming the logic for an other target CPU.
!

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 7
© Copyright 1999-2003 by ABATRON AG V 1.10
2.1.2 Adaptive Clocking
Adaptive clocking is a feature which ensures that the BDI1000 never loses synchronization with the
target device, whatever the target clock speed is.To achieve this, BDI1000 uses two signalsTCK and
RTCK.When adaptive clocking is selected, BDI1000 issues a TCK signal and waits for the Returned
TCK (RTCK) to come back. BDI1000 does not progress to the next TCK until RTCK is received. For
more information about adaptive clocking see ARM documentation.
Note :
Adaptive clocking is only supported with a special target cable. This special cable can be ordered
separately from Abatron.
For TARGET B connector signals see table on next page.
The green LED «TRGT» marked light up when target is powered up
1 - Vcc Target
2 - NC
3 - TRST
4 - NC
5 - TDI
6 - NC
7 - TMS
8 - GROUND
9 - TCK
10 - GROUND
11 - RTCK
12 - NC
13 - TDO
14 - NC
15 - RESET
16 - NC
17 - NC
18 - NC
19 - NC
20 - NC
20 pin Multi-ICE
Connector
1 19
20
2
BDI1000
AA
AAbb bbaa aattttrr rroo oonn nn AA AAGG GG SS
SSww wwiiiiss ssss ss MM MMaa aadd ddeeee
Target System
ARM
BDI TRGT
MODE
15 1
16 2
I TARGET A TARGET B

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 8
© Copyright 1999-2003 by ABATRON AG V 1.10
BDITARGET B Connector Signals:
Pin Name Describtion
1 TDO JTAGTest Data Out
This input to the BDI1000 connects to the target TDO line.
2 reserved
3 TDI JTAGTest Data In
This output of the BDI1000 connects to the target TDI line.
4 reserved
5RTCK Returned JTAGTest Clock
This input to the BDI1000 connects to the target RTCK line.
6 Vcc Target 1.8 – 5.0V:
This is the target reference voltage.It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators.It also controls the output logic
levels to the target.It is normally connected toVdd I/O on the target board.
7 TCK JTAGTest Clock
This output of the BDI1000 connects to the target TCK line.
8 TRST
JTAGTest Reset
This open-drain / push-pull output of the BDI1000 resets the JTAG TAP controller on the
target. Default driver type is open-drain.
9 TMS JTAGTest Mode Select
This output of the BDI1000 connects to the target TMS line.
10 reserved
11 reserved
12 GROUND System Ground
13 RESET
System Reset
This open collector output of the BDI1000 is used to reset the target system.
14 reseved
15 reseved
16 GROUND System Ground

bdi
RDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 9
© Copyright 1999-2003 by ABATRON AG V 1.10
2.2 Connecting the BDI1000 to Power Supply
2.2.1 External Power Supply
The BDI1000 needs to be supplied between 2.5V and 5V via the POWER connector.The available
power supply from Abatron (option) or the enclosed power cable can be directly connected.In order
to ensure reliable operation of the BDI1000, keep the power supply cable as short as possible.
For error-free operation, the power supply to the BDI1000 must be between 2.5V and 5V DC.The
maximal tolerable supply voltage is 5.25 VDC. Any higher voltage or a wrong polarity might
destroy the electronics.
Please switch on the system in the following sequence:
• 1 --> external power supply
• 2 --> target system
!
POWER Connector
1 - Vcc (+2.5 ...+5V)
2 - VccTGT
3 - GROUND
4 - NOT USED
The green LED «BDI» marked light up when power (2.5 – 5V) is connected to the BDI1000
RS232 LI POWER 10 BASE-T
1 Vcc
2
GND 3
4
TARGET A TARGET B
BDI TRGT
MODE

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 10
© Copyright 1999-2003 by ABATRON AG V 1.10
2.2.2 Power Supply fromTarget System
The BDI1000 needs to be supplied between 2.5V and 5V via TARGET A connector.This mode can
only be used when the target system runs between 2.5V and 5V and the pin «Vcc Target» is able to
deliver a current up to:
• [email protected] Target
• [email protected] Target
• [email protected] Target
For pin description and layout see chapter 2.1 «Connecting the BDI1000 to Target». Insert the en-
closed Jumper as shown in figure below. Please ensure that the jumper is inserted correctly.
For error-free operation, the power supply to the BDI1000 must be between 2.5V and 5V DC.The
maximal tolerable supply voltage is 5.25 VDC. Any higher voltage or a wrong polarity might
destroy the electronics.
!
POWER Connetcor
1 - Vcc BDI1000 (+2.5 ...+5V)
2 - Vcc Target (+2.5 ... +5V)
3 - GROUND
4 - NOT USED
The green LEDs «BDI» and «TRGT» marked light up when target is powered up
and the jumper is inserted correctly
RS232 LI POWER 10 BASE-T
1
2
3
4
TARGET A TARGET B
BDI TRGT
MODE
Jumper
359
1 - Reserved
2 - TRST
3 - GROUND
4 - TCK
5 - GROUND
6 - TMS
7 - RESET
8 - TDI
9 - Vcc Target
10 - TDO
Target A Connector

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 11
© Copyright 1999-2003 by ABATRON AG V 1.10
2.3 Status LED «MODE»
The built in LED indicates the following BDI states:
MODE LED BDI STATES
OFF The BDI is ready for use, the firmware is already loaded.
ON The power supply for the BDI1000 is < 2.5VDC.
BLINK The BDI «loader mode» is active (an invalid firmware is loaded or loading firmware is active).
TARGET A TARGET B
BDI TRGT
MODE

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 12
© Copyright 1999-2003 by ABATRON AG V 1.10
2.4 Connecting the BDI1000 to Host
2.4.1 Serial line communication
The host is connected to the BDI through the serial interface (COM1...COM4).The communication
cable between BDI and Host is a serial cable (RXD / TXD are crossed).There is the same connector
pinout for the BDI and for the Host side (Refer to Figure below).
RS232 Connector
(for PC host)
BDI1000
AA
AAbb bbaa aattttrr rroo oonn nn AA AAGG GG SS
SSww wwiiiiss ssss ss MM MMaa aadd ddeeee
Target System
RS232
PC Host
1 - NC
2 - RXD data from host
3 - TXD data to host
4 - NC
5 - GROUND
6 - NC
7 - NC
8 - NC
9 - NC
RS232 LI POWER 10 BASE-T
54321
9876
ARM

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 13
© Copyright 1999-2003 by ABATRON AG V 1.10
2.4.2 Ethernet communication
The BDI1000 has a built-in 10 BASE-T Ethernet interface (see figure below). Connect an UTP (Un-
shilded Twisted Pair) cable to the BD1000. For thin Ethernet coaxial networks you can connect a
commercially available media converter (BNC --> 10 BASE-T) between your network and the
BDI1000. Contact your network administrator if you have questions about the network.
10 BASE-T
PC Host
Target System
Ethernet (10 BASE-T)
1 - TD+
2 - TD-
3 - RD+
4 - NC
5 - NC
6 - RD-
7 - NC
8 - NC
Connector
BDI1000
AA
AAbb bbaa aattttrr rroo oonn nn AA AAGG GG SS
SSww wwiiiiss ssss ss MM MMaa aadd ddeeee
RS232 LI POWER 10 BASE-T
18
When the LI LED light is ON, data link is successful between the
UTP
port of the BDI1000 and the hub to which it is connected.
ARM

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 14
© Copyright 1999-2003 by ABATRON AG V 1.10
2.5 Installation of the Configuration Software
On the enclosed diskette you will find the BDI configuration software and the firmware required for
the BDI. Copy all these files to a directory on your hard disk.
The following files are on the diskette:
b10arm.exe Configuration program
b10arm.hlp Helpfile for the configuration program
b10arm.cnt Help contents file
b10armfw.xxx Firmware for BDI1000 for ARM targets
armjed10.xxx JEDEC file for the BDI logic device programming
bdiifc32.dll BDI Interface DLL for configuration program
bdirdi.dll RDI Interface DLL
*.bdi Configuration Examples
Example of an installation process:
• Copy the entire contents of the enclosed diskette into a directory on the hard disk.
•You may create a new shortcut to the b10arm.exe configuration program.
• The RDI interface DLL has to copied to the appropriate debugger directory

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 15
© Copyright 1999-2003 by ABATRON AG V 1.10
2.6 Configuration
Before you can use the BDI together with the debugger, the BDI must be configured.Use the SETUP
menu and follow the steps listed below:
• Load or update the firmware / logic, store IP address --> Firmware
• Set the communication parameters between Host and BDI --> Communication
• Setup an initialization list for the target processor --> Initlist
• Select the working mode --> Mode
• Transmit the configuration to the BDI --> Mode Transmit
For information about the dialogs and menus use the help system (F1).
2.6.1 BDI1000 Setup/Update
First make sure that the BDI is properly connected (see Chapter 2.1 to 2.4).The BDI must be con-
nected via RS232 to the Windows host.
To avoid data line conflicts, the BDI1000 must be disconnected from the target system while
programming the logic for an other target CPU (see Chapter 2.1.1).
The following dialogbox is used to check or update the BDI firmware and logic and to set the network
parameters.
dialog box «BDI1000 Update/Setup»
The following options allow you to check or update the BDI firmware and logic and to set the network
parameters:
Channel Select the communication port where the BDI1000 is connected during
this setup session.
Baudrate Select the baudrate used to communicate with the BDI1000 loader during
this setup session.
!

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 16
© Copyright 1999-2003 by ABATRON AG V 1.10
Connect Click on this button to establish a connection with the BDI1000 loader.
Once connected, the BDI1000 remains in loader mode until it is restarted
or this dialog box is closed.
Current Press this button to read back the current loaded BDI1000 software and
logic versions.The current loader, firmware and logic version will be dis-
played.
Update This button is only active if there is a newer firmware or logic version
present in the execution directory of the BDI setup software. Press this
button to write the new firmware and/or logic into the BDI1000 flash mem-
ory / programmable logic.
IP Address Enter the IP address for the BDI1000.
Use the following format:xxx.xxx.xxx.xxxe.g.151.120.25.101
Ask your network administrator for assigning an IP address to this
BDI1000. Every BDI1000 in your network needs a different IP address.
Subnet Mask Enter the subnet mask of the network where the BDI is connected to.
Use the following format:xxx.xxx.xxx.xxxe.g.255.255.255.0
A subnet mask of 255.255.255.255 disables the gateway feature.
Ask your network administrator for the correct subnet mask.
Default Gateway Enter the IP address of the default gateway.Ask your network administra-
tor for the correct gateway IP address. If the gateway feature is disabled,
you may enter 255.255.255.255 or any other value..
Transmit Click on this button to store the network configuration in the BDI1000 flash
memory.
In rare instances you may not be able to load the firmware in spite of a correctly connected BDI (error
of the previous firmware in the flash memory).Before carrying out the following procedure,check
the possibilities in Appendix «Troubleshooting». In case you do not have any success with the
tips there, do the following:
• Switch OFF the power supply for the BDI and open the unit as
described in Appendix «Maintenance»
• Place the jumper in the «INIT MODE» position
• Connect the power cable or target cable if the BDI is powered
from target system
• Switch ON the power supply for the BDI again and wait until the
LED «MODE» blinks fast
• Turn the power supply OFF again
• Return the jumper to the «DEFAULT» position
• Reassemble the unit as described in Appendix «Maintenance»
INIT MODE
DEFAULT
Jumper

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 17
© Copyright 1999-2003 by ABATRON AG V 1.10
3 Init List
dialog box «Startup Init List»
In order to prepare the target for debugging, you can define an Initialization List.This list is stored in
the Flash memory of the BDI1000 and worked through every time the target comes out of reset.Use
it to get the target operational after a reset.The memory system is usually initialized through this list.
After processing the init list, the RAM used to download the application must be accessible.
Use on-line help (F1) and the supplied configuration examples on the distribution disk to get more
information about the init list.

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 18
© Copyright 1999-2003 by ABATRON AG V 1.10
Special BDI Configuration Registers:
In order to change some special configuration parameters of the BDI, the GPR entry in the init list is
used. Normal ARM GPR's covers a range from 0 to 15. Other GPR's are used to set BDI internal
registers:
8005 This entry in the init list allows to change the JTAG clock frequency.This is useful if you have
to start with a slow JTAG clock out of reset but after some initialization (e.g.PLL setup) you
can use a faster clock.As an example see AT91EB55 setup.The value you enter selects the
following JTAG frequency:
0 = adaptive 5 = 200 kHz
1 = 6 MHz 6 = 100 kHz
2 = 3 MHz 7 = 50 kHz
3 = 1 MHz 8 = 20 kHz
4 = 500 kHz 9 = 10 kHz
8006 This entry in the init list allows to define a delay time (in ms) the BDI inserts between releas-
ing the reset line and starting communicating with the target.This delay is necessary when
a target needs some wake-up time after a reset (e.g. Cirrus EP7209).
8007 By default, the BDI asserts the RESET signal during reset processing.After writing zero to
this special register, the BDI no longer drives RESET low.This may be useful in some spe-
cial cases.
8008 During JTAG debugging, the PC increments while the BDI stuffs instruction into the ARM
core.It may be necessary to set the PC to a safe non-vector address before external mem-
ory is accessed to prevent pre-fetching code from an invalid address range. Enter a safe
non-vector address for the PC into this special BDI registers..
8009 By default, the TRST signal is driven with an open-drain driver by the BDI.Write a 1 to this
special BDI register if the TRST signal should be driven with a push-pull driver.
8010 Bydefault,onARM7 based targetsthe BDIuses a softwarebreakpointto supportsemihost-
ing. In cases where the vector table is allocated to ROM, write a 1 to this special BDI regis-
ters to force the use of a hardware breakpoint.This does not apply to ARM9 targets because
on ARM9 there exists a special vector catch feature.
8012 This entry in the init list allows to define a time (in ms) the BDI asserts the hardware reset
signal. By default the reset signal is asserted for about 3 ms.
8013 With this entry the MAC7100 "JTAG lockout recovery" can be activated. As value enter the
correct CMF clock divider (CMFCLKD). Calculate this value based on the reset frequency,
the frequency that is active before any init list entry is processed (PLL is not active). If for
example the system clockis8 MHz, the clockinput to the flash is 4MHz andthe correctvalue
for CFMCKLD is 19 (0x13).If this entry is present, the BDI automatically recovers a secured
flash as part of the next reset sequence.

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 19
© Copyright 1999-2003 by ABATRON AG V 1.10
3.1 Init CP15 Registers
Via the Initialization List it is possible to setup the Coprocessor 15 (CP15) registers.The address part
of a WCP15 init list entry uses a special format which depends on the used CPU type.
ARM710T, ARM720T,ARM740T:
The 16bit register number is used to build the appropriate MCR/MRC instruction to access the CP15
register.
+-----+-+-------+-------+-------+
|opc_2|0| CRm |0 0 0 0| nbr |
+-----+-+-------+-------+-------+
Normally opc_2 and CRm are zero and therefore you can simply enter the CP15 register number.
WCP15 0x0002 0x00004000 MMU: set Translation Base Address
ARM920T:
Via JTAG, CP15 registers are accessed either direct (physical access mode) or via interpreted MCR/
MRC instructions. Read also ARM920T manual, part "Debug Support - Scan Chain 15".
Register number for physical access mode (bit 12 = 0):
+-----+-+-----+-+-----+-+-------+
|0 0 0|0|0 0 0|i|0 0 0|x| nbr |
+-----+-+-----+-+-----+-+-------+
The bit "i" selects the instruction cache (scan chain bit 33), the bit "x" extends access to register 15
(scan chain bit 38).
Register number for interpreted access mode (bit 12 = 1):
+-----+-+-------+-----+-+-------+
|opc_2|1| CRm |opc_1|0| nbr |
+-----+-+-------+-----+-+-------+
The 16bit register number is used to build the appropriate MCR/MRC instruction.
ARM940T, ARM946E, ARM966E:
The CP15 registers are directly accessed via JTAG.
+-----+-+-----+-+-----+-+-------+
|0 0 0|0|0 0 0|i|0 0 0|x| nbr |
+-----+-+-----+-+-----+-+-------+
The bit "i" selects the instruction cache (scan chain bit 32), the bit "x" extends access to register 6
(scan chain bit 37).
WCP15 0x0005 0x0000000F data region 0/1 full access
WCP15 0x0105 0x0000000F inst region 0/1 full access
WCP15 0x0001 0x0000107D enable protection and caches

bdiRDI JTAG interface for RDI Debuggers, BDI1000 User Manual 20
© Copyright 1999-2003 by ABATRON AG V 1.10
ARM926E:
The 16bit register number contains the fields of the appropriate MCR/MRC instruction that would be
used to access the CP15 register.
+-+-----+-+-----+-------+-------+
|-|opc_1|-|opc_2| CRm | nbr |
+-+-----+-+-----+-------+-------+
Normallyopc_1,opc_2and CRm arezeroand thereforeyoucansimplyenter the CP15register num-
ber.
TI925T:
The CP15 registers are directly accessed via JTAG.
The following table shows the numbers used to access the CP15 registers and functions.
0 (or 0x30) : ID
1 (or 0x31) : Control
2 (or 0x32) : Translation table base
3 (or 0x33) : Domain access control
5 (or 0x35) : Fault status
6 (or 0x36) : Fault address
8 (or 0x38) : Cache information
13 (or 0x3d) : Process ID
0x10 : TI925T Status
0x11 : TI925T Configuration
0x12 : TI925T I-max
0x13 : TI925T I-min
0x14 : TI925T Thread ID
0x18 : Flush I+D TLB
0x19 : Flush I TLB
0x1a : Flush I TLB entry
0x1b : Flush D TLB
0x1c : Flush D TLB entry
0x20 : Flush I cache
0x22 : Flush I cache entry
0x23 : Flush D cache
0x24 : Flush D cache entry address
0x25 : Clean D cache entry address
0x26 : Clean + Flush D cache entry address
0x27 : Flush D cache entry index
0x28 : Clean D cache entry index
0x29 : Clean + Flush D cache entry index
0x2a : Clean D cache
0x2b : Drain Write buffer
0x37 : I cache TLB Lock-Down
0x3a : D cache TLB Lock-Down