Abatron bdiGDB User manual

bdiGDB
JTAG debug interface for GNU Debugger
ARM11 / Cortex
User Manual
Manual Version 1.21 for BDI2000
©1997-2014 by Abatron AG

bdiGDBfor GNU Debugger, BDI2000 (ARM11 / Cortex) User Manual 2
© Copyright 1997-2014 by ABATRON AG Switzerland V 1.21
1 Introduction ................................................................................................................................. 4
1.1 BDI2000................................................................................................................................. 4
1.2 BDI Configuration ..................................................................................................................5
2 Installation ................................................................................................................................... 6
2.1 Connecting the BDI2000 to Target ........................................................................................6
2.1.1 Changing Target Processor Type ................................................................................8
2.1.2 Adaptive Clocking ........................................................................................................8
2.1.3 Serial Wire Debug ......................................................................................................10
2.2 Connecting the BDI2000 to Power Supply .......................................................................... 11
2.3 Status LED «MODE»...........................................................................................................12
2.4 Connecting the BDI2000 to Host .........................................................................................13
2.4.1 Serial line communication ..........................................................................................13
2.4.2 Ethernet communication ............................................................................................14
2.5 Installation of the Configuration Software............................................................................15
2.5.1 Configuration with a Linux / Unix host........................................................................16
2.5.2 Configuration with a Windows host ............................................................................18
2.5.3 Recover procedure.....................................................................................................19
2.6 Testing the BDI2000 to host connection..............................................................................20
2.7 TFTP server for Windows....................................................................................................20
3 Using bdiGDB ............................................................................................................................ 21
3.1 Principle of operation...........................................................................................................21
3.2 Configuration File.................................................................................................................21
3.2.1 Part [INIT]...................................................................................................................22
3.2.2 Part [TARGET] ...........................................................................................................25
3.2.3 Part [HOST]................................................................................................................ 31
3.2.4 Part [FLASH] ..............................................................................................................33
3.2.5 Part [REGS] ...............................................................................................................41
3.3 Debugging with GDB ...........................................................................................................43
3.3.1 Target setup ...............................................................................................................43
3.3.2 Connecting to the target.............................................................................................43
3.3.3 Breakpoint Handling...................................................................................................44
3.3.4 GDB monitor command..............................................................................................44
3.3.5 Target serial I/O via BDI.............................................................................................45
3.3.6 Target DCC I/O via BDI..............................................................................................46
3.3.7 Target Serial Wire Output via BDI..............................................................................47
3.4 Telnet Interface....................................................................................................................48
3.4.1 Command list .............................................................................................................49
3.4.2 CPxx Registers ..........................................................................................................51
3.5 Multi-Core Support...............................................................................................................52
4 Specifications ............................................................................................................................ 55
5 Environmental notice................................................................................................................ 56
6 Declaration of Conformity (CE)................................................................................................ 56
7 Abatron Warranty and Support Terms .................................................................................... 57
7.1 Hardware ............................................................................................................................. 57
7.2 Software .............................................................................................................................. 57
7.3 Warranty and Disclaimer .....................................................................................................57
7.4 Limitation of Liability ............................................................................................................57

bdiGDBfor GNU Debugger, BDI2000 (ARM11 / Cortex) User Manual 3
© Copyright 1997-2014 by ABATRON AG Switzerland V 1.21
Appendices
A Troubleshooting ....................................................................................................................... 58
B Maintenance .............................................................................................................................. 59
C Trademarks ............................................................................................................................... 60

bdiGDBfor GNU Debugger, BDI2000 (ARM11 / Cortex) User Manual 4
© Copyright 1997-2014 by ABATRON AG Switzerland V 1.21
1 Introduction
bdiGDB enhances the GNU debugger (GDB), with JTAG debugging for ARM11 and Cortex based
targets. With the builtin Ethernet interface you get a very fast download speed of up to 200 Kbytes/
sec. No target communication channel (e.g. serial line) is wasted for debugging purposes. Even bet-
ter, you can use fast Ethernet debugging with target systems without network capability. The host to
BDI communication uses the standard GDB remote protocol.
An additional Telnet interface is available for special debug tasks (e.g. force a hardware reset,
program flash memory).
The following figure shows how the BDI2000 interface is connected between the host and the target:
1.1 BDI2000
The BDI2000 is the main part of the bdiGDB system. This small box implements the interface be-
tween the JTAG pins of the target CPU and a 10Base-T ethernet connector. The firmware and the
programable logic of the BDI2000 can be updated by the user with a simple Windows / Linux config-
uration program. The BDI2000 supports 1.8 – 5.0 Volts target systems (3.0 – 5.0 Volts target systems
with Rev. A/B).
.
GNU Debugger
(GDB)
BDI2000
Target System
Ethernet (10 BASE-T)
ARM
Unix / PC Host

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© Copyright 1997-2014 by ABATRON AG Switzerland V 1.21
1.2 BDI Configuration
As an initial setup, the IP address of the BDI2000, the IP address of the host with the configuration
file and the name of the configuration file is stored within the flash of the BDI2000.
Every time the BDI2000 is powered on, it reads the configuration file via TFTP.
Following an example of a typical configuration file:
; bdiGDB configuration for ARM Integrator CM1136JF-S
; --------------------------------------------------
;
[INIT]
WM32 0x1000000C 0x00000005 ;REMAP=1, MISC LED ON
;
[TARGET]
CPUTYPE ARM1136
CLOCK 1 ;JTAG clock (0=Adaptive,1=16MHz,2=8MHz,3=4MHz, ...)
POWERUP 3000 ;start delay after power-up detected in ms
ENDIAN LITTLE ;memory model (LITTLE | BIG)
VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset
BREAKMODE HARD ;SOFT or HARD
;
SCANPRED 0 0 ;no JTAG devices before the ARM1136
SCANSUCC 1 4 ;the ETMBUF after the ARM1136 core
;
[HOST]
IP 151.120.25.119
FILE E:\cygwin\home\demo\pid7t\fibo.x
FORMAT ELF
LOAD MANUAL ;load file MANUAL or AUTO after reset
[FLASH]
WORKSPACE 0x00001000 ;workspace in target RAM for fast programming algorithm
CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE 0x100000 ;The size of one flash chip in bytes
BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE $arm1136.cfg
FORMAT BIN 0x00010000
[REGS]
FILE $reg1136.def
Based on the information in the configuration file, the target is automatically initialized after every re-
set.

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© Copyright 1997-2014 by ABATRON AG Switzerland V 1.21
2 Installation
2.1 Connecting the BDI2000 to Target
The enclosed cables to the target system are designed for the ARM Development Boards. In case
where the target system has the same connector layout, the cable can be directly connected (14-pin
EmbeddedICE or 20-pin Multi-ICE).
In order to ensure reliable operation of the BDI (EMC, runtimes, etc.) the target cable length must not
exceed 20 cm (8").
For BDI MAIN / TARGET A connector signals see table on next page.
!
BDI TRGT MODE BDI MAIN BDI OPTION
14 pin EmbeddedICE
BDI2000
Target System
ARM
9
1
13
14
2
1
10 2
The green LED «TRGT» marked light up when target is powered up
Rev. A 1
19
20
2
Connector
1 - Vcc Target
2 - NC
3 - TRST
4 - NC
5 - TDI
6 - NC
7 - TMS
8 - GROUND
9 - TCK
10 - GROUND
11 - NC
12 - NC
13 - TDO
14 - NC
15 - RESET
16 - NC
17 - NC
18 - NC
19 - NC
20 - NC
1 - Vcc Target
2 - GROUND
3 - TRST
4 - GROUND
5 - TDI
6 - NC
7 - TMS
8 - NC
9 - TCK
10 - NC
11 - TDO
12 - RESET
13 - NC
14 - NC
20 pin Multi-ICE
Connector
BDI2000
Target System
ARM 1
13
14
2
The green LED «TRGT» marked light up when target is powered up
BDI TRGT MODE TARGET A TARGET B
9 1
10 2
Rev. B/C
14 pin EmbeddedICE
Connector
1 - Vcc Target
2 - GROUND
3 - TRST
4 - GROUND
5 - TDI
6 - NC
7 - TMS
8 - NC
9 - TCK
10 - NC
11 - TDO
12 - RESET
13 - NC
14 - NC
1 - Vcc Target
2 - NC
3 - TRST
4 - NC
5 - TDI
6 - NC
7 - TMS
8 - GROUND
9 - TCK
10 - GROUND
11 - NC
12 - NC
13 - TDO
14 - NC
15 - RESET
16 - NC
17 - NC
18 - NC
19 - NC
20 - NC
20 pin Multi-ICE
Connector
1
19
20
2

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© Copyright 1997-2014 by ABATRON AG Switzerland V 1.21
BDI MAIN / TARGET A Connector Signals
The BDI2000 works also with targets which have no dedicated TRST pin. For this kind of targets, the
BDI cannot force the target to debug mode immediately after reset. The target always begins execu-
tion of application code until the BDI has finished programming the Debug Control Register.
Note:
For targets with a 10-pin or 20-pin Cortex Debug Connector (Samtec 0.05" micro header) a special
adapter is available. This Cortex Adapter can be ordered separately from Abatron (p/n 90085).
For targets with a 14-Pin TI connector, a special cable is available. This cable can be ordered sep-
arately from Abatron (p/n 90053).
Pin Name Describtion
1 reserved This pin is currently not used.
2TRST JTAG Test Reset
This open-drain / push-pull output of the BDI2000 resets the JTAG TAP controller on the
target. Default driver type is open-drain.
3+5 GND System Ground
4 TCK JTAG Test Clock
This output of the BDI2000 connects to the target TCK line.
6 TMS JTAG Test Mode Select
This output of the BDI2000 connects to the target TMS line.
7RESET This open collector output of the BDI2000 is used to reset the target system.
8 TDI JTAG Test Data In
This output of the BDI2000 connects to the target TDI line.
9 Vcc Target 1.8 – 5.0V:
This is the target reference voltage. It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators. It also controls the output logic
levels to the target. It is normally fed from Vdd I/O on the target board.
3.0 – 5.0V with Rev. A/B :
This input to the BDI2000 is used to detect if the target is powered up. If there is a current
limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
10 TDO JTAG Test Data Out
This input to the BDI2000 connects to the target TDO line.

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2.1.1 Changing Target Processor Type
Before you can use the BDI2000 with an other target processor type (e.g. ARM <--> PPC), a new
setup has to be done (see chapter 2.5). During this process the target cable must be disconnected
from the target system. The BDI2000 needs to be supplied with 5 Volts via the BDI OPTION connec-
tor (Rev. A) or via the POWER connector (Rev. B/C). For more information see chapter 2.2.1
«External Power Supply»).
To avoid data line conflicts, the BDI2000 must be disconnected from the target system while
programming the logic for an other target CPU.
2.1.2 Adaptive Clocking
Adaptive clocking is a feature which ensures that the BDI2000 never loses synchronization with the
target device, whatever the target clock speed is. To achieve this, BDI2000 uses two signals TCK
and RTCK. When adaptive clocking is selected, BDI2000 issues a TCK signal and waits for the Re-
turned TCK (RTCK) to come back. BDI2000 does not progress to the next TCK until RTCK is re-
ceived. For more information about adaptive clocking see ARM documentation.
Note:
Adaptive clocking is only supported with BDI2000 Rev.B/C and a special target cable. This special
cable can be ordered separately from Abatron (p/n 90052).
For TARGET B connector signals see table on next page.
!
BDI2000
Target System
ARM
The green LED «TRGT» marked light up when target is powered up
Rev. B/C
1 - Vcc Target
2 - NC
3 - TRST
4 - NC
5 - TDI
6 - NC
7 - TMS
8 - GROUND
9 - TCK
10 - GROUND
11 - RTCK
12 - NC
13 - TDO
14 - NC
15 - RESET
16 - NC
17 - NC
18 - NC
19 - NC
20 - NC
20 pin Multi-ICE
Connector
1
19
20
2
BDI TRGT MODE TARGET A TARGET B
15 1
16 2

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BDI TARGET B Connector Signals:
Pin Name Describtion
1 TDO JTAG Test Data Out
This input to the BDI2000 connects to the target TDO line.
2 reserved
3 TDI JTAG Test Data In
This output of the BDI2000 connects to the target TDI line.
4 reserved
5 RTCK Returned JTAG Test Clock
This input to the BDI2000 connects to the target RTCK line.
6 Vcc Target 1.8 – 5.0V:
This is the target reference voltage. It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators. It also controls the output logic
levels to the target. It is normally fed from Vdd I/O on the target board.
3.0 – 5.0V with Rev. A/B :
This input to the BDI2000 is used to detect if the target is powered up. If there is a current
limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
7 TCK JTAG Test Clock
This output of the BDI2000 connects to the target TCK line.
8TRST JTAG Test Reset
This open-drain / push-pull output of the BDI2000 resets the JTAG TAP controller on the
target. Default driver type is open-drain.
9 TMS JTAG Test Mode Select
This output of the BDI2000 connects to the target TMS line.
10 reserved
11 reserved
12 GROUND System Ground
13 RESET System Reset
This open-drain output of the BDI2000 is used to reset the target system.
14 reseved
15 reseved
16 GROUND System Ground

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2.1.3 Serial Wire Debug
For Cortex-M3 / Cortex-A8 the BDI2000 supports also the „Serial Wire Debug Port“ (SW-DP). In or-
der to use SW-DP a different firmware/logic has to be loaded into the BDI2000 (included on the CD).
Also a special target cable is available on request (p/n 90054).
BDI MAIN / TARGET A Connector Signals
Pin Name Describtion
3 GND System Ground
4 SWCLK Serial Wire Clock
6 SWDIO Serial Wire Debug Data Input/Output
10 SWO/SWV Serial Wire Output / Viewer (optional trace data output)
7RESET This open collector output of the BDI2000 can be used to hard reset the target system.
9 Vcc Target 1.8 – 5.0V:
This is the target reference voltage. It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators. It also controls the output logic
levels to the target. It is normally fed from Vdd I/O on the target board.
3.0 – 5.0V with Rev. A/B :
This input to the BDI2000 is used to detect if the target is powered up. If there is a current
limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
BDI2000
Target System
Cortex
The green LED «TRGT» marked light up when target is powered up
BDI TRGT MODE TARGET A TARGET B
9 1
10 2
Rev. A/B/C
SWCLK
SWDIO
Reset
Vcc Target
Ground
C
D
R
+
grey
grey
grey
red
black
SWO/SWV
V
grey