Active-semi PAC5223 Specification sheet

PRODUCT USER GUIDE
PAC5223
Power Application Controller®
Multi-Mode Power ManagerTM
Configura le Analog Front EndTM
Application Specific Power DriversTM
ARM© Cortex®-M0 Controller Core
www.active-semi.com
Copyright © 2018 Active-Semi, Inc.

PAC5223 User Guide
Power Application Controller
TABLE OF CONTENTS
1. Styles and Formatting Conventions................................................................................................................. 24
1.1. Overview.................................................................................................................................................. 24
1.2. Number Representation........................................................................................................................... 24
1.3. Formatting Styles..................................................................................................................................... 24
2. Memory and Register Map............................................................................................................................... 2
2.1. Memory Map............................................................................................................................................ 2
2.2. Register Map............................................................................................................................................ 26
3. Information Block............................................................................................................................................. 39
3.1. Register.................................................................................................................................................... 39
3.1.1. Register Map.................................................................................................................................... 39
3.1.2. ROSC11........................................................................................................................................... 39
3.1.3. ADCGAIN......................................................................................................................................... 39
3.1.4. ADCOFF.......................................................................................................................................... 39
3.1. . FTTEMP........................................................................................................................................... 40
3.1.6. TEMPS............................................................................................................................................. 40
3.1.7. CLKREF........................................................................................................................................... 40
3.1.8. PACIDR............................................................................................................................................ 40
3.2. Details of Operation................................................................................................................................. 40
3.2.1. Overview.......................................................................................................................................... 40
4. System Clock Control....................................................................................................................................... 41
4.1. Register.................................................................................................................................................... 41
4.1.1. Register Map.................................................................................................................................... 41
4.1.2. CCSCTL........................................................................................................................................... 41
4.1.3. PLLCTL............................................................................................................................................ 42
4.1.4. OSCCTL.......................................................................................................................................... 42
4.1. . XTALCTL.......................................................................................................................................... 42
4.2. Details of Operation................................................................................................................................. 43
4.2.1. Block Diagram.................................................................................................................................. 43
4.2.2. Configuration.................................................................................................................................... 43
4.2.3. ROSC............................................................................................................................................... 44
4.2.4. CLKREF........................................................................................................................................... 44
4.2. . XTAL................................................................................................................................................ 44
4.2.6. EXTCLK........................................................................................................................................... 44
4.2.7. PLL................................................................................................................................................... 44
4.2.8. FRCLK............................................................................................................................................. 4
4.2.9. FCLK................................................................................................................................................ 4
4.2.10. HCLK............................................................................................................................................. 4
4.2.11. ACLK.............................................................................................................................................. 4
4.2.12. Clock Gating................................................................................................................................... 4
. Watchdog Timer............................................................................................................................................... 46
.1. Register.................................................................................................................................................... 46
.1.1. Register Map.................................................................................................................................... 46
.1.2. WDTCTL.......................................................................................................................................... 46
.1.3. WDTCDV......................................................................................................................................... 47
.1.4. WDTCTR......................................................................................................................................... 47
.2. Details of Operation................................................................................................................................. 48
.2.1. Block Diagram.................................................................................................................................. 48
.2.2. Configuration.................................................................................................................................... 48
.2.3. Watchdog Timer............................................................................................................................... 48
.2.4. Access WDT Registers.................................................................................................................... 48
.2. . WDT Clock Setting........................................................................................................................... 48
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Power Application Controller
.2.6. General Purpose Timer Mode.......................................................................................................... 48
.2.7. Watchdog Timer Mode..................................................................................................................... 49
6. GPIO Port A..................................................................................................................................................... 0
6.1. Register.................................................................................................................................................... 0
6.1.1. Register Map.................................................................................................................................... 0
6.1.2. GPIOAO........................................................................................................................................... 0
6.1.3. GPIOAOUTEN................................................................................................................................. 1
6.1.4. GPIOADS......................................................................................................................................... 1
6.1. . GPIOAPU......................................................................................................................................... 2
6.1.6. GPIOAPD......................................................................................................................................... 3
6.1.7. GPIOAIN.......................................................................................................................................... 3
6.1.8. GPIOAPSEL..................................................................................................................................... 4
6.1.9. GPIOAINTP......................................................................................................................................
6.1.10. GPIOAINTE....................................................................................................................................
6.1.11. GPIOAINTF.................................................................................................................................... 6
6.1.12. GPIOAINTM................................................................................................................................... 7
6.2. Details of Operation................................................................................................................................. 8
6.2.1. Block Diagram.................................................................................................................................. 8
6.2.2. Configuration.................................................................................................................................... 8
6.2.3. GPIO A Block................................................................................................................................... 8
6.2.4. Input................................................................................................................................................. 8
6.2. . Output and Output Enable............................................................................................................... 8
6.2.6. Output Drive Strength...................................................................................................................... 9
6.2.7. Weak Pull Up and Pull Down........................................................................................................... 9
6.2.8. Peripheral Select.............................................................................................................................. 9
6.2.9. Interrupt............................................................................................................................................ 9
7. GPIO Port B..................................................................................................................................................... 60
7.1. Register.................................................................................................................................................... 60
7.1.1. Register Map.................................................................................................................................... 60
7.1.2. GPIOBOUT...................................................................................................................................... 60
7.1.3. GPIOBOUTEN................................................................................................................................. 60
7.1.4. GPIOBDS......................................................................................................................................... 61
7.1. . GPIOBPU......................................................................................................................................... 61
7.1.6. GPIOBPD......................................................................................................................................... 62
7.1.7. GPIOBIN.......................................................................................................................................... 62
7.1.8. GPIOBPSEL..................................................................................................................................... 62
7.1.9. GPIOBINTP...................................................................................................................................... 63
7.1.10. GPIOBINTE.................................................................................................................................... 64
7.1.11. GPIOBINTF.................................................................................................................................... 64
7.1.12. GPIOBINTM................................................................................................................................... 6
7.2. Details of Operation................................................................................................................................. 66
7.2.1. Block Diagram.................................................................................................................................. 66
7.2.2. Configuration.................................................................................................................................... 66
7.2.3. GPIO B Block................................................................................................................................... 66
7.2.4. Input................................................................................................................................................. 66
7.2. . Output and Output Enable............................................................................................................... 66
7.2.6. Output Drive Strength...................................................................................................................... 66
7.2.7. Weak Pull Up and Pull Down........................................................................................................... 67
7.2.8. Peripheral Select.............................................................................................................................. 67
7.2.9. Interrupt............................................................................................................................................ 67
8. GPIO Port C..................................................................................................................................................... 68
8.1. Register.................................................................................................................................................... 68
8.1.1. Register Map.................................................................................................................................... 68
8.1.2. GPIOCOUT...................................................................................................................................... 68
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Power Application Controller
8.1.3. GPIOCOUTEN................................................................................................................................. 69
8.1.4. GPIOCIN.......................................................................................................................................... 69
8.1. . GPIOCINE....................................................................................................................................... 70
8.1.6. GPIOCINTP..................................................................................................................................... 71
8.1.7. GPIOCINTE..................................................................................................................................... 71
8.1.8. GPIOCINTF...................................................................................................................................... 72
8.1.9. GPIOCINTM..................................................................................................................................... 72
8.2. Details of Operation................................................................................................................................. 74
8.2.1. Block Diagram.................................................................................................................................. 74
8.2.2. Configuration.................................................................................................................................... 74
8.2.3. GPIO C Block................................................................................................................................... 74
8.2.4. Analog Input..................................................................................................................................... 74
8.2. . Output and Output Enable............................................................................................................... 74
8.2.6. Interrupt............................................................................................................................................ 74
9. GPIO Port D..................................................................................................................................................... 76
9.1. Register.................................................................................................................................................... 76
9.1.1. Register Map.................................................................................................................................... 76
9.1.2. GPIODO........................................................................................................................................... 76
9.1.3. GPIODOUTEN................................................................................................................................. 77
9.1.4. GPIODDS........................................................................................................................................ 77
9.1. . GPIODPU........................................................................................................................................ 78
9.1.6. GPIODPD........................................................................................................................................ 79
9.1.7. GPIODIN.......................................................................................................................................... 79
9.1.8. GPIODPSEL.................................................................................................................................... 80
9.1.9. GPIODINTP..................................................................................................................................... 81
9.1.10. GPIODINTE................................................................................................................................... 81
9.1.11. GPIODINTF.................................................................................................................................... 82
9.1.12. GPIODINTM................................................................................................................................... 82
9.2. Details of Operation................................................................................................................................. 84
9.2.1. Block Diagram.................................................................................................................................. 84
9.2.2. Configuration.................................................................................................................................... 84
9.2.3. GPIO D Block................................................................................................................................... 84
9.2.4. Input................................................................................................................................................. 84
9.2. . Output and Output Enable............................................................................................................... 84
9.2.6. Output Drive Strength...................................................................................................................... 8
9.2.7. Weak Pull Up and Pull Down........................................................................................................... 8
9.2.8. Peripheral Select.............................................................................................................................. 8
9.2.9. Interrupt............................................................................................................................................ 8
10. GPIO Port E................................................................................................................................................... 86
10.1. Register.................................................................................................................................................. 86
10.1.1. Register Map.................................................................................................................................. 86
10.1.2. GPIOEOUT.................................................................................................................................... 86
10.1.3. GPIOEOUTEN............................................................................................................................... 87
10.1.4. GPIOEDS....................................................................................................................................... 87
10.1. . GPIOEPU....................................................................................................................................... 88
10.1.6. GPIOEPD....................................................................................................................................... 89
10.1.7. GPIOEIN........................................................................................................................................ 89
10.1.8. GPIOEPSEL................................................................................................................................... 90
10.1.9. GPIOEINTP.................................................................................................................................... 91
10.1.10. GPIOEINTE.................................................................................................................................. 91
10.1.11. GPIOEINTF.................................................................................................................................. 92
10.1.12. GPIOEINTM................................................................................................................................. 92
10.2. Details of Operation............................................................................................................................... 94
10.2.1. Block Diagram................................................................................................................................ 94
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Power Application Controller
10.2.2. Configuration.................................................................................................................................. 94
10.2.3. GPIO E Block................................................................................................................................. 94
10.2.4. Input............................................................................................................................................... 94
10.2. . Output and Output Enable............................................................................................................. 94
10.2.6. Output Drive Strength.................................................................................................................... 94
10.2.7. Weak Pull Up and Pull Down......................................................................................................... 9
10.2.8. Peripheral Select............................................................................................................................ 9
10.2.9. Interrupt.......................................................................................................................................... 9
11. General Purpose Timer.................................................................................................................................. 96
11.1. Register.................................................................................................................................................. 96
11.1.1. Register Map.................................................................................................................................. 96
11.1.2. RTCCTL......................................................................................................................................... 96
11.1.3. RTCCDV........................................................................................................................................ 97
11.1.4. RTCCTR......................................................................................................................................... 97
11.2. Details of Operation................................................................................................................................ 98
11.2.1. Block Diagram................................................................................................................................ 98
11.2.2. Configuration.................................................................................................................................. 98
11.2.3. General Purpose Timer.................................................................................................................. 98
11.2.4. Access GPT Registers.................................................................................................................... 98
11.2. . GPT Clock...................................................................................................................................... 98
11.2.6. General Purpose Timer Mode........................................................................................................ 98
12. Timer A........................................................................................................................................................... 99
12.1. Register.................................................................................................................................................. 99
12.1.1. Register Map.................................................................................................................................. 99
12.1.2. TACTL.......................................................................................................................................... 100
12.1.3. TAPRD......................................................................................................................................... 101
12.1.4. TACTR......................................................................................................................................... 101
12.1. . TACC0CTRL................................................................................................................................ 101
12.1.6. TACC0CTR.................................................................................................................................. 101
12.1.7. TACC1CTRL................................................................................................................................ 102
12.1.8. TACC1CTR.................................................................................................................................. 102
12.1.9. TACC2CTRL................................................................................................................................ 102
12.1.10. TACC2CTR................................................................................................................................ 103
12.1.11. TACC3CTRL............................................................................................................................... 103
12.1.12. TACC3CTR................................................................................................................................ 103
12.1.13. TACC4CTRL.............................................................................................................................. 103
12.1.14. TACC4CTR................................................................................................................................ 104
12.1.1 . TACC CTRL.............................................................................................................................. 104
12.1.16. TACC CTR................................................................................................................................ 104
12.1.17. TACC6CTRL.............................................................................................................................. 10
12.1.18. TACC6CTR................................................................................................................................ 10
12.1.19. TACC7CTRL.............................................................................................................................. 10
12.1.20. TACC7CTR................................................................................................................................ 106
12.1.21. DTGA0CTL................................................................................................................................ 106
12.1.22. DTGA0LED................................................................................................................................ 106
12.1.23. DTGA0TED................................................................................................................................ 106
12.1.24. DTGA1CTL................................................................................................................................ 107
12.1.2 . DTGA1LED................................................................................................................................ 107
12.1.26. DTGA1TED................................................................................................................................ 107
12.1.27. DTGA2CTL................................................................................................................................ 107
12.1.28. DTGA2LED................................................................................................................................ 108
12.1.29. DTGA2TED................................................................................................................................ 108
12.1.30. DTGA3CTL................................................................................................................................ 108
12.1.31. DTGA3LED................................................................................................................................ 109
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Power Application Controller
12.1.32. DTGA3TED................................................................................................................................ 109
12.2. Details of Operation.............................................................................................................................. 110
12.2.1. Block Diagram.............................................................................................................................. 110
12.2.2. Configuration............................................................................................................................... 110
12.2.3. Timer A Block................................................................................................................................ 110
12.2.4. Timer............................................................................................................................................ 110
12.2. . Register update............................................................................................................................ 111
12.2.6. Timer Modes................................................................................................................................. 111
12.2.7. Single Shot Mode......................................................................................................................... 111
12.2.8. Input Clock And Pre-Scaler...........................................................................................................111
12.2.9. Timer Synchronization.................................................................................................................. 111
12.2.10. PWM/Compare Units.................................................................................................................. 112
12.2.11. Timer and PWM/Capture Interrupt.............................................................................................. 113
12.2.12. Dead-Time Generator................................................................................................................. 114
12.2.13. PWM Output and Capture Input Pin Selection...........................................................................116
13. Timer B......................................................................................................................................................... 117
13.1. Register................................................................................................................................................ 117
13.1.1. Register Map................................................................................................................................ 117
13.1.2. TBCTL.......................................................................................................................................... 117
13.1.3. TBPRD......................................................................................................................................... 118
13.1.4. TBCTR......................................................................................................................................... 118
13.1. . TBCC0CTRL................................................................................................................................ 118
13.1.6. TBCC0CTR.................................................................................................................................. 119
13.1.7. TBCC1CTRL................................................................................................................................ 119
13.1.8. TBCC1CTR.................................................................................................................................. 119
13.1.9. TBCC2CTRL................................................................................................................................ 120
13.1.10. TBCC2CTR................................................................................................................................ 120
13.1.11. TBCC3CTRL.............................................................................................................................. 120
13.1.12. TBCC3CTR................................................................................................................................ 121
13.1.13. DTGB0CTL................................................................................................................................ 121
13.1.14. DTGB0LED................................................................................................................................ 121
13.1.1 . DTGB0TED................................................................................................................................ 122
13.2. Details of Operation............................................................................................................................. 123
13.2.1. Block Diagram.............................................................................................................................. 123
13.2.2. Configuration................................................................................................................................ 123
13.2.3. Timer B Block............................................................................................................................... 123
13.2.4. Timer............................................................................................................................................ 123
13.2. . Register update............................................................................................................................ 124
13.2.6. Timer Modes................................................................................................................................ 124
13.2.7. Single Shot Mode......................................................................................................................... 124
13.2.8. Input Clock And Pre-Scaler..........................................................................................................124
13.2.9. Timer Synchronization.................................................................................................................. 124
13.2.10. PWM/Compare Units................................................................................................................. 12
13.2.11. Timer and PWM/Capture Interrupt..............................................................................................126
13.2.12. Dead-Time Generator................................................................................................................ 127
13.2.13. PWM Output and Capture Input Pin Selection...........................................................................129
14. Timer C......................................................................................................................................................... 130
14.1. Register................................................................................................................................................ 130
14.1.1. Register Map................................................................................................................................ 130
14.1.2. TCCTL.......................................................................................................................................... 130
14.1.3. TCPRD......................................................................................................................................... 131
14.1.4. TCCTR......................................................................................................................................... 131
14.1. . TCCC0CTRL................................................................................................................................ 131
14.1.6. TCCC0CTR.................................................................................................................................. 132
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Power Application Controller
14.1.7. TCCC1CTRL................................................................................................................................ 132
14.1.8. TCCC1CTR.................................................................................................................................. 132
14.1.9. DTGC0CTL.................................................................................................................................. 133
14.1.10. DTGC0LED................................................................................................................................ 133
14.1.11. DTGC0TED................................................................................................................................ 133
14.2. Details of Operation............................................................................................................................. 134
14.2.1. Block Diagram.............................................................................................................................. 134
14.2.2. Configuration............................................................................................................................... 134
14.2.3. Timer C Block............................................................................................................................... 134
14.2.4. Timer............................................................................................................................................ 134
14.2. . Register update............................................................................................................................ 13
14.2.6. Timer Modes................................................................................................................................ 13
14.2.7. Single Shot Mode......................................................................................................................... 13
14.2.8. Input clock and Pre-scaler............................................................................................................ 13
14.2.9. Timer synchronization.................................................................................................................. 13
14.2.10. PWM/Compare Units................................................................................................................. 136
14.2.11. Timer and PWM/Capture Interrupt..............................................................................................137
14.2.12. Dead-Time Generator................................................................................................................ 138
14.2.13. PWM Output and Capture Input Pin Selection...........................................................................140
1 . Timer D......................................................................................................................................................... 141
1 .1. Register................................................................................................................................................ 141
1 .1.1. Register Map................................................................................................................................ 141
1 .1.2. TDCTL.......................................................................................................................................... 141
1 .1.3. TDPRD......................................................................................................................................... 142
1 .1.4. TDCTR......................................................................................................................................... 142
1 .1. . TDCC0CTL.................................................................................................................................. 142
1 .1.6. TDCC0CTR.................................................................................................................................. 143
1 .1.7. TDCC1CTRL................................................................................................................................ 143
1 .1.8. TDCC1CTR.................................................................................................................................. 143
1 .1.9. DTGD0CTL.................................................................................................................................. 144
1 .1.10. DTGD0LED................................................................................................................................ 144
1 .1.11. DTGD0TED................................................................................................................................ 144
1 .2. Details of Operation............................................................................................................................. 14
1 .2.1. Block Diagram.............................................................................................................................. 14
1 .2.2. Configuration............................................................................................................................... 14
1 .2.3. Timer D Block............................................................................................................................... 14
1 .2.4. Timer............................................................................................................................................ 14
1 .2. . Register Update........................................................................................................................... 146
1 .2.6. Timer Modes................................................................................................................................ 146
1 .2.7. Single Shot Mode......................................................................................................................... 146
1 .2.8. Input Clock And Pre-Scaler..........................................................................................................146
1 .2.9. Timer Synchronization.................................................................................................................. 146
1 .2.10. PWM/Compare Units................................................................................................................. 147
1 .2.11. Timer and PWM/Capture Interrupt..............................................................................................148
1 .2.12. Dead-Time Generator................................................................................................................ 148
1 .2.13. PWM Output and Capture Input Pin Selection...........................................................................1 0
16. FLASH Memory Controller........................................................................................................................... 1 1
16.1. Register................................................................................................................................................ 1 1
16.1.1. Register Map................................................................................................................................ 1 1
16.1.2. FLASHLOCK................................................................................................................................ 1 1
16.1.3. FLASHCTL................................................................................................................................... 1 2
16.1.4. FLASHPAGE................................................................................................................................ 1 2
16.1. . FLASHPERASE........................................................................................................................... 1 3
16.1.6. SWDACCESS.............................................................................................................................. 1 3
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PAC5223 User Guide
Power Application Controller
16.1.7. FLASHWSTATE........................................................................................................................... 1 3
16.1.8. FLASHBWRITE............................................................................................................................ 1 3
16.1.9. FLASHBWDATA........................................................................................................................... 1 4
16.2. Details of Operation............................................................................................................................. 1
16.2.1. Block Diagram.............................................................................................................................. 1
16.2.2. Configuration................................................................................................................................ 1
16.2.3. FLASH Memory............................................................................................................................ 1
16.2.4. Writing to FLASH Controller Registers.........................................................................................1
16.2. . FLASH Wait State........................................................................................................................ 1
16.2.6. FLASH Page Erase...................................................................................................................... 1 6
16.2.7. Write to FLASH............................................................................................................................ 1 6
16.2.8. Buffered Write to FLASH.............................................................................................................. 1 6
16.2.9. SWD Debug Access Disable........................................................................................................ 1 7
17. ADC and AUTO SEQUENCER.................................................................................................................... 1 8
17.1. Register................................................................................................................................................ 1 8
17.1.1. Register Map................................................................................................................................ 1 8
17.1.2. EMUXCTL.................................................................................................................................... 1 9
17.1.3. EMUXDATA.................................................................................................................................. 160
17.1.4. ADCCTL....................................................................................................................................... 161
17.1. . ADCCR........................................................................................................................................ 161
17.1.6. ADCINT........................................................................................................................................ 162
17.1.7. AS0CTL........................................................................................................................................ 163
17.1.8. AS0S0.......................................................................................................................................... 164
17.1.9. AS0R0.......................................................................................................................................... 164
17.1.10. AS0S1........................................................................................................................................ 164
17.1.11. AS0R1........................................................................................................................................ 16
17.1.12. AS0S2........................................................................................................................................ 16
17.1.13. AS0R2........................................................................................................................................ 16
17.1.14. AS0S3........................................................................................................................................ 166
17.1.1 . AS0R3........................................................................................................................................ 166
17.1.16. AS0S4........................................................................................................................................ 166
17.1.17. AS0R4........................................................................................................................................ 167
17.1.18. AS0S ........................................................................................................................................ 167
17.1.19. AS0R ........................................................................................................................................ 167
17.1.20. AS0S6........................................................................................................................................ 168
17.1.21. AS0R6........................................................................................................................................ 168
17.1.22. AS0S7........................................................................................................................................ 168
17.1.23. AS0R7........................................................................................................................................ 169
17.1.24. AS1CTL...................................................................................................................................... 169
17.1.2 . AS1S0........................................................................................................................................ 170
17.1.26. AS1R0........................................................................................................................................ 170
17.1.27. AS1S1........................................................................................................................................ 171
17.1.28. AS1R1........................................................................................................................................ 171
17.1.29. AS1S2........................................................................................................................................ 171
17.1.30. AS1R2........................................................................................................................................ 172
17.1.31. AS1S3........................................................................................................................................ 172
17.1.32. AS1R3........................................................................................................................................ 172
17.1.33. AS1S4........................................................................................................................................ 173
17.1.34. AS1R4........................................................................................................................................ 173
17.1.3 . AS1S ........................................................................................................................................ 173
17.1.36. AS1R ........................................................................................................................................ 174
17.1.37. AS1S6........................................................................................................................................ 174
17.1.38. AS1R6........................................................................................................................................ 174
17.1.39. AS1S7........................................................................................................................................ 17
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Power Application Controller
17.1.40. AS1R7........................................................................................................................................ 17
17.2. Details of Operation............................................................................................................................. 17
17.2.1. Block Diagram.............................................................................................................................. 17
17.3. Details of Operation............................................................................................................................. 17
17.3.1. Basic Configuration...................................................................................................................... 17
17.3.2. ADC, Autosequencer and EMUX..................................................................................................176
17.3.3. Clock Setting................................................................................................................................ 176
17.3.4. ADC.............................................................................................................................................. 177
17.3. . EMUX........................................................................................................................................... 177
17.3.6. Auto Sequencer ASC0, ASC1......................................................................................................177
18. I2C................................................................................................................................................................ 182
18.1. Register................................................................................................................................................ 182
18.1.1. Register Map................................................................................................................................ 182
18.1.2. I2CCFG........................................................................................................................................ 182
18.1.3. I2CSTATUS.................................................................................................................................. 182
18.1.4. I2CIE............................................................................................................................................ 184
18.1. . I2CMCTRL................................................................................................................................... 184
18.1.6. I2CMRXDATA.............................................................................................................................. 18
18.1.7. I2CMTXDATA............................................................................................................................... 18
18.1.8. I2CBAUD..................................................................................................................................... 18
18.1.9. I2CSLRXDATA............................................................................................................................. 18
18.1.10. I2CSLTXDATA............................................................................................................................ 186
18.1.11. I2CADDR.................................................................................................................................... 186
18.2. Details of Operation............................................................................................................................. 187
18.2.1. Block Diagram.............................................................................................................................. 187
18.2.2. Configuration............................................................................................................................... 187
18.2.3. I2C............................................................................................................................................... 187
18.2.4. I2C Clock setting.......................................................................................................................... 187
18.2. . I2C Addressing............................................................................................................................. 188
18.2.6. I2C Master Read Transactions.....................................................................................................188
19. UART........................................................................................................................................................... 191
19.1. Register................................................................................................................................................ 191
19.1.1. Register Map................................................................................................................................ 191
19.1.2. UARTRXTX/UARTDL_L............................................................................................................... 191
19.1.3. UARTIER/UARTDL_H..................................................................................................................192
19.1.4. UARTIIR....................................................................................................................................... 192
19.1. . UARTLCR.................................................................................................................................... 193
19.1.6. UARTMCR................................................................................................................................... 193
19.1.7. UARTLSR.................................................................................................................................... 193
19.1.8. UARTSP....................................................................................................................................... 194
19.1.9. UARTFCTL2................................................................................................................................ 194
19.1.10. UARTIER2................................................................................................................................. 19
19.1.11. UARTDL_L2............................................................................................................................... 19
19.1.12. UARTDL_H2.............................................................................................................................. 19
19.1.13. UARTFD_F................................................................................................................................ 19
19.1.14. UARTSTAT................................................................................................................................. 19
19.2. Details of Operation............................................................................................................................. 197
19.2.1. Block Diagram.............................................................................................................................. 197
19.2.2. Configuration............................................................................................................................... 197
19.2.3. UART........................................................................................................................................... 197
19.2.4. UART Clock Rate Setting.............................................................................................................197
19.2. . Data settings................................................................................................................................ 199
19.2.6. FIFO Settings............................................................................................................................... 199
19.2.7. Error Checking on Received Data................................................................................................199
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Power Application Controller
20. SOC Bus bridge........................................................................................................................................... 200
20.1. Register................................................................................................................................................ 200
20.1.1. Register Map................................................................................................................................ 200
20.1.2. SOCBCTL.................................................................................................................................... 200
20.1.3. SOCBCFG................................................................................................................................... 200
20.1.4. SOCBCLKDIV.............................................................................................................................. 201
20.1. . SOCBSTAT.................................................................................................................................. 201
20.1.6. SOCBCSSTR............................................................................................................................... 202
20.1.7. SOCBD........................................................................................................................................ 203
20.1.8. SOCBINT_EN.............................................................................................................................. 203
20.2. Details of Operation............................................................................................................................. 204
20.2.1. Block Diagram.............................................................................................................................. 204
20.2.2. Configuration............................................................................................................................... 204
20.2.3. SOC Bridge.................................................................................................................................. 204
20.2.4. SOC Bridge Clock Rate Setting................................................................................................... 204
20.2. . Enable and Setup of SOC Bridge................................................................................................. 20
20.2.6. SOC Interrupt............................................................................................................................... 20
20.2.7. SOC Bridge Protocol.................................................................................................................... 20
20.2.8. Reading from SOC Bridge........................................................................................................... 20
20.2.9. Writing to SOC Bridge.................................................................................................................. 20
21. SPI............................................................................................................................................................... 206
21.1. Register................................................................................................................................................ 206
21.1.1. Register Map................................................................................................................................ 206
21.1.2. SPICTL........................................................................................................................................ 206
21.1.3. SPICFG........................................................................................................................................ 207
21.1.4. SPICLKDIV.................................................................................................................................. 208
21.1. . SPISTAT....................................................................................................................................... 208
21.1.6. SPICSSTR................................................................................................................................... 210
21.1.7. SPID............................................................................................................................................. 211
21.1.8. SPIINT_EN................................................................................................................................... 211
21.2. Details of Operation............................................................................................................................. 212
21.2.1. Block Diagram.............................................................................................................................. 212
21.2.2. Configuration............................................................................................................................... 212
21.2.3. SPI............................................................................................................................................... 212
21.2.4. SPI Clock Rate Setting................................................................................................................. 212
21.2. . Master Slave Mode...................................................................................................................... 213
21.2.6. Clock Phase, Polarity................................................................................................................... 213
21.2.7. SPI Early Data Transmit............................................................................................................... 213
21.2.8. Data Format................................................................................................................................. 214
21.2.9. Chip Select Settings..................................................................................................................... 21
21.2.10. Auto Retransmit Data Word........................................................................................................ 21
21.2.11. Loop Back Mode........................................................................................................................ 21
21.2.12. SPI Interrupt............................................................................................................................... 216
21.2.13. SPI Enable................................................................................................................................. 216
22. Multi-Mode Power Manager......................................................................................................................... 217
22.1. Register................................................................................................................................................ 217
22.1.1. Register Map................................................................................................................................ 217
22.1.2. SYSTAT........................................................................................................................................ 217
22.1.3. DEVID.......................................................................................................................................... 218
22.1.4. VERID.......................................................................................................................................... 218
22.1. . PWRCTL...................................................................................................................................... 218
22.1.6. PWRSTAT.................................................................................................................................... 219
22.1.7. PSTATSET................................................................................................................................... 219
22.1.8. IMOD............................................................................................................................................ 220
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22.1.9. SCFG........................................................................................................................................... 220
22.1.10. SCFG2....................................................................................................................................... 220
23. Configurable Analog FRONT END............................................................................................................... 222
23.1. Register................................................................................................................................................ 222
23.1.1. Register Map................................................................................................................................ 222
23.1.2. SOC.CFGAIO0............................................................................................................................. 223
23.1.3. SOC.CFGAIO1............................................................................................................................. 223
23.1.4. SOC.CFGAIO2............................................................................................................................. 22
23.1. . SOC.CFGAIO3............................................................................................................................. 22
23.1.6. SOC.CFGAIO4............................................................................................................................. 227
23.1.7. SOC.CFGAIO ............................................................................................................................. 227
23.1.8. SOC.CFGAIO6............................................................................................................................. 229
23.1.9. SOC.CFGAIO7............................................................................................................................. 230
23.1.10. SOC.CFGAIO8........................................................................................................................... 231
23.1.11. SOC.CFGAIO9........................................................................................................................... 232
23.1.12. SOC.SIGSET............................................................................................................................. 233
23.1.13. SOC.HPDAC.............................................................................................................................. 233
23.1.14. SOC.LPDAC0............................................................................................................................ 233
23.1.1 . SOC.LPDAC1............................................................................................................................ 233
23.1.16. SOC.ADCSCAN......................................................................................................................... 234
23.1.17. SOC.ADCIN1............................................................................................................................. 234
23.1.18. SOC.PROTINTM........................................................................................................................ 234
23.1.19. SOC.PROTSTAT........................................................................................................................ 23
23.1.20. SOC.DOUTSIG0........................................................................................................................ 23
23.1.21. SOC.DOUTSIG1........................................................................................................................ 236
23.1.22. SOC.DINSIG0............................................................................................................................ 236
23.1.23. SOC.DINSIG1............................................................................................................................ 237
23.1.24. SOC.SIGINTM........................................................................................................................... 237
23.1.2 . SOC.SIGINTF............................................................................................................................ 238
23.1.26. SOC.ENSIG............................................................................................................................... 238
23.2. Details of Operation............................................................................................................................. 239
23.2.1. Block Diagram.............................................................................................................................. 239
23.2.2. Configuration............................................................................................................................... 239
23.2.3. Configurable Analog Front End....................................................................................................239
23.3. AIO1, AIO0........................................................................................................................................... 240
23.3.1. Block Diagram.............................................................................................................................. 240
23.3.2. AIO1, AIO0................................................................................................................................... 240
23.3.3. AIO1, AIO0 digital I/O Mode......................................................................................................... 240
23.3.4. AIO1, AIO0 differential Amplifier Mode.........................................................................................241
23.3. . AIO1, AIO0 Protection.................................................................................................................. 241
23.4. AIO3, AIO2........................................................................................................................................... 243
23.4.1. Block Diagram.............................................................................................................................. 243
23.4.2. AIO3, AIO2................................................................................................................................... 243
23.4.3. AIO3, AIO2 digital I/O Mode......................................................................................................... 243
23.4.4. AIO3, AIO2 differential Amplifier Mode DAO32............................................................................244
23.4. . AIO3, AIO2 Protection.................................................................................................................. 244
23. . AIO , AIO4........................................................................................................................................... 246
23. .1. Block Diagram.............................................................................................................................. 246
23. .2. AIO , AIO4................................................................................................................................... 246
23. .3. AIO , AIO4 digital I/O Mode......................................................................................................... 246
23. .4. AIO , AIO4 differential Amplifier Mode DAO 4............................................................................247
23. . . AIO , AIO4 Protection.................................................................................................................. 247
23.6. AIO6..................................................................................................................................................... 249
23.6.1. Block Diagram.............................................................................................................................. 249
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23.6.2. AIO6............................................................................................................................................. 249
23.6.3. AIO6 digital I/O Mode...................................................................................................................2 0
23.6.4. AIO6 Single Ended Amplifier Mode.............................................................................................. 2 0
23.6. . AIO6 Comparator Mode............................................................................................................... 2 0
23.6.6. AIO6 Special Mode...................................................................................................................... 2 1
23.6.7. AIO6 Push Button Mode............................................................................................................... 2 1
23.7. AIO7..................................................................................................................................................... 2 3
23.7.1. Block Diagram.............................................................................................................................. 2 3
23.7.2. AIO7............................................................................................................................................. 2 3
23.7.3. AIO7 digital I/O Mode...................................................................................................................2 3
23.7.4. AIO7 Single Ended Amplifier Mode.............................................................................................. 2 4
23.7. . AIO7 Comparator Mode............................................................................................................... 2 4
23.7.6. AIO7 Special Mode...................................................................................................................... 2
23.8. AIO8..................................................................................................................................................... 2 7
23.8.1. Block Diagram.............................................................................................................................. 2 7
23.8.2. AIO8............................................................................................................................................. 2 7
23.8.3. AIO8 digital I/O Mode...................................................................................................................2 8
23.8.4. AIO8 Single Ended Amplifier Mode.............................................................................................. 2 8
23.8. . AIO8 Comparator Mode............................................................................................................... 2 8
23.8.6. AIO8 Special Mode...................................................................................................................... 2 9
23.9. AIO9..................................................................................................................................................... 261
23.9.1. Block Diagram.............................................................................................................................. 261
23.9.2. AIO9............................................................................................................................................. 261
23.9.3. AIO9 digital I/O Mode...................................................................................................................262
23.9.4. AIO9 Single Ended Amplifier Mode.............................................................................................. 262
23.9. . AIO9 Comparator Mode............................................................................................................... 262
23.9.6. AIO9 Special Mode...................................................................................................................... 263
23.10. EMUX and ADMUX............................................................................................................................ 26
23.10.1. Block Diagram............................................................................................................................ 26
23.10.2. EMUX......................................................................................................................................... 26
23.10.3. ADMUX...................................................................................................................................... 266
24. Application Specific Power Driver................................................................................................................. 268
24.1. Register................................................................................................................................................ 268
24.1.1. Register Map................................................................................................................................ 268
24.1.2. SOC.CFGDRV0........................................................................................................................... 268
24.1.3. SOC.CFGDRV1........................................................................................................................... 268
24.1.4. SOC.CFGDRQ6........................................................................................................................... 269
24.1. . SOC.CFGDRQ7........................................................................................................................... 269
24.1.6. SOC.DOUTDRV........................................................................................................................... 270
24.1.7. SOC.DINDRV............................................................................................................................... 270
24.1.8. SOC.ENDRV................................................................................................................................ 271
24.1.9. SOC.ENBBM................................................................................................................................ 271
24.1.10. SOC.PROTCTL.......................................................................................................................... 271
24.2. Details of Operation............................................................................................................................. 272
24.2.1. Block Diagram.............................................................................................................................. 272
24.2.2. Configuration............................................................................................................................... 272
24.2.3. Application Specific Power Driver.................................................................................................272
24.3. ENHS1, ENLS1 Protection................................................................................................................... 273
24.3.1. Block Diagram.............................................................................................................................. 273
24.3.2. ENHS1, ENLS1 Protection........................................................................................................... 273
24.4. DRL0 Low Side Driver.......................................................................................................................... 27
24.4.1. Block Diagram.............................................................................................................................. 27
24.4.2. DRL0............................................................................................................................................ 27
24. . DRL1 Low Side Driver.......................................................................................................................... 276
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24. .1. Block Diagram.............................................................................................................................. 276
24. .2. DRL1............................................................................................................................................ 276
24.6. DRL2 Low Side Driver.......................................................................................................................... 277
24.6.1. Block Diagram.............................................................................................................................. 277
24.6.2. DRL2............................................................................................................................................ 277
24.7. DRH3 High Side Driver........................................................................................................................ 278
24.7.1. Block Diagram.............................................................................................................................. 278
24.7.2. DRH3........................................................................................................................................... 278
24.8. DRH4 High Side Driver........................................................................................................................ 279
24.8.1. Block Diagram.............................................................................................................................. 279
24.8.2. DRH4........................................................................................................................................... 279
24.9. DRH High Side Driver........................................................................................................................ 280
24.9.1. Block Diagram.............................................................................................................................. 280
24.9.2. DRH ........................................................................................................................................... 280
2 . Arm Cortex-M0 Reference............................................................................................................................ 281
2 .1. Introduction.......................................................................................................................................... 281
2 .1.1. Overview...................................................................................................................................... 281
2 .1.2. About the Cortex-M0 processor and core peripherals..................................................................281
2 .2. The Cortex-M0 Processor.................................................................................................................... 283
2 .2.1. Programmers Model..................................................................................................................... 283
2 .2.2. Memory model............................................................................................................................. 290
2 .2.3. Exception model........................................................................................................................... 29
2 .2.4. Fault handling............................................................................................................................... 301
2 .2. . Power management..................................................................................................................... 302
2 .3. The Cortex-M0 Instruction Set............................................................................................................. 304
2 .3.1. Instruction set summary............................................................................................................... 304
2 .3.2. Intrinsic Functions........................................................................................................................ 306
2 .3.3. About the Instruction Descriptions................................................................................................307
2 .3.4. Memory access instructions......................................................................................................... 312
2 .3. . General data processing instructions...........................................................................................319
2 .3.6. Branch and control instructions.................................................................................................... 331
2 .3.7. Miscellaneous instructions........................................................................................................... 333
2 .4. Cortex-M0 Peripherals......................................................................................................................... 343
2 .4.1. About the Cortex-M0 peripherals.................................................................................................. 343
2 .4.2. Nested Vectored Interrupt Controller............................................................................................343
2 .4.3. System Control Block................................................................................................................... 349
2 .4.4. System timer, SysTick.................................................................................................................. 3 6
26. Legal Information......................................................................................................................................... 360
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Power Application Controller
LIST OF TABLES
Table 2-1. Embedded FLASH Register Map........................................................................................................26
Table 2-2. ROM Register Map.............................................................................................................................. 27
Table 2-3. System Clock Control Register Map.................................................................................................... 28
Table 2-4. FLASH Memory Controller Register Map............................................................................................29
Table 2- . Watchdog Timer Register Map............................................................................................................ 29
Table 2-6. General Purpose Timer Register Map.................................................................................................29
Table 2-7. GPIO Port A Register Map................................................................................................................... 29
Table 2-8. GPIO Port B Register Map..................................................................................................................30
Table 2-9. GPIO Port AB Register Map................................................................................................................31
Table 2-10. GPIO Port C Register Map................................................................................................................ 31
Table 2-11. GPIO Port D Register Map................................................................................................................31
Table 2-12. GPIO Port CD Register Map............................................................................................................. 32
Table 2-13. GPIO Port E Register Map................................................................................................................ 32
Table 2-14. Timer A Register Map........................................................................................................................ 33
Table 2-1 . Timer B Register Map........................................................................................................................ 34
Table 2-16. Timer C Register Map........................................................................................................................ 34
Table 2-17. Timer D Register Map........................................................................................................................ 3
Table 2-18. EMUX Register Map.......................................................................................................................... 3
Table 2-19. ADC Register Map............................................................................................................................. 3
Table 2-20. ADC Auto-Sampling Sequencer 0 Register Map...............................................................................3
Table 2-21. ADC Auto-Sampling Sequencer 1 Register Map...............................................................................36
Table 2-22. I2C Register Map............................................................................................................................... 36
Table 2-23. UART Register Map.......................................................................................................................... 37
Table 2-24. SOC Bus Bridge Register Map.......................................................................................................... 37
Table 2-2 . SPI Register Map.............................................................................................................................. 38
Table 2-26. Multi-Mode Power Manager Register Map........................................................................................38
Table 3-1. Information Block Register Map..........................................................................................................39
Table 4-1. System Clock Control Register Map.................................................................................................... 41
Table -1. Watchdog Timer Register Map............................................................................................................ 46
Table 6-1. GPIO Port A Register Map................................................................................................................... 0
Table 7-1. GPIO Port B Register Map..................................................................................................................60
Table 8-1. GPIO Port C Register Map.................................................................................................................. 68
Table 9-1. GPIO Port D Register Map.................................................................................................................. 76
Table 10-1. GPIO Port E Register Map................................................................................................................ 86
Table 11-1. General Purpose Timer Register Map............................................................................................... 96
Table 12-1. Timer A Register Map........................................................................................................................ 99
Table 12-2. Timer A Signal to Pin Mapping......................................................................................................... 116
Table 13-1. Timer B Register Map...................................................................................................................... 117
Table 13-2. Timer B Signal to Pin Mapping........................................................................................................ 129
Table 14-1. Timer C Register Map...................................................................................................................... 130
Table 14-2. Timer C Signal to Pin Mapping........................................................................................................140
Table 1 -1. Timer D Register Map...................................................................................................................... 141
Table 1 -2. Timer D Signal to Pin Mapping........................................................................................................ 1 0
Table 16-1. FLASH Memory Controller Register Map........................................................................................1 1
Table 17-1. Register Map – EMUX..................................................................................................................... 1 8
Table 17-2. Register Map – ADC........................................................................................................................ 1 8
Table 17-3. Register Map – ADC Auto Sequencer 0..........................................................................................1 8
Table 17-4. Register Map – ADC Auto Sequencer 1..........................................................................................1 9
Table 18-1. I2C Register Map............................................................................................................................. 182
Table 19-1. UART Register Map........................................................................................................................ 191
Table 20-1. SOC Bus Bridge Register Map........................................................................................................ 200
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Power Application Controller
Table 21-1. SPI Register Map............................................................................................................................ 206
Table 22-1. Multi-Mode Power Manager Register Map......................................................................................217
Table 23-1. Configurable Analog Front End Register Map.................................................................................222
Table 24-1. Application Specific Power Driver Register Map..............................................................................268
Table 2 -1. Summary of processor mode and stack use options.......................................................................283
Table 2 -2. Core register set summary.............................................................................................................. 284
Table 2 -3. Core register set summary.............................................................................................................. 286
Table 2 -4. APSR bit assignments..................................................................................................................... 286
Table 2 - . IPSR bit assignments...................................................................................................................... 286
Table 2 -6. EPSR bit assignments..................................................................................................................... 287
Table 2 -7. PRIMASK register bit assignments..................................................................................................288
Table 2 -8. CONTROL register bit assignments................................................................................................289
Table 2 -9. Memory Access Behavior................................................................................................................ 293
Table 2 -10. Properties of the different exception types.....................................................................................296
Table 2 -11. Execution return behavior..............................................................................................................301
Table 2 -12. Cortex-M0 instructions................................................................................................................... 30
Table 2 -13. CMSIS intrinsic functions to generate some Cortex-M0 instructions.............................................306
Table 2 -14. CMSIS intrinsic functions to access special registers....................................................................307
Table 2 -1 . Condition code suffixes................................................................................................................. 312
Table 2 -16. Memory access instructions.......................................................................................................... 312
Table 2 -17. Data processing instructions......................................................................................................... 319
Table 2 -18. ADC, ADD, RSB, SBC, and SUB operand restrictions..................................................................321
Table 2 -19. Branch and Control instructions.....................................................................................................331
Table 2 -20. Branch ranges............................................................................................................................... 332
Table 2 -21. Miscellaneous instructions............................................................................................................. 333
Table 2 -22. Core peripheral register regions....................................................................................................343
Table 2 -23. NVIC register summary................................................................................................................. 343
Table 2 -24. CMSIS access NVIC functions...................................................................................................... 344
Table 2 -2 . ISER bit assignments.................................................................................................................... 344
Table 2 -26. ICER bit assignments.................................................................................................................... 34
Table 2 -27. ISPR bit assignments.................................................................................................................... 346
Table 2 -28. ICPR bit assignments.................................................................................................................... 346
Table 2 -29. IPR bit assignments....................................................................................................................... 347
Table 2 -30. CMSIS access NVIC functions...................................................................................................... 349
Table 2 -31. Summary of the SCB register........................................................................................................ 349
Table 2 -32. CPUID register bit assignments.....................................................................................................3 0
Table 2 -33. ICSR register bit assignments....................................................................................................... 3 1
Table 2 -34. AIRCR register bit assignments.....................................................................................................3 2
Table 2 -3 . SCR register bit assignments........................................................................................................3 3
Table 2 -36. CCR register bit assignments........................................................................................................3 4
Table 2 -37. System fault handler priority fields................................................................................................. 3
Table 2 -38. SHPR2 register bit assignments....................................................................................................3
Table 2 -39. SHPR3 register bit assignments....................................................................................................3
Table 2 -40. System timer register summary..................................................................................................... 3 6
Table 2 -41. SYST_CSR register bit assignments.............................................................................................3 7
Table 2 -42. SYST_RVR register bit assignments.............................................................................................3 7
Table 2 -43. SYST_CVR register bit assignments.............................................................................................3 8
Table 2 -44. SYST_CALIB register bit assignments.......................................................................................... 3 8
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Power Application Controller
LIST OF REGISTERS
Register 3-1. ROSC11 (ROSC11 Frequency Value, 0x0010 0010)......................................................................39
Register 3-2. ADCGAIN (ADC Gain Value, 0x0010 0020)....................................................................................39
Register 3-3. ADCOFF (ADC Offset, 0x0010 0024).............................................................................................39
Register 3-4. FTTEMP (FT Temp value, 0x0010 0028)........................................................................................40
Register 3- . TEMPS (Temperature Sensor reading, 0x0010 002A)....................................................................40
Register 3-6. CLKREF (CLKREF Frequency Value, 0x0010 002C).....................................................................40
Register 3-7. PACIDR (PAC part number and revision, 0x0010 0044).................................................................40
Register 4-1. CCSCTL (System Clock Control, 0x4000 0000).............................................................................41
Register 4-2. PLLCTL (PLL Control, 0x4000 0004).............................................................................................. 42
Register 4-3. OSCCTL (Ring Oscillator Control, 0x4000 0008)...........................................................................42
Register 4-4. XTALCTL (Crystal Driver Control, 0x4000 000C)............................................................................42
Table 4- . PLL output frequency settings using 4MHz ROSC as input.................................................................4
Register -1. WDTCTL (Watchdog Timer Control, 0x4003 0000)........................................................................46
Register -2. WDTCDV (Watchdog Timer Count-Down Value, 0x4003 0004).....................................................47
Register -3. WDTCTR (Watchdog Timer Counter, 0x4003 0008).......................................................................47
Register 6-1. GPIOAOUT (GPIO Port A Output, 0x4007 0000)............................................................................ 0
Register 6-2. GPIOAOUTEN (GPIO Port A Output Enable, 0x4007 0004).......................................................... 1
Register 6-3. GPIOADS (GPIO Port A Output Drive Strength, 0x4007 0008)...................................................... 1
Register 6-4. GPIOAPU (GPIO Port A Weak Pull Up, 0x4007 000C)................................................................... 2
Register 6- . GPIOAPD (GPIO Port A Weak Pull Down, 0x4007 0010)............................................................... 3
Register 6-6. GPIOAIN (GPIO Port A Input, 0x4007 0014).................................................................................. 3
Register 6-7. GPIOAPSEL (GPIO Port A Peripheral Select, 0x4007 001C)......................................................... 4
Register 6-8. GPIOAINTP (GPIO Port A Interrupt Polarity, 0x4007 0020)............................................................
Register 6-9. GPIOAINTE (GPIO Port A Interrupt Enable, 0x4007 0024)............................................................
Register 6-10. GPIOAINTF (GPIO Port A Interrupt Flag, 0x4007 0028)............................................................... 6
Register 6-11. GPIOAINTM (GPIO Port A Interrupt Mask, 0x4007 002C)............................................................ 7
Register 7-1. GPIOBOUT (GPIO Port B Output, 0x4007 0040)...........................................................................60
Register 7-2. GIOBOUTEN (GPIO Port B Output Enable, 0x4007 0044)............................................................60
Register 7-3. GPIOBDS (GPIO Port B Output Drive Strength, 0x4007 0048)......................................................61
Register 7-4. GPIOBPU (GPIO Port B Weak Pull Up, 0x4007 004C)..................................................................61
Register 7- . GPIOBPD (GPIO Port B Weak Pull Down, 0x4007 00 0)..............................................................62
Register 7-6. GPIOBIN (GPIO Port B Input, 0x4007 00 4)..................................................................................62
Register 7-7. GPIOBPSEL (GPIO Port B Peripheral Select, 0x4007 00 C).........................................................62
Register 7-8. GPGPIOIOBINTP (GPIO Port B Interrupt Polarity, 0x4007 0060)..................................................63
Register 7-9. GPIOBINTE (GPIO Port B Interrupt Enable, 0x4007 0064)............................................................64
Register 7-10. GPIOBINTF (GPIO Port B Interrupt Flag, 0x4007 0068)..............................................................64
Register 7-11. GPIOBINTM (GPIO Port B Interrupt Mask, 0x4007 006C)............................................................6
Register 8-1. GPIOCOUT (GPIO Port C Output, 0x4008 0000)...........................................................................68
Register 8-2. GPIOCOUTEN (GPIO Port C Output Enable, 0x4008 0004)..........................................................69
Register 8-3. GPIOCIN (GPIO Port C Input, 0x4008 0018)..................................................................................69
Register 8-4. GPIOCINE (GPIO Port C Input Enable, 0x4008 0014)...................................................................70
Register 8- . GPIOCINTP (GPIO Port C Interrupt Polarity, 0x4008 0020)...........................................................71
Register 8-6. GPIOCINTE (GPIO Port C Interrupt Enable, 0x4008 0024)...........................................................71
Register 8-7. GPIOCINTF (GPIO Port C Interrupt, 0x4008 0028)........................................................................72
Register 8-8. GPIOCINTM (GPIO Port C Interrupt Mask, 0x4008 002C).............................................................72
Register 9-1. GPIODO (GPIO Port D Output, 0x4008 0040)................................................................................76
Register 9-2. GPIODOUTEN (GPIO Port D Output Enable, 0x4008 0044)..........................................................77
Register 9-3. GPIODDS (GPIO Port D Output Drive Strength, 0x4008 0048)......................................................77
Register 9-4. GPIODPU (GPIO Port D Weak Pull Up, 0x4008 004C)..................................................................78
Register 9- . GPIODPD (GPIO Port D Weak Pull Down, 0x4008 00 0)..............................................................79
Register 9-6. GPIODIN (GPIO Port D Input, 0x4008 00 4)..................................................................................79
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Register 9-7. GPIODPSEL (GPIO Port D Peripheral Select, 0x4008 00 C)........................................................80
Register 9-8. GPIODINTP (GPIO Port D Interrupt Polarity, 0x4008 0060)...........................................................81
Register 9-9. GPIODINTE (GPIO Port D Interrupt Enable, 0x4008 0064)...........................................................81
Register 9-10. GPIODINTF (GPIO Port D Interrupt, 0x4008 0068)......................................................................82
Register 9-11. GPIODINTM (GPIO Port D Interrupt Mask, 0x4008 006C)...........................................................82
Register 10-1. GPIOEOUT (GPIO Port E Output, 0x4009 0000).........................................................................86
Register 10-2. GPIOEOUTEN (GPIO Port E Output Enable, 0x4009 0004)........................................................87
Register 10-3. GPIOEDS (GPIO Port E Output Drive Strength, 0x4009 0008)....................................................87
Register 10-4. GPIOEPU (GPIO Port E Weak Pull Up, 0x4009 000C)................................................................88
Register 10- . GPIOEPD (GPIO Port E Weak Pull Down, 0x4009 0010)............................................................89
Register 10-6. GPIOEIN (GPIO Port E Input, 0x4009 0014)................................................................................89
Register 10-7. GPIOEPSEL (GPIO Port E Peripheral Select, 0x4009 001C).......................................................90
Register 10-8. GPIOEINTP (GPIO Port E Interrupt Polarity, 0x4009 0020).........................................................91
Register 10-9. GPIOEINTE (GPIO Port E Interrupt Enable, 0x4009 0024)..........................................................91
Register 10-10. GPIOEINTF (GPIO Port E Interrupt Flag, 0x4009 0028)............................................................92
Register 10-11. GPIOEINTM (GPIO Port E Interrupt Mask, 0x4009 002C)..........................................................92
Register 11-1. RTCCTL (Real Time Clock Control, 0x4004 0000).......................................................................96
Register 11-2. RTCCDV (Real Time Clock Count-Down Value, 0x4004 0004)....................................................97
Register 11-3. RTCCTR (Real Time Clock Counter, 0x4004 0008)......................................................................97
Register 12-1. TACTL (Timer A Control, 0x400D 0000)......................................................................................100
Register 12-2. TAPRD (Timer A Period, 0x400D 0004)......................................................................................101
Register 12-3. TACTR (Timer A Counter, 0x400D 0008)....................................................................................101
Register 12-4. TACC0CTRL (Timer A PWMA0 Capture and Compare Control, 0x400D 0040)..........................101
Register 12- . TACC0CTR (Timer A PWMA0 Capture and Compare Counter, 0x400D 0044)..........................101
Register 12-6. TACC1CTRL (Timer A PWMA1 Capture and Compare Control, 0x400D 0048)..........................102
Register 12-7. TACC1CTR (Timer A PWMA1 Capture and Compare Counter, 0x400D 004C)..........................102
Register 12-8. TACC2CTRL (Timer A PWMA2 Capture and Compare Control, 0x400D 00 0)..........................102
Register 12-9. TACC2CTR (Timer A PWMA2 Capture and Compare Counter, 0x400D 00 4)..........................103
Register 12-10. TACC3CTRL (Timer A PWMA3 Capture and Compare Control, 0x400D 00 8)........................103
Register 12-11. TACC3CTR (Timer A PWMA3 Capture and Compare Counter, 0x400D 00 C)........................103
Register 12-12. TACC4CTRL (Timer A PWMA4 Capture and Compare Control, 0x400D 0060)........................103
Register 12-13. TACC4CTR (Timer A PWMA4 Capture and Compare Counter, 0x400D 0064)........................104
Register 12-14. TACC CTRL (Timer A PWMA Capture and Compare Control, 0x400D 0068)........................104
Register 12-1 . TACC CTR (Timer A PWMA Capture and Compare Counter, 0x400D 006C)........................104
Register 12-16. TACC6CTRL (Timer A PWMA6 Capture and Compare Control, 0x400D 0070)........................10
Register 12-17. TACC6CTR (Timer A PWMA6 Capture and Compare Counter, 0x400D 0074)........................10
Register 12-18. TACC7CTRL (Timer A PWMA7 Capture and Compare Control, 0x400D 0078)........................10
Register 12-19. TACC7CTR (Timer A PWMA7 Capture and Compare Counter, 0x400D 007C)........................106
Register 12-20. DTGA0CTL (Timer A Dead Time Generator 0 Control, 0x400D 00A0).....................................106
Register 12-21. DTGA0LED (Timer A Dead Time Generator 0 Leading Edge Delay, 0x400D 00A4).................106
Register 12-22. DTGA0TED (Timer A Dead Time Generator 0 Trailing Edge Delay, 0x400D 00A8)..................106
Register 12-23. DTGA1CTL (Timer A Dead Time Generator 1 Control, 0x400D 00B0).....................................107
Register 12-24. DTGA1LED (Timer A Dead Time Generator 1 Leading Edge Delay, 0x400D 00B4).................107
Register 12-2 . DTGA1TED (Timer A Dead Time Generator 1 Trailing Edge Delay, 0x400D 00B8)..................107
Register 12-26. DTGA2CTL (Timer A Dead Time Generator 2 Control, 0x400D 00C0).....................................107
Register 12-27. DTGA2LED (Timer A Dead Time Generator 2 Leading Edge Delay, 0x400D 00C4)................108
Register 12-28. DTGA2TED (Timer A Dead Time Generator 2 Trailing Edge Delay, 0x400D 00C8).................108
Register 12-29. DTGA3CTL (Timer A Dead Time Generator 3 Control, 0x400D 00D0).....................................108
Register 12-30. DTGA3LED (Timer A Dead Time Generator 3 Leading Edge Delay, 0x400D 00D4)................109
Register 12-31. DTGA3TED (Timer A Dead Time Generator 3 Trailing Edge Delay, 0x400D 00D8).................109
Register 13-1. TBCTL (Timer B Control, 0x400E 0000).....................................................................................117
Register 13-2. TBPRD (Timer B Period, 0x400E 0004)...................................................................................... 118
Register 13-3. TBCTR (Timer B Counter, 0x400E 0008)....................................................................................118
Register 13-4. TBCC0CTRL (Timer B PWMB0 Capture and Compare Control, 0x400E 0040).........................118
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PAC5223 User Guide
Power Application Controller
Register 13- . TBCC0CTR (Timer B PWMB0 Capture and Compare Counter, 0x400E 0044)..........................119
Register 13-6. TBCC1CTRL (Timer B PWMB1 Capture and Compare Control, 0x400E 0048).........................119
Register 13-7. TBCC1CTR (Timer B PWMB1 Capture and Compare Counter, 0x400E 004C)..........................119
Register 13-8. TBCC2CTRL (Timer B PWMB2 Capture and Compare Control, 0x400E 00 0).........................120
Register 13-9. TBCC2CTR (Timer B PWMB2 Capture and Compare Counter, 0x400E 00 4)..........................120
Register 13-10. TBCC3CTRL (Timer B PWMB3 Capture and Compare Control, 0x400E 00 8).......................120
Register 13-11. TBCC3CTR (Timer B PWMB3 Capture and Compare Counter, 0x400E 00 C)........................121
Register 13-12. DTGB0CTL (Timer B Dead Time Generator 0 Control, 0x400E 00A0).....................................121
Register 13-13. DTGB0LED (Timer B Dead Time Generator 0 Leading Edge Delay, 0x400E 00A4)................121
Register 13-14. DTGB0TED (Timer B Dead Time Generator 0 Trailing Edge Delay, 0x400E 00A8).................122
Register 14-1. TCCTL (Timer C Control, 0x400F 0000).....................................................................................130
Register 14-2. TCPRD (Timer C Period, 0x400F 0004).....................................................................................131
Register 14-3. TCCTR (Timer C Counter, 0x400F 0008)...................................................................................131
Register 14-4. TCCC0CTL (Timer C PWMC0 Capture and Compare Control, 0x400F 0040)...........................131
Register 14- . TCCC0CTR (Timer C PWMC0 Capture and Compare Counter, 0x400F 0044)..........................132
Register 14-6. TCCC1CTL (Timer C PWMC1 Capture and Compare Control, 0x400F 0048)...........................132
Register 14-7. TCCC1CTR (Timer C PWMC1 Capture and Compare Counter, 0x400F 004C).........................132
Register 14-8. DTGC0CTL (Timer C Dead Time Generator 0 Control, 0x400F 00A0).......................................133
Register 14-9. DTGC0LED (Timer C Dead Time Generator 0 Leading Edge Delay, 0x400F 00A4)..................133
Register 14-10. DTGC0TED (Timer C Dead Time Generator 0 Trailing Edge Delay, 0x400F 00A8).................133
Register 1 -1. TDCTL (Timer D Control, 0x4010 0000).....................................................................................141
Register 1 -2. TDPRD (Timer D Period, 0x4010 0004).....................................................................................142
Register 1 -3. TDCTR (Timer D Counter, 0x4010 0008)...................................................................................142
Register 1 -4. TDCC0CTRL (Timer D PWMD0 Capture and Compare Control, 0x4010 0040).........................142
Register 1 - . TDCC0CTR (Timer D PWMD0 Capture and Compare Counter, 0x4010 0044)..........................143
Register 1 -6. TDCC1CTL (Timer D PWMD1 Capture and Compare Control, 0x4010 0048)...........................143
Register 1 -7. TDCC1CTR (Timer D PWMD1 Capture and Compare Counter, 0x4010 004C).........................143
Register 1 -8. DTGD0CTL (Timer D Dead Time Generator 0 Control, 0x4010 00A0).......................................144
Register 1 -9. DTGD0LED (Timer D Dead Time Generator 0 Leading Edge Delay, 0x4010 00A4)..................144
Register 1 -10. DTGD0TED (Timer D Dead Time Generator 0 Trailing Edge Delay, 0x4010 00A8).................144
Register 16-1. FLASHLOCK (FLASH Lock, 0x4002 0000)................................................................................1 1
Register 16-2. FLASHCTL (FLASH Control and Status, 0x4002 0004).............................................................1 2
Register 16-3. FLASHPAGE (FLASH Page Selector, 0x4002 0008)..................................................................1 2
Register 16-4. FLASHPERASE (FLASH Page Erase, 0x4002 0014)................................................................1 3
Register 16- . SWDACCESS (SDW Access Status, 0x4002 0024)...................................................................1 3
Register 16-6. FLASHWSTATE (FLASH Access Wait State, 0x4002 0028).......................................................1 3
Register 16-7. FLASHBWRITE (Buffered FLASH Write, 0x4002 002C)............................................................1 3
Register 16-8. FLASHBWDATA (Buffered FLASH Write Data, 0x4002 0030)....................................................1 4
Register 17-1. EMUXCTL (ADC external MUX control register 0x401 0000)...................................................1 9
Register 17-2. EMUXDATA (EMUX data register 0x401 0004)........................................................................160
Register 17-3. ADCCTL (ADC control register 0x401 0008)............................................................................161
Register 17-4. ADCCR (ADC conversion result register 0x401 000C).............................................................161
Register 17- . ADCINT (ADC Interrupt register 0x401 0010)...........................................................................162
Register 17-6. AS0CTL (Auto Sequencer 0 control register 0x401 0040)........................................................163
Register 17-7. AS0S0 (Auto sequencer 0-sample 0 control 0x401 0044)........................................................164
Register 17-8. AS0R0 ( Auto sequencer 0-sample 0 result register 0x401 0048)............................................164
Register 17-9. AS0S1 (Auto sequencer 0-sample 1 control 0x401 004C)........................................................164
Register 17-10. AS0R1 ( Auto sequencer 0-sample 1 result register 0x401 00 0)..........................................16
Register 17-11. AS0S2 (Auto sequencer 0-sample 2 control 0x401 00 4).......................................................16
Register 17-12. AS0R2 ( Auto sequencer 0-sample 2 result register 0x401 00 8)..........................................16
Register 17-13. AS0S3 (Auto sequencer 0-sample 3 control 0x401 00 C)......................................................166
Register 17-14. AS0R3 ( Auto sequencer 0-sample 3 result register 0x401 0060)..........................................166
Register 17-1 . AS0S4 (Auto sequencer 0-sample 4 control 0x401 0064)......................................................166
Register 17-16. AS0R4 ( Auto sequencer 0-sample 4 result register 0x401 0068)..........................................167
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PAC5223 User Guide
Power Application Controller
Register 17-17. AS0S (Auto sequencer 0-sample control 0x401 006C)......................................................167
Register 17-18. AS0R ( Auto sequencer 0-sample result register 0x401 0070)..........................................167
Register 17-19. AS0S6 (Auto sequencer 0-sample 6 control 0x401 0074)......................................................168
Register 17-20. AS0R6 ( Auto sequencer 0-sample 6 result register 0x401 0078)..........................................168
Register 17-21. AS0S7 (Auto sequencer 0-sample 7 control 0x401 007C)......................................................168
Register 17-22. AS0R7 ( Auto sequencer 0-sample 7 result register 0x401 0080)..........................................169
Register 17-23. AS1CTL (Auto Sequencer 1 control register 0x401 0100)......................................................169
Register 17-24. AS1S0 (Auto sequencer 1-sample 0 control 0x401 0104)......................................................170
Register 17-2 . AS1R0 ( Auto sequencer 1-sample 0 result register 0x401 0108)..........................................170
Register 17-26. AS1S1 (Auto sequencer 1-sample 1 control 0x401 010C)......................................................171
Register 17-27. AS1R1 ( Auto sequencer 1-sample 1 result register 0x401 0110)...........................................171
Register 17-28. AS1S2 (Auto sequencer 1-sample 2 control 0x401 0114).......................................................171
Register 17-29. AS1R2 ( Auto sequencer 1-sample 2 result register 0x401 0118)...........................................172
Register 17-30. AS1S3 (Auto sequencer 1-sample 3 control 0x401 011C)......................................................172
Register 17-31. AS1R3 ( Auto sequencer 1-sample 3 result register 0x401 0120)..........................................172
Register 17-32. AS1S4 (Auto sequencer 1-sample 4 control 0x401 0124)......................................................173
Register 17-33. AS1R4 ( Auto sequencer 1-sample 4 result register 0x401 0128)..........................................173
Register 17-34. AS1S (Auto sequencer 1-sample control 0x401 012C)......................................................173
Register 17-3 . AS1R ( Auto sequencer 1-sample result register 0x401 0130)..........................................174
Register 17-36. AS1S6 (Auto sequencer 1-sample 6 control 0x401 0134)......................................................174
Register 17-37. AS1R6 ( Auto sequencer 1-sample 6 result register 0x401 0138)..........................................174
Register 17-38. AS1S7 (Auto sequencer 1-sample 7 control 0x401 013C)......................................................17
Register 17-39. AS1R7 ( Auto sequencer 1-sample 7 result register 0x401 0140)..........................................17
Register 18-1. I2CCFG (I2C Configuration, 0x401B 0000).................................................................................182
Register 18-2. I2CSTATUS (I2C Interrupt Status, 0x401B 0004)........................................................................182
Register 18-3. I2CIE (I2C Interrupt Enable, 0x401B 0008).................................................................................184
Register 18-4. I2CMCTRL (I2C Master Access Control, 0x401B 0030)..............................................................184
Register 18- . I2CMRXDATA (I2C Master Receive Data, 0x401B 0034)...........................................................18
Register 18-6. I2CMTXDATA (I2C Master Transmit Data, 0x401B 0038)...........................................................18
Register 18-7. I2CBAUD (I2C Baud Rate, 0x401B 0040)...................................................................................18
Register 18-8. I2CSLRXDATA (I2C Slave Receive Data, 0x401B 0070)............................................................18
Register 18-9. I2CSLTXDATA (I2C Slave Transmit Data, 0x401B 0074)............................................................186
Register 18-10. I2CADDR (I2C Slave Address, 0x401B 0074)...........................................................................186
Table 18-11. I2CBAUD settings for different HCLK............................................................................................ 187
Register 19-1. UARTRXTX (UART Receive/Transmit FIFO, 0x401D 0000)......................................................191
Register 19-2. UARTIER (UART Interrupt Enable, 0x401D 0004).....................................................................192
Register 19-3. UARTIIR (UART Interrupt Identification, 0x401D 0008)..............................................................192
Register 19-4. UARTLCR (UART Line Control, 0x401D 000C)..........................................................................193
Register 19- . UARTMCR (UART Modem Control, 0x401D 0010)....................................................................193
Register 19-6. UARTLSR (UART Line Status, 0x401D 0014)............................................................................193
Register 19-7. UARTSP (UART Scratch Pad, 0x401D 001C)............................................................................194
Register 19-8. UARTFCTL2 (FIFO Control, 0x401D 0020)................................................................................194
Register 19-9. UARTIER2 (UART Interrupt Enable, 0x401D 0024)...................................................................19
Register 19-10. UARTDL_L2 (UART Divisor Latch Low Byte, 0x401D 0028)....................................................19
Register 19-11. UARTDL_H2 (UART Divisor Latch High Byte, 0x401D 002C)..................................................19
Register 19-12. UARTFD_F (UART Fractional Divisor Value, 0x401D 0038)....................................................19
Register 19-13. UARTSTAT (UART FIFO Status, 0x401D 0040).......................................................................19
Register 19-14. UART Divisor Settings for 0 MHz HCLK.................................................................................198
Register 20-1. SOCBCTL (SOC Bus Bridge Control, 0x4020 0000)..................................................................200
Register 20-2. SOCBCFG (SOC Bus Bridge Configuration, 0x4020 0004).......................................................200
Register 20-3. SOCBCLK (SOC Bus Bridge Clock Divider, 0x4020 0008)........................................................201
Register 20-4. SOCBSTAT (SOC Bus Bridge Status, 0x4020 0014)..................................................................201
Register 20- . SOCBSTAT (SOC Bus Bridge Chip Select Steering, 0x4020 0018)...........................................202
Register 20-6. SOCBD (SOC Bus Bridge Data, 0x4020 001C)..........................................................................203
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PAC5223 User Guide
Power Application Controller
Register 20-7. SOCBINT_EN (SOC Bus Bridge Interrupt Enable, 0x4020 0020)..............................................203
Register 21-1. SPICTL (SPI Control, 0x4021 0000)........................................................................................... 206
Register 21-2. SPICFG (SPI Configuration, 0x4021 0004)................................................................................207
Register 21-3. SPICLKDIV (SPI Clock Divider, 0x4021 0008)...........................................................................208
Register 21-4. SPISTAT (SPI Status, 0x4021 0014)..........................................................................................208
Register 21- . SPICSSTR (SPI Chip Select Steering, 0x4021 0018)................................................................210
Register 21-6. SPID (SPI Data, 0x4021 001C)...................................................................................................211
Register 21-7. SPIINT_EN (SPI Interrupt Enable, 0x4021 0020).......................................................................211
Register 22-1. SYSSTAT (System Status, 0x00)................................................................................................217
Register 22-2. DEVID (Device Identification, 0x08)............................................................................................218
Register 22-3. VERID (Version Identification, 0x09)...........................................................................................218
Register 22-4. PWRCTL (Power Manager Control, 0x10)..................................................................................218
Register 22- . PWRSTAT (Power Manager Status, 0x11h, Persistent In Hibernate Mode)...............................219
Register 22-6. PSTATSET (Power Manager Setting, 0x12)...............................................................................219
Register 22-7. IMOD (Current Modulation, 0x13)...............................................................................................220
Register 22-8. SCFG (Switching Supply Configuration, 0x14)...........................................................................220
Register 22-9. SCFG2 (Switching Supply Configuration 2, 0x1 )......................................................................220
Register 23-1. SOC.SOC.CFGAIO0 (AIO0 Configuration, SOC 0x20)..............................................................223
Register 23-2. SOC.CFGAIO1 (AIO1 Configuration, SOC 0x21).......................................................................223
Register 23-3. SOC.SOC.CFGAIO2 (AIO2 Configuration, SOC 0x22)..............................................................22
Register 23-4. SOC.CFGAIO3 (AIO3 Configuration, SOC 0x23).......................................................................22
Register 23- . SOC.SOC.CFGAIO4 (AIO4 Configuration, SOC 0x24)..............................................................227
Register 23-6. SOC.CFGAIO (AIO Configuration, SOC 0x2 ).......................................................................227
Register 23-7. SOC.CFGAIO6 (AIO6 Configuration, SOC 0x26).......................................................................229
Register 23-8. SOC.CFGAIO7 (AIO7 Configuration, SOC 0x27).......................................................................230
Register 23-9. SOC.CFGAIO8 (AIO8 Configuration, SOC 0x28).......................................................................231
Register 23-10. SOC.CFGAIO9 (AIO9 Configuration, SOC 0x29).....................................................................232
Register 23-11. SOC.SIGSET (Signal Manager Configuration, SOC 0x2A).......................................................233
Register 23-12. SOC.HPDAC (HPDAC Setting, SOC 0x2B)..............................................................................233
Register 23-13. SOC.LPDAC0 (LPDAC Setting [9:2], SOC 0x2C).....................................................................233
Register 23-14. SOC.LPDAC1 (LPDAC Setting [1:0], SOC 0x2D).....................................................................233
Register 23-1 . SOC.ADCSCAN (ADCSCAN Configuration, SOC 0x2E).........................................................234
Register 23-16. SOC.ADCIN1 (AD Mux Selector, SOC 0x2F)...........................................................................234
Register 23-17. SOC.PROTINTM (Protection Interrupt Enable, SOC 0x30)......................................................234
Register 23-18. SOC.PROTSTAT (Protection Interrupt, SOC 0x31)..................................................................23
Register 23-19. SOC.DOUTSIG0 (AIO Digital Output, SOC 0x32)....................................................................23
Register 23-20. SOC.DOUTSIG1 (AIO Digital Output, SOC 0x33)....................................................................236
Register 23-21. SOC.DINSIG0 (AIO Digital Input, SOC 0x34)...........................................................................236
Register 23-22. SOC.DINSIG1 (AIO Digital Input 1, SOC 0x3 )........................................................................237
Register 23-23. SOC.SIGINTM (AIO6,7,8,9 Interrupt Enable, SOC 0x36).........................................................237
Register 23-24. SOC.SIGINTF (AIO6,7,8,9 Interrupt, SOC 0x37)......................................................................238
Register 23-2 . SOC.ENSIG (Signal Manager Control SOC 0x38)...................................................................238
Register 23-26. EMUX Packet Structure............................................................................................................ 26
Register 24-1. SOC.CFGDRV0 (Driver Configuration 0, SOC 0x60).................................................................268
Register 24-2. SOC.CFGDRV1 (Driver Configuration 1, SOC 0x61).................................................................268
Register 24-3. SOC.CFGDRQ6 (OHI6 Configuration, SOC 0x62).....................................................................269
Register 24-4. SOC.CFGDRQ7 (OHI6 Configuration, SOC 0x63).....................................................................269
Register 24- . SOC.DOUTDRV (OHI6/7, OM0/2/4 Output, SOC 0x64).............................................................270
Register 24-6. SOC.DINDRV (OHI6, OHI7 Input, SOC 0x6 )............................................................................270
Register 24-7. SOC.ENDRV (Application Specific Power Driver Control, SOC 0x66).......................................271
Register 24-8. SOC.ENBBM (Driver Break Before Make Control, SOC 0x67)...................................................271
Register 24-9. SOC.PROTCTL (Driver Protection Control, SOC 0x68).............................................................271
- 20 - Rev 18‒March 4, 2018