ADLINK Technology aTCA-3430 User manual
1
aTCA-3430
10GbE AdvancedTCA
Fabric Interface Switch
User's Manual
Manual Revision: 0.20 preliminary
Revision Date: Dec. 30, 2014
Part Number: 50-1G039-1000
Advance Technologies; Automate the World.
aTCA-3430 User's Manual
2
Revision History
Rev Date Description
0.10 2014/12/27 Preliminary release
0.20 2014/12/30 Update switch info, 10GbE port switching diagram
aTCA-3430 User's Manual
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Preface
Copyright 2014 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this
manual may be reproduced by any mechanical, electronic, or other means in any form without prior written
permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability,
design, and function and does not represent a commitment on the part of the manufacturer. In no event will
the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance
with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and
Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have
enforced measures to ensure that our products, manufacturing processes, components, and raw materials
have as little impact on the environment as possible. When products are at their end of life, our customers are
encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed
by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or
registered trademarks of their respective companies.
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Table of Contents
Revision History .................................................................................................................................... ii
Preface................................................................................................................................................... iii
List of Tables......................................................................................................................................... vi
List of Figures ....................................................................................................................................... vi
Abbreviations....................................................................................................................................... vii
1. Overview........................................................................................................................................... 9
1.1 Introduction................................................................................................................................ 9
1.2 Functional Block Diagram ...................................................................................................... 10
1.3 Package Contents ................................................................................................................... 10
2. Features and Specifications......................................................................................................... 11
3. External Interfaces ........................................................................................................................ 12
3.1 Front Panel............................................................................................................................... 12
3.2 Front Panel............................................................................................................................... 12
3.2.1 Serial Console Port................................................................................................................. 12
3.2.2 USB Port................................................................................................................................. 13
3.2.3 Management Ethernet Port .................................................................................................... 13
3.2.4 Service Ports .......................................................................................................................... 14
3.2.5 Reset Switch........................................................................................................................... 14
3.2.6 LEDs and Markers .................................................................................................................. 14
3.3 Zone 2 Backplane Interfaces.................................................................................................. 15
4. Getting Started............................................................................................................................... 16
4.1 Safety Requirements............................................................................................................... 16
4.2 Quick Start ............................................................................................................................... 17
4.2.1 Hardware Configuration Setting ............................................................................................. 17
Headers and Jumpers................................................................................................................... 18
DIP Switches................................................................................................................................. 21
Programmable Devices................................................................................................................. 22
4.2.2 Connecting to the Blade .........................................................................................................23
Connecting to the aTCA-3430 via COM port ................................................................................ 23
Connecting to the aTCA-3430 remotely ....................................................................................... 25
Boot into CLI for Base Switch Management ................................................................................. 26
Boot into CLI for Fabric Switch Management ............................................................................... 27
5. Software Setup/Update/Recovery................................................................................................ 28
5.1 U-Boot Installation .................................................................................................................. 28
5.1.1 Building U-Boot....................................................................................................................... 28
5.1.2 Updating U-Boot ..................................................................................................................... 28
5.2 BSP/Embedded Linux/BCM SDK Installation ....................................................................... 29
5.3 Redundant LMP Firmware & Boot ......................................................................................... 31
5.3.1 Boot Auto-Switch .................................................................................................................... 31
5.3.2 Boot Manual Switch................................................................................................................ 31
5.4 IPMI Firmware Update Procedure.......................................................................................... 32
5.4.1 Update over Serial Interface................................................................................................... 32
5.4.2 Update over LAN .................................................................................................................... 32
6. Configuring and Managing the Fabric Switch ............................................................................. 34
7. Advanced Operation ..................................................................................................................... 35
7.1 Switching I/O between Front Panel and Base Switch ......................................................... 35
7.2 Switch UART Serial Port between Front Panel and IPMC................................................... 36
8. Architecture Overview .................................................................................................................. 38
8.1 LMP Subsystem....................................................................................................................... 38
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8.1.1 Boot Image Redundancy ........................................................................................................ 38
U-Boot Redundancy...................................................................................................................... 38
8.1.2 LMP SDK/BSP Porting (U-Boot file system) .......................................................................... 40
8.1.3 Device Drivers ........................................................................................................................ 40
8.1.4 LMP State Machines............................................................................................................... 42
8.1.5 Boot Sequence ....................................................................................................................... 43
8.1.6 Non-volatile Memory Mapping................................................................................................ 44
8.2 Switch Subsystem................................................................................................................... 45
8.2.1 Broadcom SDK ....................................................................................................................... 45
I.................................................................................................................................................. 46
8.3 PMI Subsystem........................................................................................................................ 46
8.3.1 Platform Management Overview ............................................................................................ 46
8.3.2 Serial Over LAN (SOL) ...........................................................................................................46
8.3.3 IPMI Sensors .......................................................................................................................... 46
Sensor Reading (FRU Hot Swap Sensor) .................................................................................... 49
Get Sensor Reading (Physical IPMB-0 Sensor) ........................................................................... 49
Watchdog Timer Sensor ............................................................................................................... 50
Version Change Sensor................................................................................................................ 51
Get Sensor Reading Command.................................................................................................... 52
8.3.4 FRU Information ..................................................................................................................... 53
Board information area ................................................................................................................. 53
Product information area............................................................................................................... 53
Board E-key Information ............................................................................................................... 54
8.3.5 IPMI Commands ..................................................................................................................... 56
9. Software Component Overview ................................................................................................... 58
9.1 IPMI Subsystem....................................................................................................................... 58
9.2 LMP Subsystem....................................................................................................................... 59
9.3 Switch Subsystem................................................................................................................... 59
9.4 PacketManager ........................................................................................................................ 60
9.4.1 Features List ........................................................................................................................... 60
Safety .................................................................................................................................................... 61
Consignes de Sécurité........................................................................................................................ 62
Getting Service .................................................................................................................................... 63
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List of Tables
Table 1: aTCA-3430 Specifications ..................................................................................................................................... 11
Table 2. Serial Console Port Pinout .................................................................................................................................... 13
Table 3. Serial Console Port Configuration Values ............................................................................................................. 13
Table 4. RJ-45 Management Port Pinout ............................................................................................................................ 13
Table 5. Front Panel LEDs and Markers ............................................................................................................................. 15
Table 6. Ground Header Settings (JP3) .............................................................................................................................. 18
Table 7. XAUI_SEL Status Settings (JP5)........................................................................................................................... 19
Table 8. JTAGSEL Pin Definition (JP8)............................................................................................................................... 19
Table 9. SPI Flash or SD Card Selection (SW1) ................................................................................................................. 21
Table 10. Faceplate Serial Port Selection (SW2) ................................................................................................................ 21
Table 11. Multi-function Switch (SW3) ................................................................................................................................ 22
Table 12. Programmable Devices ....................................................................................................................................... 22
Table 13. Firmware Image and File Name .......................................................................................................................... 33
Table 14. LMP U-Boot Boot-up Failover Actions ................................................................................................................. 39
Table 15. Summary of Devices and Access........................................................................................................................ 41
Table 16. LMP State Descriptions ....................................................................................................................................... 42
Table 17. LMP State Transition Descriptions ...................................................................................................................... 43
Table 18. Boot Sequence State Descriptions ...................................................................................................................... 44
Table 19. Non-volatile Memory Map.................................................................................................................................... 44
List of Figures
Figure 1. aTCA-3430 Block Diagram................................................................................................................................... 10
Figure 2. Configurable Component Locations ..................................................................................................................... 17
Figure 3. Ground Header Schematic (JP3) ......................................................................................................................... 18
Figure 4. XAUI_SEL Status Header Schematic (JP5) ......................................................................................................... 18
Figure 5. JTAGSEL Mode Header Schematic (JP8) ........................................................................................................... 19
Figure 6. IPMC JTAG Header Schematic (JP9) .................................................................................................................. 20
Figure 7. CPLD JTAG Header Schematic (JP12)................................................................................................................ 20
Figure 8. Switching I/O between Front Panel and Base Switch .......................................................................................... 35
Figure 9. U-Boot Redundancy Flow .................................................................................................................................... 39
Figure 10. LMP SDK/BSP Porting ....................................................................................................................................... 40
Figure 11. LMP State Machine............................................................................................................................................ 42
Figure 12. aTCA-3430 Boot Sequence ............................................................................................................................... 43
Figure 13. Broadcom SDK Porting ...................................................................................................................................... 45
Figure 14. aTCA-3430 Software Overview.......................................................................................................................... 58
Figure 15. IPMI Function Blocks.......................................................................................................................................... 59
Figure 16. Broadcom SDK Function Blocks ........................................................................................................................ 60
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Abbreviations
Term Description
ASIC Application Specific Integrated Circuit
ATCA Advanced Telecom Computing Architecture
Base Interface ATCA Base Interface on Zone-2 connectors to connect to the dual hubs, 4 differential pairs
per Base Channel.
Blade A printed circuit board assembly that plugs into a chassis
BSP Board Support Package
Boot-flash Flash memory where the bootloader program is stored
Bootloader Code used to boot the System before loading OS
DDR Double Data Rate DRAM memory
DFT/DFM Design For Test/Manufacturing
DIMM Dual Inline Memory Module
ECC Error Correction Control
E-keying Standard defined by PICMG useful to verify whether the ATCA blade plugged in is compliant
to the fabric link capabilities
Fabric Interface ATCA Fabric Interface on the Zone-2 connectors to connect to the dual Switch Fabric Blades
Fabric Slot A slot supporting a link connection to/from each node slot
FRU Field Replaceable Unit
GPIO General Purpose Input/Output
Hot-swap Functions of replacing system components without shutting down the system
IPMB Intelligent Platform Management Bus
IPMB-L IPMB Local interface
IPMC Intelligent Platform Management Controller
IPMI Intelligent Platform Management Interface
JTAG Joint Test Action Group
MAC Media Access Controller
MMC Module Management Controller
NPU Network Processor Unit
OOS Out Of Service
PCI Peripheral Component Interconnect
PCIe Peripheral Component Interconnect-Express
PHY Physical Layer or Physical Layer Device
PICMG PCI Industrial Computer Manufacturers Group
RGMII Reduced Gigabit Medium Independent Interface
RTM Rear Transition Module
SDR Sensor Data Record
SDRAM Synchronous Dynamic Random Access Memory
SFP Small Form Pluggable (1G interface)
SFP+ Small Form Pluggable Plus (10G interface)
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Term Description
SGMII Serial Gigabit Medium Independent Interface
SOL Serial Over LAN
QSFP+ Quad Small Form Pluggable Plus (40G interface)
UART Universal Asynchronous Receiver-Transmitter
VLP Very Low Profile, DRAM Module Form Factor Spec
XLAUI 40 Gigabit (XL) Attachment Unit Interface
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1. Overview
1.1 Introduction
The aTCA-3430 is a high performance 10G Fabric switch blade for AdvancedTCA®platforms. This product is
ideal for bandwidth intensive telecom applications such as wireless access controllers, DPI/security network,
IPTV, IP multimedia subsystems, RNC/BSC, broadband access/bearer networks, data centers, and LTE/4G
network applications. The aTCA-3430 provides 10GbE hub-to-node connectivity and integrated switch silicon
that supports load balancing, priority queues, packet classification, and flow control to enable strict bandwidth
management for implemented applications.
In addition to a Fabric switch, the aTCA-3430 also incorporates a Base switch to provide PICMG 3.0 Gigabit
Ethernet backplane connectivity. The Base switch provides up to 13 ports of node slot connectivity to support
both 6 and 14-slot chassis in addition to 8 ports of front I/O, with 6 ports supporting 1GbE and 2 ports
supporting 10GbE. Other ports are used to provide connectivity to other components on the board such as the
Local Management Processor (LMP) and Intelligent Platform Management Controller (IPMC), and a
redundant switch slot supports connectivity with the redundant Base switch and shelf management. A
powerful quad-core LMP executes all switch functions, blade setup and hardware platform management
functions. Dual boot flash memory is provided for redundancy and a microSD card is provided for OS storage.
The ADLINK aTCA-3430 is equipped with the ADLINK PacketManager software package, which combines all
the essential features required for a fully functional switch infrastructure on ATCA platforms. This complete
package allows customers to focus on revenue-generating software development projects and provides the
flexibility to develop specific functions according to customer requirements.
aTCA-3430 User's Manual
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1.2 Functional Block Diagram
Fabric InterfaceBase Interface
Zone 1
RJ-45
RJ-45
IPMC
ShMC
1
ShMC
2
GbE
RS-232
10/100M
10/100M
GbE x1
IPMB-A
GbE x13
10GbE x9
SFP+
#1
SFP+
#9
PCIe x2
GbE x6
10GbE x13
IPMB-B
LED
UART (SOL)
USB 2.0
USB
RJ-45
#1
RJ-45
#6
UART (payload)
Base Switch
(BCM56334)
24x GbE
Fabric Switch
BCM56842 320G
GbE x1
4GB, DDR3 SDRAM
8GB, microSD card
2x 1MB, Boot Flash
LMP
UART (debug)
SFP+
#12
10GbE x1
MUX
DIP SW
SFP+
#11
10GbE x1
MUX
SFP+
#10
10GbE x1
Figure 1. aTCA-3430 Block Diagram
1.3 Package Contents
The aTCA-3430 is shipped with the components listed below. If any of the items in the contents list are
missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection.
Please obtain authorization before returning any product to ADLINK.
The packing contents of non-standard configurations may vary depending on customer requests.
aTCA-3430 AdvancedTCA Switch Blade
aTCA-3430 User's Manual
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2. Features and Specifications
Feature Function Description
Dimensions 322.25mm x 280mm x 6HP (L x W x H), AdvancedTCA single
slot
Processor Freescale QorIQ P2040(Quad Core) @ 1.0GHz
DRAM Memory 4GB DDR3 1333 Mini-RDIMM 1Rx8 VLP (512Mx8)
Boot Flash Memory 2x 8 Mbit SPI serial flash, redundant
LMP Subsystem
OS Flash Memory 8GB industrial grade microSD card
Data
Interconnection
Ethernet Switching BCM56842 320Gbps bandwidth 10GbE switch fabric with
QoS support
10GB Interface 12 x SFP+, 10 ports from Fabric switch, 2 ports from Base
switch
1GB Interface 6 x RJ-45
10/100/1000BASE-T
Management One RJ-45 from LMP
Serial Console (UART) One RJ-45 serial port connects to either LMP or IPMC
USB One USB 2.0 port
I/O Interface
Reset Button Recessed push button for blade reset
Base Interface Zone 2, supporting 13 ports 1000BASE-T Ethernet &
2 ports 10/100BASE-T Ethernet to ShMC, dual star
Fabric Interface Zone 2, PICMG 3.1 Rev 2.0 Fabric Interface switching –
Option1, 9, 9-K (10GBASE-KX4), 1-KR (one 10GBASE-KR)
Backplane
Connection
Power Interface Zone 1, -48VDC
Power Consumption 100W max.
Temperature Operating: +0°C to 50°C
Non-operating: -40°C to 70°C
Relative Humidity 5 - 95%, non-condensing
Shock Non-operating: 20G peak-to-peak, 11ms duration
Environmental
and Reliability
Vibration Operating: 0.5Grms 5-500Hz each axis
Non-operating: 1.88Grms, 5-500Hz each axis
Bootloader U-Boot (LMP)
BSP ADLINK BSP (LMP)
Operating System Open Linux OS
Development Environment Broadcom SDK running under Open Linux on LMP
ADLINK Shelf Management
in IPMI package
yHW management per ATCA PICMG 3.0; includes IPMI
management, FRU HW management, shelf environment
management (power, cooling, watchdog timer, E-keying),
and shelf sensor management
yIPMI over LAN (RMCP/IP) and Serial-Over-LAN per
PICMG 3.0
Software
ADLINK PacketManager
Software
yFull featured CLI/Telnet for controlling all switch features
yL2/L3 packet processing
yLoad balancing based on L2, L3, L4 switching protocol,
routing etc.
yACLs up to 7-tuple matching Layer 2-4 fields
yIP packet forwarding of IPv4, IPv6 and IP multicast
yVLAN, STP, link aggregation etc.
yAdditional protocols are available upon request
Table 1: aTCA-3430 Specifications
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3. External Interfaces
3.1 Front Panel
The face plate of the main blade has the following components:
zLED-OOS: Out Of Service indicator
zLED-Power Good: Power indicator
zLED-Health: Health indicator
zLED-HS: Hot-Swap indicator
zLED-Fabric Interface: Fabric Interface Link & Activity indicator
zLED-Base Interface: Base Interface Link & Activity indicator
zLED-Mgmt Link/Act: Management Port Link/ACT indicator
zLED-Mgmt Speed: Management Port Speed indicator
zLED-Service Ports Enable/Act: Service Port indicator
zConsole Port: Serial port to LMP or IPMC
zUSB Port: Connected to LMP
zManagement Ethernet Port: 10/100/1000BASE-T
zReset Button: System reset switch (recessed)
zService Ports #1~#12: SFP+ ports for data plane interface
zService Ports#1~#6: RJ-45 ports for data plane interface
3.2 Front Panel
3.2.1 Serial Console Port
One serial console port is provided via an RJ-45 shielded connector outlet, and is connected to the LMP,
which enables access to all major devices using command line interface commands for configuration and
monitoring. This port is also configured to be shared with the IPMC. Serial port configuration is RS-232
compatible including XON/XOFF, baud rate, stop, and start bit setting. The label for the serial console port is
noticeably different from the management Ethernet port to avoid ambiguity as they are both RJ-45 connectors
(the console port has no LEDs) . The pin-out of the serial interface RJ-45 connector is compatible to the Cisco
serial port pinout as shown in Table 2, and the configuration values are shown in Table 3.
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Pin Description
1 RTS
2 NC
3 TXD
4 GND
5 GND
6 RXD
7 NC
8 CTS
Table 2. Serial Console Port Pinout
Item Value
Baud rate 115200
Data 8-bit
Parity None
Stop bit 1-bit
Flow control None
Table 3. Serial Console Port Configuration Values
3.2.2 USB Port
A single USB port is available on the face plate, which is connected to the LMP. The P2040 supports 2x USB
compliant to USB specification Rev 2.0. On the board, USB2 is routed to the faceplate USB connector. USB1
is not used.
3.2.3 Management Ethernet Port
Seven RJ-45 Ethernet ports are provided on the front panel. One 10/100/1000BASE-T port is connected
directly to the LMP for easy debugging/testing (such as a simple connection to a different subnet console by
configuring an IP address for the port without involvement of the blade switch). The label for the management
Ethernet port is noticeably different from the serial conole port to avoid ambiguity as they are both RJ-45
connectors (the management Ethernet port has Link/Act LEDs)
Pin # 1000BASE-T
1 BI_DA+
2 BI_DA-
3 BI_DB+
4 BI_DB-
5 BI_DC+
6 BI_DC-
7 BI_DD+
8 BI_DD-
Table 4. RJ-45 Management Port Pinout
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3.2.4 Service Ports
Traffic service ports are provided with RJ-45 and SFP+ outlets. Either a fiber optic cable or a copper cable
with a mating SFP+ connector can be used to connect the blade with remote blades or appliances. The SFP+
ports support IEEE 802.3ae (Clause 52) and IEEE 802.3aq (Clause 68).
3.2.5 Reset Switch
The front panel reset switch is a global reset switch for the blade. When pushed, a payload reset event is sent
to the IPMC to begin corresponding initialization procedures.
3.2.6 LEDs and Markers
Various LEDs for system status monitoring are available from the faceplate. Shown in Table 5 are the LEDs
and their descriptions.
Name Marker Display Description
Blue Solid DC-DC Power OFF(M1)
Blue Short Blink Hot swap Operation(M5/M6)
Blue Long Blink Hot swap Operation(M2)
HS LED
OFF Normal Operation(M3/M4)
Red Solid Out of Service(M1)
Red Blink Out of Service or Service
Preparation (M5/M6)
OOS LED
OFF Normal Operation(M3/M4)
Green Solid Power GOOD
Power Good LED OFF Power Fail
Amber Solid Health Check
Health LED APP OFF Normal Operation
Green Solid MGMT Link ON
Green Blink MGMT Link ON & Activity
Mgmt Link/Act LED OFF MGMT Link OFF
Yellow Solid 1G speed Indicator
Mgmt Speed LED OFF 10/100Mbps Speed Indicator
Green Solid/Blink Link ON & Activity
OFF Link OFF
Yellow Solid 1G speed Indicator
Base Service Port
LED
OFF 10/100Mbps Speed Indicator
Green Solid 1G or 10G Link ON
EOFF Link OFF
Green Blink 1G or 10G Activity
Fabric Service Port
LED L/A OFF No Activity
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Name Marker Display Description
Console Port N/A Section 3.1.1
USB Port N/A Section 3.1.2
MGMT Port N/A Section 3.1.3
Table 5. Front Panel LEDs and Markers
3.3 Zone 2 Backplane Interfaces
ATCA specifications define Zone 2 for Fabric, Base and update channel interface interconnections. The Base
Interface port is compliant to 1000BASE-T Ethernet. Thirteen Base Interface ports from the backplane are
connected to the Ethernet switch in the blade. Through the switch, the Base Interface traffic goes to the LMP
for necessary processing. The Fabric Interface on the aTCA-3430 blade can connect to up to thirteen boards
in the chassis. The thirteen Fabric Interface ports are connected to the high capacity onboard Ethernet switch,
where the port speed is configurable to 1Gbps/10Gbps in the form of 4 SerDes lanes at 2.5Gbps each or 1
SerDes lanes at 10Gbps, each compliant with Option 1/9, 10GBase-KX4 or 10GBase-KR respectively.
aTCA-3430 User's Manual
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4. Getting Started
The aTCA-3430 has been designed for easy installation. However, the following standard precautions,
installation procedures, and general information must be observed to ensure proper installation and to
preclude damage to the board, other system components, or injury to personnel.
4.1 Safety Requirements
The following safety precautions must be observed when installing or operating the aTCA-3430. ADLINK
assumes no responsibility for any damage resulting from failure to comply with these requirements.
Do not touch the heatsink when installing or removing the board. The board should not be placed on any
surface or in any form of storage container until the board and heat sink have cooled down to room
temperature.
This ATCA blade contains electrostatic sensitive devices. Please observe the necessary precautions to avoid
damage to your board:
Discharge your clothing before touching the assembly. Tools must be discharged before use.
Do not touch components, connector-pins or traces.
If working at an anti-static workbench with professional discharging equipment, please do not omit to
use it.
aTCA-3430 User's Manual
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4.2 Quick Start
4.2.1 Hardware Configuration Setting
For normal operation, it is not recommended to change any onboard hardware configuration settings, but
there are some options on the board for those want to investigate more flexibility for testing. Figure 2
illustrates the locations of the configurable components.
Figure 2. Configurable Component Locations
JP3
SW3
SW2
SW1
aTCA-3430 User's Manual
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Headers and Jumpers
•Ground Connection (JP3): This header is used to short GND and GND_SHELF on the board.
The default setting is Pin 1 and Pin 2 shorted.
BC892
C1000P2KV6MX7
JP3
PH-1*3-2D54-D-ST-ML-6/3
1
2
3
GND_SHELF
Figure 3. Ground Header Schematic (JP3)
GND Connection JP3
Short GND and Chassis GND
by capacitor
GND not shorted
Table 6. Ground Header Settings (JP3)
•XAUI_SEL Status (JP5): This header is a reserved hardware switch. The default configuration of
XAUI_SEL status is set by IPMC through keying in instructions.
P1V5_IPMC
XAUI_SEL_JP
XAUI_SEL_1V5
JP5
PH-1*3-2D54-D-ST-ML-6/3
1
2
3R3346 4K7R2F
R889 0R2NI
XAUI_SEL_P2041
XAUI_SEL_JP
XAUI_SELXAUI_SEL_IPMC R897 0R2
R890 0R2NI
Figure 4. XAUI_SEL Status Header Schematic (JP5)
321
3 2 1
aTCA-3430 User's Manual
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Pin Description
1 BCM56842 connects to BCM56334 (HiGig)
0 BCM56842 connects to aDB3710 (BCM8706)
Table 7. XAUI_SEL Status Settings (JP5)
•IPMC JTAGSEL Mode (JP8): This header is used to select either FPGA Fabric TAP or Cortex-M3
JTAG debug. The default setting is FPGA Fabric TAP.
P3V3_PRE
R3360
4K7R2F
JP9
PH-1*2-2D54-D-ST-ML
1
2
R16
R3361
4K7R2F
JTAGSEL
A2F500M2G-FGG484
Figure 5. JTAGSEL Mode Header Schematic (JP8)
Name Type Polarity/Bus Size Description
JTAGSEL In 1 JTAG controller selection
Depending on the state of the JTAGSEL pin,
an external JTAG controller will either see the
FPGA fabric TAP/auxiliary TAP (High) or the
Cortex-M3 JTAG debug interface (Low).
The JTAGSEL pin should be connected to an
external pull-up resistor such that the default
configuration selects the FPGA fabric TAP.
Table 8. JTAGSEL Pin Definition (JP8)
aTCA-3430 User's Manual
20
•IPMC JTAG (JP9): This header is used to program the IPMC bit file using a JTAG cable.
IPMC _J TAG_TD O
IPMC _J TAG_TMS
IPMC _J TAG_TD I
VJTAG
JP9
PH-2*5-2D54-D-ST-ML-6/3-JVE
1 2
3 4
5 6
7 8
910
R862
0R2
P3V3_PRE
R86810KR2F
R13
1KR2F
NI
R873
10KR2F
NI
VPUMP
IPMC _J TAG_TC K
IPMC_JTAG_nTRST
R861
0R2
Figure 6. IPMC JTAG Header Schematic (JP9)
•JTAG Header (JP12): This header is used to reprogram the CPLD bit file using a JTAG cable.
Figure 7. CPLD JTAG Header Schematic (JP12)
P3V3_PRE
CPLD_TMS
CPLD_TDI
JP12
PH-2*5-2D54-D-ST-ML-6/3-JVE
12
34
56
78
910
BC835
CD1U16V2KX7
CPLD_TDO
CPLD_TCK
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