
PCI-1243U User Manual vi
3.2.2 Motion I/O Configuration Page ................................................... 23
Figure 3.5:Motion I/O Configuration .......................................... 23
3.2.3 Home Configuration Page ........................................................... 24
Figure 3.6:Home Configuration .................................................. 24
Figure 3.7:Save and Load Configuration Files ........................... 25
3.3 Motion Operations ...................................................................... 25
3.3.1 Testing Motion Movement .......................................................... 25
3.3.2 Point to Point Movement ............................................................. 26
Figure 3.8:Point to Point Movement ........................................... 27
3.3.3 Home Function ............................................................................ 28
Figure 3.9:Home Function .......................................................... 28
3.3.4 Digital I/O Operation ................................................................... 29
Figure 3.10:Digital I/O Operation ............................................... 29
Chapter 4 Register Programming ..................................... 32
4.1 Motion Control Registers ........................................................... 32
4.1.1 R0: Preset Pulse Counter (24 bits) .............................................. 32
4.1.2 R1: FL Speed Register (13 bits) .................................................. 33
4.1.3 R2: FH Speed Register (13 bits) .................................................. 33
Figure 4.1:R4’s Effect on Output Pulse Speed ............................ 33
4.1.4 R3: Accel/decel Rate Register (10 bits) ...................................... 34
Figure 4.2:R3’s Effect ................................................................. 34
4.1.5 R4: Multiplier Register (10 bits) ................................................. 35
4.1.6 R5: Ramping-Down Point Register (16 bits) .............................. 36
Figure 4.3:Setting the Ideal Ramping-Down Point ..................... 37
Figure 4.4:Pulse Calculation ....................................................... 38
4.1.7 R6: Idling Pulse Register (3-bit) ................................................. 39
4.1.8 R7: Environmental Data Register (1-bit) .................................... 39
4.2 Programming PCI-1243U........................................................... 40
4.2.1 I/O Control Register Map: ........................................................... 40
4.2.2 Command Buffer Register Format .............................................. 44
4.3 Command Modes........................................................................ 45
4.3.1 Start-Stop Commands .................................................................. 45
4.3.2 Operation Mode Select Command .............................................. 47
4.3.3 Register Select Command ........................................................... 48
4.3.4 Output Mode Select Command ................................................... 50
4.4 Status Registers........................................................................... 51
4.4.1 Status0: Channel Status Buffers (RD0, RD4, RD8 and RD13) .. 52
4.4.2 Extension Monitor ....................................................................... 52
4.5 General I/O Registers ................................................................. 54
4.5.1 Base+10h: Read Board ID ........................................................... 54
4.5.2 Base+11h: Read/Write IDO Port ................................................. 54
4.5.3 Base+12h: Read/Write IDI Port .................................................. 54
4.5.4 Base+13h: R/W IDI Port Trigger Control Register ..................... 55
4.5.5 Base+14h: IRQ Control/Enable Register Low Byte ................... 55
4.5.6 Base+15h: IRQ Control/Enable Register High Byte ................... 55
4.5.7 Base+16h: IRQ Status Low Byte ................................................ 56
4.5.8 Base+17h: IRQ Status High Byte ................................................ 56