Alcatel MTK-40131 User manual

Key features
▼Digitally programmed
transmission and signalling
characteristics meets
world-wide specification
requirements
▼Integrated ringing, sine or
trapezoid
▼Metering injection
▼Battery reversal
▼Tone generators for signalling
and test
▼Minimal external components
▼CODEC and SLIC functions for
2 lines
▼Low-cost POTS interface for
short range
▼Standard GCI interface
Applications
▼Advanced ISDN NT (NTplus)
▼Analog / Digital PABX
▼Cable Telephone systems
(set-top box)
▼Remote telephone access
systems
Fibre to the curb
Radio in the loop
▼Internet telephones
MTC-20232 CODSP
MTC-30132 SH LIC
MTK-40131
SH POTS chipset
Rev. 1.31 - December 1998
Data Sheet and
User Manual
Fig. 1: Application Sketch / Block Diagram
General Description
The MTK-40131 chipset provides all
the functions necessary to connect ana-
log telephone sets or other analog ter-
minals (telefax, answering machines,
modems etc...) into digital communica-
tion systems. It provides an economical
solution for the traditional ‘BORSHT’
functions found in central-office
exchanges, but optimised for short-
range communication (e.g. up to 500m
with 4 RENs attached). Virtually all sys-
tem-dependent parameters can be set
under software control, giving a hither-
to unprecedented flexibility to the sys-
tem integrator, as well as optimising the
system cost. The digital interface to the
SH POTS chipset uses the industry-stan-
dard “GCI”* interface. The system
architecture has been designed to offer
the most cost-effective solution for short-
haul systems, yet offers the full flexibility
required to meet world-wide analog
telephony standards. Suitable for
Q.552 applications.
The MTK-40131 chipset comprises three
devices (see fig 1.): A pair of high-volt-
age device, the Short-Haul Line Interface
Circuit (SH LIC) which provides the sig-
nal and power interface to the analog
lines (one per line) and a low-voltage
CMOS, DSP-based dual CODEC/con-
trol device (CODSP) which provides all
signal processing and control functions
for up to two lines.
(* The General Circuit Interface (GCI) is an interface specification,
developed jointly by Alcatel, Italtel, GPT and Siemens;
date March 1989; issue 1.0)
Ordering Information
Part number Package Code Temp
MTK-40131-C Includ.MTC-20232PQ-C 44 pinPQFP PQ44 0 to -70°C
2x MTC-30132SO-C 28 pinSO SO28 0 to -70°C
MTK-40131-I Includ.MTC-20232PQ-I 44 pinPQFP PQ44 -40/+85°C
2x MTC-30132SO-I 28 pinSO SO28 -40/+85°C

2
MTK-40131
MTC-30132
SH LIC
28 PSOP
GNDB
AW
BW
SA
BAT
SB
BATS
SSB
BATR
DCO
PU
DCI
NC
NC
NC
NC
RNG
DCC
BR
TX
TST
RX
VAG
DCLF1
VDDA
DCLF2
GNDA
V3V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Package / Pinout
Fig. 2: Device Pinouts
MTC-20232
CODSP
44 PQFP
PU[0]
SPDI
SPICS
SPICK
SPIDO
PWRS
RNG[0]
TST[0]
BR[0]
TEST
ZOUT
JTDO
JTCK
JTMS
JTDI
JTRS
V3VD
DU
DD
DCL
FSC
GNDD
AD2
AD1
AD0
GCIM
TST[1]
BR[1]
RNG[1]
PU[1]
SCLK
PLLCK
CPLL
RX[0]
TX[0]
DCC[0]
DCO[0]
DCC[1]
DCO[1]
GNDA
VAG
V3VA
TX[1]
RX[1]
2
3
4
5
6
7
8
9
10
11
17
13
14
15
16
18
19
20
21
22
40
44
43
42
41
39
38
37
36
35
33
32
31
30
29
28
27
26
25
24

3
MTK-40131
Table of Content
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Note on Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Characteristics of the SH POTS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-hook Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ringing Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Battery Voltage and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Transmission Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmit and Receive Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Source Impedance (Zco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Balance Impedance (Echo Canceller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Off-hook Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Metering Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CODSP Clock Recovery PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
User-Defined I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal Shutdown SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Transient Energy Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC Characteristics (MTC-30132 SHLIC, unless otherwise noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
V3V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AW, BW DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RX, TX DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DCO DC- Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VAG Analog Ground Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SA,SB Sense Bridge Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DCC Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Characteristics for the Digital I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Battery Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC Characteristics (SHLIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Overpower and Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4
MTK-40131
Quality / Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Detailed Programming Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
C/I Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
C/I Bit Allocation:C/I Bit Allocation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ID Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Memory Map of the CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Global Memory Map and MemID Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
CoProcessor Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
SHARED Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Meaning and Default Values of the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General dimensions of the MTC-20232PQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General dimensions of the MTC-30132SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

5
MTK-40131
List of Figures
Fig. 1: Application Sketch / Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Fig. 2: Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Fig. 3: Application schematic for 2 analog lines (see Table 3 for component values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Fig. 4: MTC-20132 CODSP Recommended Power-Supply Decoupling Arrangements . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Fig. 5: Recommended overvoltage protection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fig. 6: SH POTS Line voltages - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Fig. 7: Nominal hook-switch detection thresholds (default values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fig. 8: DC Feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fig. 9: Transmit and receive frequency response (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fig. 10: Relative Group delay, transmit and receive paths (Digital to Digital) refered to 1kHz . . . . . . . . . . . . . . . . . . . . . . 18
Fig. 11: 3-element Zco model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Fig. 12: Metering pulse timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Fig. 13: Application suggestion for Semi-unbalanced ringing injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Fig. 14: Block diagram showing the gains in the various signal paths in the SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fig. 15: Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fig. 16: GCI data exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig. 17: GCI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6
MTK-40131
List of Tables
Table 1: Pin description for MTC-20232PQ CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2: Pin description for MTC-30132SO SH LIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3: Recommended external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4: MTC-20232 CODSP unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5: MTC-30132 SH LIC unused pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6: Table 6: On-hook Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7: Ringing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8: DC Feed Characteristics (Rfeed = 60Ωtotal (50Ω+10Ωprotection) x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9: Examples of ZCO Coëfficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10: Off-hook Characteristics (MTK-40131 System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11: Metering Characteristics (Determinized by MTC-20232 CODSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12: Tone signal levels (common values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13: Tone Generator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14: Tone generator division values for common frequencies from ETS-300-001, and DTMF tones . . . . . . . . . . . . . . . 24
Table 15: Required frequency setting values (N) for a melody generator (western equal-tempered scale) . . . . . . . . . . . . . . 25
Table 16: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18: SHLIC Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19: Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20: Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21: V3V Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22: Voltage Characteristics A Wire, B Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23: Impedance Characteristics A Wire, B Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24: RX, TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25: DCO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 26: VAG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 27: Sense Bridge Inputs Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 28: DC Loop Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 29: DCC Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 30: Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 31: Test Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 32: Ringing Battery Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 33: Typical Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 34: Short Circuit Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 35: GCI Mode and Timeslot address programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 36: GCI Interface: Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 37: Memory Map for CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 38: Data RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 39: LBO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 40: Data RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 41: Coprocessor Coefficient RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 42: Coprocessor Coefficient RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 43: Shared Memory: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 44: Shared Memory: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7
MTK-40131
Pin Description
Pin Name Description
1 JTDO JTAG Test port data out
2 JTCK JTAG Test port clock
3 JTMS JTAG Test port mode select
4 JTDI JTAG Test port Data In
5 JTRS JTAG Test port reset
6 V3VD Digital section supply voltage
7 DU GCI port upstream data
8 DD GCI port downstream data
9 DCL GCI port data clock
10 FSC GCI port frame clock
11 GNDD Digital ground (0V)
12 AD2 GCI port timeslot select, MSB
13 AD1 GCI port timeslot select
14 AD0 GCI port timeslot select, LSB
15 GCIM GCI port operating mode (0 = 1 timeslot, 1 = 8 timeslots)
16 TST[1] SH LIC 1 test select
17 BR[1] SH LIC 1 Bat Reverse control
18 RNG[1] SH LIC 1 Ring control
19 PU[1] SH LIC 1 Power-up control
20 SCLK system clock (test only)
21 PLLCK PLL clock (test only)
22 CPLL PLL loop filter capacitor
23 RX[1] SH LIC 1 RX analog signal
24 TX[1] SH LIC 1 TX analog signal
25 V3VA Analog supply voltage
26 VAG Analog ground reference voltage output
27 GNDA Analog ground (0V)
28 DCO[1] SH LIC 1 DC loop output
29 DCC[1] SH LIC 1 DC loop control
30 DCO[0] SH LIC 0 DC loop output
31 DCC[0] SH LIC 0 DC loop control
32 TX[0] SH LIC 0 TX analog signal
33 RX[0] SH LIC 0 RX analog signal
34 ZOUT Digital I/O drive control (test only)
35 TEST Test mode select (test only)
36 TST[0] SH LIC 0 test select
37 BR[0] SH LIC 0 Bat Reverse control
38 RNG[0] SH LIC 0 Ring control
39 PU[0] SH LIC 0 Power-up control
40 SPIDI SPI port data in (User I/O)
41 SPICS SPI port chip-select (User I/O)
42 SPICK SPI port clock (User I/O)
43 SPIDO SPI port data out (User I/O)
44 PWRS Reset input
Table 1: Pin description for MTC-20232PQ CODSP

8
MTK-40131
Table 2: Pin description for MTC-30132SO SH LIC
Pin Name Description
1 GNDB Battery ground (0V)
2 BW B wire output
3 BAT Battery voltage (output, do not connect)
4 BATS Battery voltage input, SPEECH mode
5 BATR Battery voltage input, RING mode
6 PU Power-up control
7 NC Do not connect. Thermal conduction pin
8 NC Do not connect. Thermal conduction pin
9 RNG Ring mode control
10 BR Battery Reverse control
11 TST Test mode control
12 VAG Analog Ground reference input
13 VDDA Analog supply voltage
14 GNDA Analog Ground, 0V
15 V3V 3V regulator output
16 DCLF1 DC bias filter capacitor 1
17 DCLF2 DC bias filter capacitor 2
18 RX Analog receive signal
19 TX Analog transmit signal
20 DCC DC loop control input
21 NC Do not connect. Thermal conduction pin
22 NC Do not connect. Thermal conduction pin
23 DCI DC loop control separation filter input
24 DCO DC loop control output
25 SSB Loop test resistor switch
26 SB B-wire sense input
27 SA A-wire sense input
28 AW A-wire output

9
MTK-40131
Application Schematic
CODSP
SH LIC
SA
AW
SSB
BW
SB
BATS
BATR
VDDA
GNDB
DCLF1
DCLF2
GNDA
V3V
TST[0]
BR[0]
RNG[0]
PU[0]
RX
TX
DCC
DCO
DCI
VAG
Vbats
Vbatr
VddA
Cvag
Cdci
CV3VD
Cb1
Cb2
RB2
RB1
Ztest
Cf1
Cf2
Cs
Cd
protection
LINE
a
b
RX[0]
TX[0]
DCC[0]
DCO[0]
VAG
TST
BR
RNG
PU
SH LIC
SA
AW
SSB
BW
SB
BATS
BATR
VDDA
GNDB
DCLF1
DCLF2
GNDA
V3V
TST[1]
BR[1]
RNG[1]
PU[1]
RX
TX
DCC
DCO
DCI
VAG
Vbats
Vbatr
VddA
Cdci
CV3VA
Cb1
Cb2
RB2
RB1
Ztest
protection
LINE
a
b
RX[1]
TX[1]
DCC[1]
DCO[1]
TST
BR
RNG
PU
CPLL
Cpll
GNDD
GNDA
V3VD
SPIDI
SPIDO
SPICS
SPICK
PLLCK
GCIM
DU
DD
FSC
DCL
AD0
AD1
AD2
GCI mode
and timeslot
address
GCI port
User
Outputs
(optional)
JTDI
JTDO
JTCK
JTMS
JTRS
TEST
ZOUT
JTAG test
access
Device
test
Cpwrs
PWRS
V3VD
Rpwrs
0
0
0
1
0
0
-
0
0,1
0,1
0,1
0,1
V3VD
BAT
BAT
Dp
SCLK
0
Rf1
Rf2
Cf1
Cf2
Rf1
Rf2
Rprot
Rprot
CV3VA
Dp
Dp
D1
Fig. 3: Application schematic for 2 analog lines (see Table 3 for component values).

10
MTK-40131
Table 3: Recommended external components
Component Function Value Comment
RB1, RB2 Feed resistor 50Ω1/4 W ±1% *
Rprot Protection resistance 2x10Ω
Ztest Test resistor 510Ω1/4 W, optional
Rf1, Rf2 DC bias filter 10kΩ
Cb1, Cb2 No-load stabilisation 1nF 100V **
Cdci DC feed separation 330nF 5%
Cf1,Cf2 DC bias filter 470nF 100V, 10%
Cvag Analog ground decoupling 100nF
CV3VA Analog 3,3V regulator decoupling 10µF+100nF
CV3VD Digital 3,3V decoupling 10µF+100nF
Cs, Cd Battery supply decoupling 100nF 100V
Cpll PLL loop filter 4.7nF
Cpwrs Power-on reset delay 100nF
Rpws Power-on reset delay 100kΩ
D1 Power loss reset Any small signal diode
Dp Battery input protection BAT46 Required depending on
the power supplies
* ±1% results in a maximum longitudinal balance of 40dB. For higher values, more
precise matching is required (e.g. ±0.1% for 46dB).
** Capacitors are generally not required. They are foreseen to stabilise the line dri-
ver outputs when active but driving no load (test condition only).

11
MTK-40131
Table 4: MTC-20232 CODSP unused pin connectionsUnused Pins
CODSP:
Pins which are not used in the applica-
tion should be connected as described
here. Failure to do so could result in
excessive sensitivity to RFI, or other
erratic behaviour. ‘0’ or ‘1’ indicates
that the pin should be connected to
ground or to the device’s digital supply.
‘-’ indicates that the pins is an output
and must be left unconnected.
Pin # Connect to
SPDO 43 -
GCIM 15 0,1 (GCI mode select)
AD0 14 0,1 (GCI timeslot select)
AD1 13 0,1 (GCI timeslot select)
AD2 12 0,1 (GCI timeslot select)
JTDI 4 0
JTDO 1 -
JTCK 2 0
JTMS 3 0
JTRS 5 1
SCLK 20 0
PLLCK 21 0
ZOUT 34 0
TEST 35 0
Table 5: MTC-30132 SH LIC unused pin connections
Pin # Connect to
BAT 3 No Connect or see text below
NC 7 No Connect or see text below
NC 8 No Connect or see text below
NC 21 No Connect or see text below
SHLIC:
The pins NC (7, 8, 21 and 22) are
connected to the device substrate,
which is at a voltage equal to the
VBATR supply pin, and may optionally
be electrically connected to this pin.
The pin BAT is the internal supply to the
line-drivers, and adopts the voltage of
VBATR or VBATS, plus the voltage drop
across the internal switch, depending
on the operating mode. In low-voltage
only systems (very short connections,
the pins BAT, VBATR and VBATS may
all be connected together, and a single
supply (e.g. -27V) used for both ringing
and speech modes. (In this mode, the
voltage drop of the internal switches is
avoided).

12
MTK-40131
Note on Decoupling
As in any system, the PCB layout and
supply decoupling can influence the
system performance, particularly with
respect to noise.
CODSP:
• It is recommended to connect V3VD
and V3VA (digital and analog sup-
ply pins) in a star configuration from
the supply (either from the SH LIC or
an external supply), and each pin be
independently decoupled using 10µF
in parallel with 100nF.
In 2-line systems using the SHLIC’s
regulator to supply the CODSP only
(i.e. no other use is made of the regu-
lator), one SHLIC may be used to
provide V3VD power and the other
V3VA, thus giving improved decou-
pling between analog and digital
supplies. See figure 4.
• The VAG line (analog signal refer-
ence) must always be properly
decoupled using 100nF, placed as
close as possible to the CODSP
device.
SHLIC:
• The SHLIC should use separate
100nF decoupling capacitors
between VDD and GNDB and VDD
and GNDA. When the on-board reg-
ulator of the SHLIC is not used, no
capacitor is required at the V3V pin
of this device.
MTC-30132
SH LIC
MTC-30132
SH LIC
MTC-20132
CODSP
GNDD
V3VD
GNDA
V3VA
VAG
+3.3V Star point
Ground
star-point
GNDA
GNDB
GNDA
GNDB
MTC-30132
SH LIC
MTC-30132
SH LIC
MTC-20132
CODSP
GNDD
V3VD
GNDA
V3VA
VAG
Ground
star-point
GNDA
GNDB
GNDA
GNDB
V3V
V3V
10 µF Ta
100 nF Cer
Fig. 4: MTC-20132 CODSP Recommended Power-Supply
Decoupling Arrangements

RB1
Rpr1
RB2
Rpr2
BATR
GNDB
AW
SA
SB
BW
MTC-30132
SH LIC
RB1
Rpr1
RB2
Rpr2
GNDB
AW
SA
SB
BW
MTC-30132
SH LIC
RB1
Rpr1
RB2
Rpr2
GNDB
AW
SA
SB
BW
MTC-30132
SH LIC
RB1
Rpr1
RB2
Rpr2
GNDB
AW
SA
SB
BW
MTC-30132
SH LIC
Transient
Suppressor
13
MTK-40131
Overvoltage Protection
There are several recommended over-
voltage protection options. The applica-
tion will determine the most appropriate
one to chose (e.g. in-house only systems
with minimal protection requirements,
or systems with loops outside a protect-
ed environment requiring more extend-
ed protection).
The first external protection network to
protect the line circuit against foreign
voltages consists of the resistors Rpr1
and Rpr2 and an overvoltage protec-
tion component, see fig 5. The series
resistors Rpr1 and Rpr2 can be PTC,
poly-switch or fusible components.
For further protection, the simplest and
cheapest solution is a diode bridge
between SA,SB and GNDB, BATR
respectively. The diodes must be able to
allow current peaks more then 20A.
In case the battery BATR cannot accept
these high current peaks, one has to
add a voltage clamping component to
GND or a transient suppresser between
each line and GND. The clamp voltage
or protection voltage minimum must
always be larger then the maximum
used ringing battery BATR.
The protection components must be
dimensioned in such a way that the
transient energy on the chip pins AW,
BW does not exceed 1mJoule.(energy
on chip because of 1 lightning pulse)
Fig. 5: Recommended overvoltage protection options

0V
VbatS
VbatR
(avg. DC = VbatR/2)
ON HOOK
ON HOOK ADSI
RING BURST
OFF HOOK
(saturation, <0.5V)
(bias, 3V)
(bias, 3V)
(e.g. -24V)
(e.g. -64V)
(bias, 3V + drop
of BAT switch)
(bias, 3V + drop of BAT switch)
14
MTK-40131
Fig 6: SH POTS Line voltages - example.
Functional Characteristics of the SH POTS System
For reference, fig 6 shows the typical
voltages on both wires during various
stages of operation. For detailed electri-
cal parameters, please refer to the Elec-
trical Characteristics section.

On-hook Conditions
When a line is not in use (on-hook), the
designer may select either the speech
battery or the ringing battery as the sup-
ply to the line drivers. In this mode, most
of the internal circuits are put into a low
power operating mode, to minimise
supply currents. The A and B wire out-
puts are effectively connected to the
supply voltage, thus applying this volt-
age (minus a small saturation voltage)
to the line. The output is current limited
in this mode, thus protecting against
short circuits, and limiting any inrush
current when a set goes off hook. If the
SH LIC detects a current in excess of a
(programmable) limit, the off-hook con-
dition will be detected (an on-chip
debouncer with selectable delay avoids
accidental hookswitch detection), and
the circuit will be put into active speech
mode. The nominal off-hook detection
currents, and the hysteresis, are shown
in fig 7. When in the on-hook condi-
tion, the system designer may select,
under program control via the GCI bus,
an ‘on hook active mode’, whereby on-
hook signalling (ADSI, CLI etc..) can be
performed in either direction (note, how-
ever, that battery reversal is not avail-
able in this mode.).
15
MTK-40131
off-hook
on-hook
6.0
8.8
10.2
13.6
line current
mA
Fig. 7: Nominal hook-switch detection thresholds (default values)
Parameter Conditions Min Max Units Note
Vfeedo Open-line feed voltage Vbats-1 Vbatr V 4
Ion Line current guaranteeing on-hook state 5.1 11.1 mA 1
Ioff Line current guaranteeing off-hook state 8.2 14.2 mA 1
Iohyst Hookswitch detect hysteresis 2 mA 1
Thks Hookswitch detect time 20 ms 2
Ioc Peak over-current limit, on-hook mode 145 mA 3
VbiasH Bias voltage during ADSI mode 2 4 V
VbiasL on a (H) and b (L) wires ref. BAT pin
Notes:
1. These are the default values, after
reset. The on-hook and off-hook thresh-
olds can be individually programmed in
the range 0 to 63mA nominal.
2. Time between off-hook condition and
the line current reaching 90% of its final
value.
3. This is the intrinsic current limit of the
output driver. This current can only be
seen during on-hook to off-hook tran-
sients, or during ringing into a short-cir-
cuit load during the ring-trip delay peri-
od. The actual value measured will
depend on the load resitance used.
4. Iline=0mA, independent of battery
reversal mode. This voltage is selected
by the user. The output impedance
when in the on-hook condition is set by
the sense resistors Rfeed.
The hook-switch detector has a pro-
grammable debounce timer. Times of 8,
16, 24 or 64 ms can be selected (com-
mon for both channels).
Table 6: On-hook Characteristics
6.3 10.0

16
MTK-40131
Parameter Conditions Min Max Units Note
Fr Ringing frequency
16.66, 20, 25 Hz -1 +1 Hz
50 Hz -2 +2 Hz
SFNr Single-frequency noise, 10 Hz to 4 kHz -63 dBm
Vr Ringing voltage (max), Vbatr=-72V 50 Vrms 4
Dr Ringing distortion, sine mode
30Hz to 132 kHz 5 %
Trtd Ring-trip delay, load = 500Ω+4µF 150 ms
Trtdeb Ring-trip de-bounce time 0 30 ms 3
Trtzc Ring-trip detect zero-cross mask time 1.75 ms 2
Tc Ring-cadence times (active and silent) 1 255 n/n 1
IrtH Ring-trip current, high threshold 6.0 12.0 mA 2
IrtL Ring-trip current, low threshold 3.5 9.5 mA 2
Hrt Ring-trip hysteresis 2 mA 2
Notes:
1. Units are periods of the selected ring-
ing frequency. The default values are 1s
on, 3s off with a ringing frequency of
50Hz.
2. These are the default values, after
reset. The max and min ring-trip thresh-
olds can be individually programmed
in the range 0 to 63mA(!) nominal. The
ring-trip detect mask time is used to
bridge the zero-crossings of the ringing
signal, and is programmable between
0 and 32 ms in 125µs steps.
3. User-selectable 0 or 30ms. Default is
30 ms.
4. Ringing voltage is user programma-
ble from 0 to 70Vp(diff) between the a
and b wires (NB, the ringing battery
voltage must be large enough to encom-
pass this voltage), in 256 steps. The
default is the maximum value. Condi-
tion: Load = Ø mA
Ringing Injection
The SH POTS chipset is capable of
directly injecting a ringing signal of up
to 50Vrms (sine wave) without the need
for additional external components. The
technique of “balanced ringing” is
used, which allows this large voltage
swing to remain within the technology
limits of the SH LIC device. (Balanced
ringing requires a specific algorithm for
ring-trip detection, which is also imple-
mented by the chipset). The SH POTS
chipset allows the user to program a
DC offset during ringing as well as a
reduced amplitude ringing signal,
should the application require
this. Ringing waveform, frequency,
amplitude and cadence, as well as ring-
trip thresholds, are controlled by the
CODSP device, and are all program-
mable. Ringing cadence can be auto-
matic, with independently programma-
ble ring and pause times, or ringing
can be controlled directly via the GCI
bus. In automatic cadence mode, ring-
ing bursts on both channels can option-
ally be interleaved if simultaneously
active, to avoid peaks in current from
the ringing battery supply.
Table 7: Ringing Characteristics

DC Feed Characteristics
As shown in figure 8, the SH POTS
chip-set implements a constant-current
feed. The limit current and the residual
resistance (slope of the characteristic)
are both programmable by the user.
The DC characteristic falls into three
regions. When the combination of line
and subset result in a current less than
the programmed limit current, the sys-
tem behaves like a battery with a fixed
feed resistance of 120Ω, and a voltage
equivalent to the speech supply voltage
(VbatS) minus the bias voltage on both
lines (6V nominal in total). Should line
conditions permit a current which
exceeds the programmed limit current,
the system enters the constant-current
feed mode described above. In order to
protect the output stage in the transition
region at higher line currents (in excess
of 50mA), a third region is defined,
where the system synthesises a fixed
feed resistance of 200Ω. The slope of
the voltage/current characteristic in the
constant-current mode can be user pro-
grammed to select the effective feed-
resistance.
Note: The SH LIC device includes an
over-temperature protection, which acti-
vates in case of overheating of the
device.
Battery Voltage and Rever-
sal
The open-line voltage (i.e. the voltage
seen on the line when on-hook) is user-
selectable for each channel via an inter-
nal register. It can be either the ringing
battery supply (most common use) or
the speech battery supply. The speech
battery supply is automatically selected
when an off-hook condition is detected,
independently of these control bits. The
selected supply voltage is maintained
when the on-hook signalling function
(ADSI) is enabled.
The polarity of the line feed can be
dynamically controlled by the user. In
the ‘normal’ condition, the A-Wire is the
most positive. Reversal thus makes the B-
Wire the most positive. Battery reversal
is fast (not soft), is controlled by pro-
gramming an internal register and is
independent for both channels. The
selected polarity is used in all states (on-
hook, off-hook, ringing etc...) except on-
hook signalling which is normal battery
mode.
17
MTK-40131
Iline (mA)
20
40
60
80
Vline (V)
Vbats
VfN
(Programmable)
Rfeed
Rfeed=200Ω
Rfeed=120Ω
Fig 8: DC Feed characteristics.
Parameter Conditions Min Max Units Note
VbiasH Bias voltage, a wire (Iline=0) 2.5 3.5 V
VbiasL Bias voltage, b wire (Iline=0) 2.5 3.5 V
TOLIcl Current limit tolerance ±15 %
TRfeedcl Tolerance on programmed Rfeed ±15 %
when in current-limit
Icl Current-limit, useful programmed range 20 70 mA
Table 8: DC Feed Characteristics (Rfeed = 60Ωtotal (50Ω+10Ωprotection) x2)

18
MTK-40131
1500
1200
900
600
300
0
1800
500
600
1000
2000
2600
2800
frequency
Hz
µs
Delay
Fig 10: Relative Group delay, transmit and receive paths
(Digital to Digital) refered to 1kHz
16000
4600
3600
3400
3000
2400
600
400
300
200
receive
transmit
receive / transmit
-0.3
0.0
0.35
0.55
0.75
1.0
1.5
12.5
25.0
4000
Fig 9: Transmit and receive frequency response (default).
Transmit and Receive
Filter Characteristics
The Short-haul POTS chipset implements
transmit and receive filters according to
ITU-T (G.712). These filters can be
reprogrammed by the user for specific
requirements. Please contact Alcatel
Microelectronics for further details on
this. The default filter characteristics
implemented are shown in figures 9
and 10 below.
AC Transmission Characteristics (MTK-40131 System)
Transmit and Receive Gain
Transmit (from analog subset towards
the switching system) and receive gains
are user programmable, independently
for both lines. The default values are
0dBr in the transmit direction, and -
7dBr in the receive direction.
12.5 1 - SIN dB
π(4000-ƒ)
1200

19
MTK-40131
Source Impedance (Zco)
The central-office impedance, Zco, is
synthesised using digital signal proces-
sing techniques. This renders it very sta-
ble, and moreover programmable by
the user by means of coefficients which
are loaded via the GCI. Real or com-
plex Zco’s can be synthesised, using the
common 3-element model (Rs, Rp, Cp;
see fig 11). The Zco setting is common
for both lines. Both real and complex
Zco’s can be programmed to address
the local requirements of specifications
world-wide, and cover the range:
Using the default coefficient values, the
return loss when measured against
600Ω(using 0dBm input signal level) is
better than 20dB in the 300 to 3400
Hz band, and better than 10 dB at 10
kHz.
Real impedances: 600Ωto 900Ω
Complex impedances:
Rs from 160Ωto 500Ω
Rp from 300Ωto 1000Ω
Rp//Cp pole from 725 Hz to 5kHz
Rs
Rp
Cp
Fig. 11: 3-element Zco model.
Balance Impedance
(Echo Canceller)
The balance impedance (model of the
line+set impedance used to separate
the receive and transmit signals in the
‘hybrid’) is independently programma-
ble (though is the same for both
channels). Default values offer echo
return loss of better than 20dB, though
optimization to specific line and set
characteristics may yield further
improvement.
Rs Rp Cp ZcoSh Alfa3 ZcoA2 Rzco ZcoGamma ZcoAlfa3 Ftx Ap Nan ACG
Belgium 600 0 0 0 0 3 0 0 237 0 0 103
Germany 220 820 115nF 0 40 9 9 5 52 346 512 125
Europe 270 750 150nF 0 19 7 15 4 122 388 -179 125
ZCO850 850 0 0 0 0 0 0 0 282 0 0 123
ZCO900 900 0 0 0 0 0 0 0 290 0 0 126
Table 9: Examples of ZCO Coefficients
h0 h1 h2 h3 a0 c5 b0 Dzd0 Dzd1
Belgium 4 -22 105 95 0 0 0 1 1
Germany -31 48 1 156 0 0 0 0 0
Europe 3 -23 118 88 0 0 0 0 0
ZCO850 4 -22 105 95 0 0 0 1 1
ZCO900 4 -22 105 95 0 0 0 1 1

20
MTK-40131
Off-hook Characteristics (MTK-40131 System)
Parameter Conditions Min Max Units Note
Gtx Relative gain, transmit direction -6 +1 dB 1
Gain programming step 0.25 dB
Step accuracy 0.1 dB
Gain tolerance (ref. programmed value) -0.5 +0.5 dB
Grx Relative gain, receive direction -12 +1 dB 1
Gain programming step 0.25 dB
Step accuracy 0.05 dB
Gain tolerance (ref. programmed value) -0.5 +0.5 dB
dGlt Long-term gain stability -0.5 +0.5 dB 2
Gttx Gain tracking, TX path
+3 to -40 dBm0 ±0.3 dB 3
-40 to -50 dBm0 ±0.6 dB 3
-50 to -55 dBm0 ±1.6 dB 3
Gtrx Gain tracking, RX path
+3 to -40 dBm0 ±0.3 dB 3
-40 to -50 dBm0 ±0.6 dB 3
-50 to -55 dBm0 ±1.6 dB 3
IMDtx Intermodulation distortion, TX path -45 dBm0 4
IMDrx Intermodulation distortion, RX path -50 dBm0 4
Sdtx Signal to total distortion ratio, TX (gain= 0 dB)
-0 to -10 dBm0 35 dB 5
-20 dBm0 34.7 dB
-30 dBm0 32.9 dB
-40 dBm0 24.9 dB
-45 dBm0 19.9 dB
Sdrx Signal to total distortion ratio, RX (gain= - 7 dB)
-0 to -10 dBm0 35 dB 5
-20 dBm0 33.8 dB
-30 dBm0 28.8 dB
-40 dBm0 19.5 dB
-45 dBm0 14.5 dB
SFNrx Single frequency noise
300 to 3400 Hz, all out of band freqs. -40 dB
700 to 1100 Hz in band 300 to 3400Hz -49 dB
Longitudinal balance
Resistor matching 1% 40 dB
0.1% 46 dB
Notes:
1. User programmable.
2. Covers variations within the permit-
ted ranges of supply voltage and tem-
perature during any one year.
3. Referred to the gain at 1020 Hz
applied to the input at a level -10dBm0.
4. Intermodulation distortion measured
for all intermodulation products of any
non-harmonically related frequencies in
the range 300 to 3400 Hz for levels
between -4 and -21 dBm0.
5. Intermodulation distortion measured
for all intermodulation products of a fre-
quency in the range 300 to 3400 Hz at
-9dBm0 and 50Hz at -23dBm0.
Table 10: Off-hook Characteristics (MTK-40131 System)
Conditions: see paragraph "operating conditions"
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