Alinco DR-620 User manual

DR-620
Service Manual
CONTENTS
SPECIFICATIONS
1) GENERAL.............................................................................2
2) TRANSMITTER...................................................................2
3) RECEIVER ........................................................................... 3
CIRCUIT DESCRIPTION
1) VHF Rece tion....................................................................4
2) UHF Rece tion....................................................................5
3) FM Rece tion.......................................................................5
4) V/V (VHF-VHF) Dual Rece tion......................................6
5) U/U (UHF-UHF) Dual Rece tion .................................... 6
6) VHF Squelch Control .........................................................6
7) UHF Squelch Control.........................................................6
8) Transmit Signal Path..........................................................7
9) VHF Transmit Signal Path.................................................7
10) UHF Transmit Signal Path.................................................7
11) VHF Tx APC Circuit............................................................7
12) UHF Tx APC Circuit............................................................8
13) VHF PTT Circuit...................................................................8
14) UHF PTT Circuit..................................................................8
15) VHF PLL................................................................................8
16) UHF PLL................................................................................9
17) Power-on Circuit.................................................................9
SEMICONDUCTOR DATA
1) M5218FP (XA0068)......................................................... 10
2) NJM78L05UA (XA0098) ................................................. 10
3) NJM7808FA (XA0102).................................................... 10
4) TC4S66F (XA0115)......................................................... 11
5) AN8010M (XA0119).........................................................11
6) BU4052BF (XA0236)....................................................... 11
7) TA75S01F (XA0332)........................................................ 12
8) TC4W53FU (XA0348)..................................................... 12
9) TA31136FN (XA0404)..................................................... 12
10) LA4425A (XA0410).......................................................... 13
11) NJM2904V (XA0573)....................................................... 13
12) NJM2902V-TE1 (XA0596) ............................................. 13
13) S-80845ALMP-EA9-T2 (XA0620) ............................... 14
14) TK10931V (XA0666)........................................................ 14
15) BR24C64F-E2 (XA0669) ............................................... 15
16) LC75884W (X A 0899) ..................................................... 16
17) M51132FP (XA0900)....................................................... 17
18) M30620FCAGP (XA0913/XA0949)...................... 17~19
19) M38503M2H667FP (XA0914) ............................... 20~21
20) M64076AGP (XA0915)...................................................22
21) S-816A50AMC (XA0925)
............................................... 23
22) NJM78M05DL1A (X A0947) .......................................... 23
23) Transistor, Diode, and LED Outline Drawings.... 24~25
24) LCD Connection........................................................26~27
EXPLODED VIEW
1) Front View ........................................................................... 28
2) Bottom View....................................................................... 29
PARTS LIST
Front Unit.................................................................... 30~31
LED Unit..............................................................................31
Main Unit.....................................................................31~42
Mechanical Parts..............................................................42
Packing Parts.....................................................................42
Accessories (Screw S et).................................................42
ADJUSTMENT
1) Adjustment S ot...............................................................43
2) Adjustment Mode..............................................................44
3) VHF Adjustment S ecification.......................................45
4) UHF Adjustment S ecification.....................................46
5) VHF Test S ecification....................................................47
6) UHF Test S ecification....................................................48
PC BOARD VIEW
1) Front Side A ........................................................................49
2) Front Side B ........................................................................49
3) Main Side A ........................................................................50
4) Main Side B ........................................................................ 51
FRONT SCHEMATIC D IA G RAM ...................................52
MAIN SCHEMATIC D IA G R AM ........................................53
FRONT BLOCK D IA G RAM ..............................................54
MAIN BLOCK DIA GRAM ...................................................55
ALINCO,INC.

SPECIFICATIONS
1) GENERAL
Frequency coverage
DR-620T (U.S amateur)
DR-620E (Euro ean amateur)
O erating mode
Frequency resolution
Number of memory channels
Antenna im edance
Power requirement
Ground method
Current drain Receive
Transmit
O erating tem erature
Frequency stability
Dimensions
Weight
2) TRANSMITTER
Out ut ower
Modulation system
Maximum frequency deviation
S urious emission
Adjacent channel ower
Modulation Distortion
Micro hone im edance
87.500 - 107.995MHz (WFM RX)
108.000 - 135.995MHz (AM RX)
136.000 - 173.995MHz (RX)
144.000 - 147.995MHz (TX)
335.000 - 479.995MHz (RX)
430.000 - 449.995MHz (TX)
87.500 - 107.995MHz (WFM)
144.000 - 145.995MHz (RX, TX)
430.000 - 439.995MHz (RX, TX)
16K0F3E (Wide mode) 8K50F3E (Narrow mode)
5, 8.33, 10, 12.5, 15, 20, 25, 30, 50, 100kHz
200
50Q unbalanced
13.8V DC±15% (11.7 to 15.8V)
Negative ground
0.6A (Max.) 0.4A (Squelched)
11.0A
- 10 to 60 C
±2.5 m
142 (w) x 40 (h) x 174 (d) mm
(w/o knobs)
A rox. 1.0kg
High : 50W (VHF)
35 W(UHF)
Mid : 10W
Low : 5W
Variable reactance frequency modulation
±5kHz (Wide mode) ±2.5kHz (Narrow mode)
-60dB
-60dB
Lass than 3%
2kQ
2

3) RECEIVER
Sensitivity
Receiver circuitry
Intermediate frequency
Squelch sensitivity
Selectivity (-6dB / -60dB)
S urious and image rejection ratio
Audio out ut ower
-16dBu for 12dB SINAD
Double conversion su erheterodyne
1st 21.7MHz 2nd 450kHz (VHF)
1st 45.1MHz 2nd 455kHz (UHF)
-18dBu
12kHz/ 24kHz
70dB
2.0W (8Q, 10% THD)
! Note : All s ecifications are subject to change without notice or obligation.
3

CIRCUIT DESCRIPTION
1) VHF Rece tion
Incoming VHF signals are assed through a low- ass filter network, antenna switching diodes D20
(1SV268), D19 (1SS355) and D26 (DAN235E), and a high- ass filer network, and on to the RF am lifier
Q19 (3SK131). The am lified RF signal is assed through another RF am lifier Q18 (2SC5226) and
band- ass filtered again by varactor-turned resonators L46, L49, L51 and D28, D29, D30 (all HVU359),
then a lied to the 1st mixer Q21 (3SK240) along with the first local signal from the PLL circuit.
The first local signal is generated between 122.3 MHz and 126.3 MHz by the VHF VCO, which consists
of Q9 (2SK508) and varactor diodes D10, and D11 (both 1SV282) according to the receiving frequency.
The 21.7 MHz first IF signal is a lied to monolithic crystal filters XF and XF2 (both Q2175AD20)
which stri away unwanted mixer roducts, and the IF signal is a lied to the first IF am lifier Q20
(2SC4618). The am lified first IF signal is then delivered to the FM IF subsystem IC IC3 (TK10931V),
which contains the second mixer, limiter am lifier, noise am lifier, and FM detector.
The second local signal is generated by 21.25MHz TCXO, roducing the 450 kHz second IF signal
when mixed with the first IF signal within IC3.
The 450 kHz second IF signal is a lied to the ceramic filter FL1 (ALFYM450E) which stri s away all
but the desired signal, and then asses through the limiter am lifier within IC3 to the discriminator coil
L101, which removes any am litude variations in the 450 kHz IF signal before detection of s eech.
The detected audio then signal is am lified by IC9 (NJM2902V-B) asses through the de-em hasis
network, a high- ass filter consisting of IC9 (NJM2902V-A) and associated circuitry, and low- ass
filter consisting and associated circuitry. The filtered audio signal is switched by IC12 (BU4052), then
asses through the audio volume control IC IC13 (M511312FP) which adjusts the audio sensitivity to
com ensate for audio level variations.
The audio signal is am lified by IC8 (LA4425A), then a lied to the internal louds eaker.
4

2) UHF Rece tion
Incoming UHF signals are assed through a low- ass filter network, high- ass filter network, antenna
switching diodes D16 (1SS355) and D18 (1SV268), and on to the band- ass filter network consisting
of varctor diode D49 (HVU359) and L79.
The filtered UHF signal is am lified by RF am lifier Q41 (3SK240) and fed to another band- ass filter
consisting of varactor diode D50 (HVU359) and L80, and then is assed through another RF am lifier
Q43 (2SC5226) to another band- ass filter consisting of varactor diodes D51 and D52 (both HVU359)
and L81/L82.
The am lified and filtered UHF signal is a lied to the 1st mixer Q42 (3SK240) along with the first local
signal from the PLL circuit.
The first local signal is generated between 384.9 MHz and 404.9 (*2) MHz by the UHF VCO, which
consists of Q29 (2SK508) and varactor diodes D38 and D40 (both ISV278), according to the receiving
frequency.
The 45.1MHz first IF signal is a lied to monolithic crystal filters XF3A and XF3B (Q4511BD10) which
stri away unwanted mixer roducts, and the IF signal is a lied to the first IF am lifier Q44 (2SC4618).
The am lified first IF signal is then delivered to the FM IF subsystem IC IC5 (TA31136FN), which 2)
The am lified first IF signal is then delivered to the FM IF subsystem IC IC5 (TA31136FN), which
contains the second mixer, limiter am lifier, noise am lifier, and FM detector.
The second local signal is generated by 45.555 MHz crystal X4, roducing the 455 kHz second IF
signal within IC5.
The 455kHz second IF signal is a lied to the ceramic filter FL4 (CFW455E) which stri s away all but
the desired signal, and then asses through the limiter am lifier within IC5 to the discriminator coil
L102 , which removes any am litude variations in the 455 kHz IF signal before detection of s eech.
The detected audio then signal is am lified by IC9 (NJM2902V-C) asses through the de-em hasis
network, a high- ass filter consisting of IC9 (NJM2902V-D) and associated circuitry, and a low- ass
filter consisting and associated circuitry. The filtered audio signal is switched by IC12 (BU4052), then
asses through the audio volume control IC IC13 (M511312FP), which adjusts the audio sensitivity to
com ensate for audio level variations.
The audio signal is am lified by IC8 (LA4425A) then a lied to the internal louds eaker.
3) FM Rece tion
Incoming FM signals are assed through a low- ass filter network, antenna switching diodes D19
(1SS355), D20 (1SV2685) and D26 (DAN235E), and a high- ass filter network, and on the RF am lifier
Q36 (2SC5066). The am lified RF signal is assed through band- ass filtered L, C, then a lied to
the 1st mixer Q33 (2SC5066) along with the first local signal from the circuit.
The first local signal is generated between 86.7 MH and 118.7 MHz by the FM VCO, which consists of
Q14 (2SC4808) and varactor diodes D23, and D25, (both 1SV282) according to the receiving frequency.
The 10.7 MHz first IF signal is a lied to ceramic filters FL3 (SFT10.7MAS) which stri away unwanted
mixer roducts, and the IF signal is a lied to the first IF am lifier Q37 (2SC4618). The am lified first
IF signal is then delivered to the FM IF subsystem IC IC3 (TK10931V), limiter am lifier, noise am lifier,
and FM detector.
The 10.7 MHz first IF signal is a lied to the discriminator coil L53, which removes any am litude
variations in the 10.7 MHz IF signal before detection of s eech.
5

4) V/V (VHF-VHF) Dual Rece tion
During V & V o eration, the incoming VHF “sub” band signal is assed through a low- ass filter network,
antenna switching diode D19 (1SS355), D20 (1SV268) and a high- ass filter network to the RF am lifier
Q19 (3SK131). The am lified RF signal is assed through a high- ass filter network, VHF “sub” RF
am lifier Q31 (2SC5066), and a low- ass filter network, then is a lied to the VHF “sub” first mixer
Q32 (2SC5066) along with the 45.1 MHz VHF “sub” first local signal from the VHF “sub” VCO circuit.
The VHF “sub” first local signal is generated between 189.1 MHz and 193.1 MHz by the VHF “sub”
VCO Q38.
The 45.1 MHz VHF “sub” second IF signal is a lied to the UHF receiving circuit. The VHF “sub” signal
is am lified, filtered, and demodulated, etc., by the UHF “main” receiving circuit, described reviously.
5) U/U (UHF-UHF) Dual Rece tion
During U/U o eration, the incoming UHF “sub” band signal is assed through high- ass and low- ass
filter networks, antenna switching diodes D16 (1SS355) and D18 (ISV268), and another high- ass
filter network to the RF am lifier Q51 (2SC5066). The am lified RF signal is assed through a low-
ass filter network, UHF “sub ”RF am lifier Q49 (2SC5066), and low- ass filter network, then is a lied
to the UHF “sub” first mixer Q52 (2SC5066) along with the 21.7 MHz UHF “sub” first local signal from
the UHF “sub” VCO.
The UHF “sub” first local signal is generated between 408.3 MHz and 428.3MHz by the UHF “sub”
VCO Q13.
The 21.7 MHz UHF “sub” second IF signal a lied to VHF receiving circuit. The UHF “sub” signal is
am lified, filtered, and demodulated, etc., by the VHF receiving circuit, described reviously.
6) VHF Squelch Control
When no VHF carrier is being received, noise at the out ut of the detector stage in IC3 is am lified and
band- ass filtered by the noise am section of IC3, then asses through the noise adjust VR (VR8) to
CPU. The resulting DC voltage is a lied to in 88 of main CPU IC19 (M30624FGAGP), which
com ares the squelch threshold level to that which set by the font anel VHF SQL knob.
While no carrier is received, in 55 of IC19 remains “high,” turning on the squelch switch Q108
(DTC363EK) to disable audio out ut from the s eaker.
7) UHF Squelch Control
When no UHF carrier is being received, noise at the out ut of the detector stage in IC5 is am lified
and band- ass filtered by the noise am section of IC5, then asses through the noise adjust VR8 to
c u. The resulting DC voltage is a lied to in 90 of main CPU IC19, which com ares the squelch
threshold level to that which set by the front anel UHF SQL knob.
While no carrier is received, in 56 of IC19 remains “high” turning the squelch switch Q109 (DTC363EK)
to disable audio out ut from the s eaker.
6

8) Transmit Signal Path
The s eech signal from the micro hone asses through the MIC jack CN601 to AF am lifier IC601
(M5218FP) on the FRONT UNT. The am lified s eech signal is subjected to am litude limiting by
IC601 (M5218FP), then asses through the Front interface jacks CN602 and CN2 to MAIN Unit. On
the MAIN UNIT, the s eech signal asses through the audio mute switch IC7 (TC4066F), MIC gain
control VR5 and buffer am lifier IC1 (NJM2902V-C) and a low- ass filter network at IC1 (NJM2902V-
A) to deviation control VR3 (for VHF Tx audio) or VR4 (for UHF Tx audio).
9) VHF Transmit Signal Path
The adjusted s eech signal from VR3 is delivered to VHF VCO Q9, which frequency modulates the
transmitting VCO D6 (1SV278).
The modulated transmit signal asses through buffer am lifier Q7 (2SC5066), a low- ass filter network,
and another buffer am lifier Q3 (2SC5226) to another low- ass filter network.
The filtered transmit signal is a lied to the Pre-Drive am lifier Q2 (2SK3074) and Drive am lifier Q1
(2SK2975), then finally is am lified by Power am lifier Q4 (RD70HV1) u to 50 Watts. This three
stage ower am lifier’s gain is controlled by the APC circuit.
The 50-Watt RF signal asses through a low- ass filter network, antenna switch D1 (XB15A407), and
another low- ass filter network, and then is delivered to the ANT jack.
10) UHF Transmit Signal Path
The adjusted s eech signal from VR4 is delivered to UHF VCO Q29 which frequency modulates the
transmitting VCO D35 (1SV278).
The modulated transmit signal asses through buffer am lifiers Q28 (2SC5066) and Q7 (2SC5226) to
a high- as filter network.
The filtered transmit signal is a lied to the Pre-Drive am lifier Q2 (2SK3074) and Drive am lifier Q1
(2SK2975), then finally is am lified by Power am lifier Q4 (RD70HV1) u to 35 Watts. This three
stage ower am lifier’s gain is controlled by the APC circuit.
The 35-Watt RF signal asses through a high- ass filter network, antenna switch D12 and D13
(UM9401F), low- ass filter and high- ass filter networks, and then is delivered to the ANT jack.
11) VHF Tx APC Circuit
A ortion of the ower am lifier out ut is rectified by D8 (MA4S713), D9 (MA4S713) and Q12 (2SC4081),
then delivered to APC IC1 (NJM2902V-D) as a DC voltage which is ro ortional to the out ut level of
the ower am lifier.
The APC IC1 com ares the rectified DC voltage from the ower am lifier and the reference voltage
from the main CPU IC19, roducing a control voltage for the Automatic Power Controller Q8 (RN2107)
and Q11 (RN1107) which regulates su ly voltage to the Pre-Drive am lifier Q2, Drive am lifier Q1,
and Power am lifier Q4, so as to maintain stable out ut ower under varying antenna loading conditions.
7

12) UHF Tx APC Circuit
A portion of the power amplifier output is rectified by D9 (M44S71 ), D22 (MA4S71 ) and Q12
(2SC4081), then delivered to APCD ICI (NJM2902V-D) as a DC voltage which is proportional to the
output level of the power amplifier.
The APC IC1 compares the rectified DC voltage from the power amplifier and the reference voltage
from the main CPU IC19, producing a control voltage for the Automatic Power Controller Q8 (RN2107)
and Q11 (RN1107) which regulates supply voltage to the Pre-Drive amplifier Q2, Drive amplifier Q1,
and Power amplifier Q4, so as to maintain stable output power under varying antenna loading conditions.
13) VHF PTT Circuit
When the PTT switch is pressed, pin 4 of front CPU IC604 (M 850 M) goes “LOW,” which sends the
“PTT” command to the main CPU, IC19. When it receives the “PTT” command, pin71 of Q19 goes
“high” to control local switch D5 (DAN2 5E), filter switch D2, D , TX switch D17 (DAN2 5E), and APC
switch Q8/Q11, which activates the VHF Tx circuit. Meanwhile, pin 69 of IC19 goes “low,” which
disables the VHF Rx circuit.
14) UHF PTT Circuit
When the PTT switch is pressed, pin 4 of FICront CPU IC604 (M 850 M) goes “LO” which sends the
“PTT” command to the main CPU, IC19, When it receives the “PTT” command, pin72 of IC19 goes
“high” to controls local switch D5, filter switch D2, D , TX switch D17 and APC switch Q8/Q11, which
activates the UHF Tx circuit. Meanwhile, pin 70 of Q19 goes “low,” which disables the UHF Rx circuit.
15) VHF PLL
A portion of the output from the VHF VCO Q9 (2SK508) passes through buffer amplifiers Q7 (2SC5066)
and Q5 (2SC5066) to the programmable divider section of the PLL IC IC2 (M64076AGP), which
divides the frequency according to the frequency dividing data from the main CPU, IC19. It is then
sent to the phase comparator.
The 21.25 MHz frequency of the reference oscillator circuit, made up of TCXO X1, is divided by the
reference frequency divider section of IC2 into 4250 or 400 parts to become 5 kHz or 6.25 kHz
comparative reference frequencies, which are utilized by the phase comparator.
The phase comparator section of IC2 compares the phase between the frequency-divided oscillation
frequency of the VCO circuit and comparative frequency, and its output is a pulse corresponding to the
phase difference.
This pulse is integrated by the charge pump and loop filter of IC2 into a control voltage (VCV) to
control the oscillation frequency of the VHF VCO Q9.
8

16) UHF PLL
A portion of the output from the UHF VCO Q29 (2SK508) passes through buffer amplifier Q28 (2SC5066)
and Q 9 (2SC5066) to the programmable divider section of the PLL IC IC2 (M64076AGP), which
divides the frequency according to the frequency dividing data from the main PU IC2. It is then sent to
the phase comparator.
The 21.25 MHz frequency of the reference oscillator circuit, made up of TCX0 X1, is divided by the
reference frequency divider section of IC2 into 4250 or 400 parts to become 5 kHz or 6.25kHz
comparative reference frequencies, which are utilized by the phase comparator.
The phase comparator section of IC2 compares the phase between the frequency-divided oscillation
frequency of the VCO circuit and comparative frequency, and its output is a pulse corresponding to the
phase difference.
This pulse is integrated by the charge pump and loop filter of IC2 into a control voltage (VCV) to
control the oscillation frequency of the UHF VCO Q29.
17) Power-on Circuit
When the POWER switch is turned on, pin 18 of man CPU IC19 goes “low.” When pin 18 of IC19 goes
“low,” pin 79 of IC19 goes “high” to activate the power switches Q6 (2SB1 86) and Q74 (2SC4081),
which supply the DC power to the radio.
9

SEMICONDUCTOR DATA
1) M5218FP (XA0068)
Dual Low Noise
O erational Am lifiers
Output 1 1
Inverting Input 1 2
Non Inverting Input 1 3
Power supply Minus 4
2) NJM78L05UA (XA0098)
5V Voltage Regulator
1 OUTPUT
2 COMMON
3 INPUT
3) NJM7808FA (XA0102)
8V Voltage Ragulator
Pin Assignment
1 OUTPUT
2 COMMON
3 INPUT
3 2 1
8
7
6
5
Power Supply Plus
Output 2
Inverting Input 2
Non Inverting Input 2
10

Bilateral Switch
4) TC4S66F (XA0115)
5) AN8010M (XA0119)
10V Voltage Regulator
Test Circuit
u u u
Output Common Input
AN8010M
6) BU4052BF (XA0236)
Analog Multi lexer/Demulti lexer
11

7) TA75S01F (XA0332)
Operational Amplifiers
jg ____ a
y y y
8) TC4W53FU (XA0348)
Multiplexer/Demultiplexer
Function Table
Control input ON channel
INH A
L L ch0
L H ch1
H*NONE
* Don't Care
9) TA31136FN (XA0404)
COMMON 1 •8 VDD
-P*
INH 2 7 ch0
O i
VEE |_3_ GO
~n 6 | ch1
VSS 4 5 A
Low Power FM IF
Block Diagram
VCC OUT
12

5W Audio Power Amplifiers
10) LA4425A (XA0410)
Test Circuit
1 2 3 4 5
11) NJM2904V (XA0573)
12) NJM2902V-TE1 (XA0596)
Quad Single Supply Operational Amplifier
13

Pin Assignment / BLOCK Diagram (Top View)
o
to
w
X
>
o
o>
o>
o>
o
0 <
c 3
1 -
o 02
o <
3
>
O
§
ST
(Q
CD
D
CD
CD
O
O
3
c
3
c r
(D
13) S-80845ALMP-EA9-T2 (XA0620)

EE-P ROM
Block Diagram
15) BR24C64F-E2 (XA0669)
AO 1
A1 2
A2 3
GND 4
64Kbit EEPROM ARRAY
ábit
ADDRESS
DECODER h
13bit
N
SLAVE^WORD
ADDRESS REGISTER DATA
REGISTER
START STOP
CONTROL CIRCUIT
IACK H
4HIGH VOLTAGE VOLTAGE r5
GENERATOR DETECTOR
a Vcc
7 WP
e SCL
5 SDA
Pin Assignment
Vcc WP SCL SDA
O
BR24Ce4/F
AO A1 A2 GND
15

LCD Driver
16) LC75884W (XA0899)
*n 'J'
in m
vt in -c m fN ■-<
in Tf fo fs h j; £ E E f O iN H ü t n c c ^ y M n '# ^
[/) ui tu m u O O O o m m u - u rj^ j'-îï^ r ^ j'-ïj'^ ’iT
i i W K K i i U U U U i O t i f l n n w w w w w u ju )
nnnnnnnnnnnnnnnnnnnn
/ fiO 50 41
KS6 \=Z 61 AO t z i S42
K I1 t= Z S41
K I2 C = — } S4G
K I3 E = l S 39
K I4 C = = ZI S 38
K I5 CT! = ) S 37
VDD E = “ ZI S 36
VLCD 1ZZ z n S 35
V L C D l C Z
VLC D2 i = 70 LC75884W = 1 S 34
= 1 S3 3
VSS EZZ
TE S T 1 = (SQFP80) 30 = J S 32
= ] S 31
OSC C Z = □ S30
RES C Z n : S2 9
d o i n : 5 2 9
CE 1 = m S27
CL C Z ^ S 26
D i c n = 3 £ 2 5
P l / S l c = aoO S24
P 2 /S 2 c z : 21 = 3 S 23
1 10 20
WLI
■v.-^ w w M w w n t n t o w w u i u li/)
cO **
A ft
Block Diagram co (N
S 2
o o
u u
O O O
^ ro CN I—)
P4 P4 Al Ai
\ \ \ \
in ^ m fN >h
co co co co co
0 0 0 0 0
DO O-
D I O-
CL O -
CE O -
VDD O
COMMON
D R IV E R
CLOCK
GENERATOR
CCB
IN TE R FACE
VDET
h
SEGMENT D R IV E R & LATCH
S H IF T R E G IS TER
CONTROL
R E G IS TE R
KEY BUFFER
KEY SCAN
Ô Ô Ô Ô Ô
in n (N h
H H H H H
« « « « «
Ô Û Ô Ô Ô Ô
vo in (*) in h
co co co co co co
« « W w U5 W
N X
in
in in
co co
16

2ch Electronic Volume
17) M51132FP (XA0900)
Ref. su ly out 1O16 Out ut 1
Filter 5 ! 15 In ut 1
NC 5
w
K>
T I
T I
1 3 VCC
GND £S I NC
Volume 1 cont. [ T 1 2 NC
Noise cont. m11 In ut 2
Volume 2 cont. EH Out ut 2
VCA SW HZ SMode SW
18) M30620FCAGP (XA0913/XA0949)
Main CPU
Q Q
K. 51
"co ^ 7?5
Q Q Q
U) "(Ö N
1 1 L
? Q Q Q Q Q Q Q
'5 ^ 's i's ^ - a 's 'i; Q
QQQQQQQQ 5-
< < < < < < < < < ■?<<<<<<
^ 1- cjIo ^ w^5 Is-
C\JC\IC\1C\JCMC\JC\JC\IC0C0 OCOCOCOCOCOCOCO
D_Q_Q_D_Q_Q_Q_CL>Q_>CLÜ_CLCLQ_Q_Q- II CL CL
m u m u m w m
P12/D10 -
i 1/D9 -
P-Io/Ds-
PO7/D7 -
P06/D6 *
P05/D5 -
P04/D4 -
P03/D3 *
P02/D2 -
P01/D1 -
PO0/D0 -
PIO7/AN7/KI3-
PIO6/AN6/KI2 -
P105/AN5/KM -
P104/AN4/KIO -
P103/AN3 -
PIO2/AN2 -
PIO1/AN1 -
AVss -
PIO0/AN0 '
Vref "
_____ AVcc _
P97/ADtrg/Sin4 "
P96/ANEX1/SOUT4 "
P95/ANEX0/C K4 -
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CD CD
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■ P42/A18
■ P43/A19
- P44/CS0
• P45/CS1
• P46/CS2
■ P47/CS3 ___
• P50/WRL7WR
• P51/WRH/BHE
• P52/RD
' P53/BCLK
' P54/HLDA
‘ P55/HOLD
• P56/ALE
• P57/RDY/CLKOUT
■ P60/CTS0/RTS0
- P61/CLK0
• P62/RXD0
• P63/TXD0 ____
’ P64/CTS1/RTS1/CLKS1
■ P65/CLK1
■ P6e/RxDi
• P67/TXD1
■ P7o/TxD2/SDA/TAOoUT(;ii)
• P7i/RxD2/SCL7TA0lN/TB5lN(ä1)
' P72/CLK2/TA1 out/V
17

Terminal Function of Main CPU
No. Pin Name Function I/O Logic up Description
1 P94/DA1 TONE O D/A CTCSS tone output/DCS output
2 P9 /DA0 APC O D/A Power output control
P92 DATA O Pulse Serial data output for PLL IC
4 P91 STB O Pulse Strobe for PLL IC
5 P90 CLK O Pulse Seriai clock output for PLL IC
6 BYTE BYTE I GND
7 CNVss CNVss I H Witer control
8 P87 -O-
9 P86 -O-
10 RESET RESET I L Reset input
11 Xout XOUT O Main clock output
12 Vss VSS -GND
1 Xin XIN IMain clock input
14 Vcc VCC -CPU power terminal
15 P85 NMI I Activ high Interruption
16 P84 BU I L Backup signal detection input
17 P8 SEC I Activ high Aleam(SCR) sinal input
18 P82 PSW I L Power switch input
19 P81 CLKS O Activ high CPU clock-shift output
20 P80 MVRC O Pluse Main volume control
21 P77 LAMP I L up Lighting color selection (H:2color)
22 P76 SVRC O Pulse Sub volume control
2 P75 -O
24 P74 TUV O Pulse 144MHz Tuning-voltage control
25 P7 -O
26 P72 TUU O Pulse 4 0MHz Tuning-voltage control
27 P71 RXD2 I Pulse Serial Communication port for Clone
28 P70 TXD2 O Pulse Serial Communication port for Clone
29 P67 TXD1 O Pulse Serial Communication port for TNC
0 P66 RXD1 I Pulse Serial Communication port for TNC
1 P65 SCLK O Pulse Witer control
2 P64 BUSY O Pulse Witer control
P6 TXD O Pulse Serial Communication port for Front CPU
4 P62 RXD I Pulse Serial Communication port for Front CPU
5 P61 SCL O Pulse Serial clock output for EEPROM
6 P60 SDA I/O Pulse Serial dara output for EEPROM
7 P57 DUD I Activ low up Digital unit detect
8 P56 SCR I Activ low up Ready sigunal for digital unit
9 P55 EPM I Activ low up Witer control
40 P54 PTTM I Activ low up PTT input for TNC
41 P5 T5 O Activ low TX power output ON/OFF
42 P52 SQC O Activ low Squelch control for TNC
4 P51 STBD O Pulse Strobe for Digital unit
44 P50 DSQ I Activ high Squelch signal input for Digital unit
45 P47 TNCB O Activ high Power switch ON/OFF for TNC
46 P46 VVCS O Activ high VHF Main VCO ON/OFF
47 P45 UVCS O Activ high UHF Main VCO ON/OFF
48 P44 DCSW O Activ high DCS switch
49 P4 C/S O Activ low Digital/TNC mode ON/OFF
50 P42 VAD O Activ high VHF digital ON/OFF
51 P41 UAD O Activ high UHF digital ON/OFF
52 P40 M/S O Activ high MAIN/SUB band select
5 P 7 WIDE O Activ low Wide mode select
54 P 6 NAR O Activ low Narrow mode select
55 P 5 MUTV O Activ low VHF AF mute signal output
56 P 4 MUTU O Activ low VHF AF mute signal output
18

5l PSS XBR O Activ high XBR mute siqnal
5a PS2 DCSV OActiv high VHF DCS switch
59 P i DCSU O Activ high UHF DCS switch
60 Vcc VCC -CPU power terminal
6i P 0 SCRB O Activ low Power output for Aleam
e2Vss VSS -GND
6 P2l VMMT O Activ high VHF mod mute output
64 P2e UMMT O Activ high UHF mod mute output
eS P2S MMUT O Activ low Mic mute output
ee P24 ULV I Activ high VHF unlock input
6i P2S ULU I Activ high UHF unlock input
ea P22 AM O Activ high AM mode ON/OFF
e9 P2i 5RV O Activ high VHF RX power ON/OFF
i0 P20 SRU OActiv high UHF RX power ON/OFF
ii Pil STV O Activ high VHF TX power ON/OFF
i2 Pi6 STU O Activ high UHF TX power ON/OFF
i Pi5 14RS O Activ high MAIN 144MHz power OM/OFF
i4 Pi4 S4 RS O Activ high SUB 4 0MHz power ON/OFF
i5 Pi FMS O Activ high FM power ON/OFF
l6 Pi2 4SRS O Activ high MAIN 4 0MHz power OM/OFF
ii Pii Si4RS O Activ high SUB 144MHz power ON/OFF
ia PiO aiRS O Actv high Ext band power ON/OFF
i9 POl 5VS O Actv high 5V power ON/OFF
a0 P06 CSS O Activ high 5V power ON/OFF
ai P05 ALAM O Activ low AF mute for Aleam
a2P04 TB O Pulse ART/Toneburst siqnal output
aS P0 BEPi O Pulse Beep sound 1 output
a4 P02 BEP2 O Pulse Beep sound 2 output
aS POi O
ae POO FAN O Activ high Air FAN power ON/OFF
ai PiOl/ANl SMTV I A/D VHF S-meter siqnal input
aa Pi06/AN6 SQLV I A/D VHF noise input for squelch
a9 Pi05/AN5 SMTU I A/D UHF S-meter siqnal input
90 Pi04/AN4 SQLU I A/D UHF noise input for squelch
91 Pi0 /AN TINV I A/D VHF CTCSS/DCS tone input
92 Pi02/AN2 TINU I A/D UHF CTCSS/DCS tone input
9S PiOi/ANi BAT I A/D Power-supply voltage input
94 Avss AVSS -AD converter Gnd
9S PiOO/ANO BPi I A/D Band plan
9e Vref VREF -AD converter ref. power
9l Avcc AVCC -AD converter power
9a P9l BP2 I Ext.Band plan
99 P9e/ANEXi BPS I CH Band plan (L:CH)
i00 P9S/ANEXO THC I A/D PA Temperature detection
19

Front CPU
19) M3B5Ü3M2H667FP (XÄÜ914)
20