Alinco DR-150T User manual

D R - 1 5 0 T / E
S e r v i c e M a n u a l
CONTENTS
• SPECIFICATIONS
1 General ............................................................2
2 Transmitter.......................................................2
3 Receiver...........................................................2
• CIRCUIT DESCRIPTION
1 Receiver System..............................................3
2 Transmitter System......................................3 -4
3 PLL Circuit........................................................4
4 Terminal Function of Microprocessor .......... 5 - 7
5 Terminal Function of 4094 ................................ 8
• SEMICONDUCTOR DATA
1 AT24C08-10SI-2.7 ............................................ 9
2 BU4094BF........................................................9
3 MB1504LPF-G-BND-TF
.................................. 10
4 NJM2902M (T1 .............................................. 10
5 NJM7809A ......................................................11
6 RH5VA45AA-T1.............................................. 11
7 TA75S01F.......................................................11
8 TA7806F (TE16L ........................................... 11
9 S-AV17 ............................................................12
10 TC35305F (TP1 ............................................. 13
11 TK10930VTL...................................................14
12 TC4W66FU......................................................15
13 nPC1241H....................................................... 15
14 Transistor, Diode and LED Outline Drawings....16
15 LCD Connection.............................................17
• EXPLODED VIEW
1 Bottom View....................................................18
2 LCD View........................................................18
3 Top, Front View............................................... 19
• PARTS LIST
CPU Unit................................................. 20-21
MAIN Unit................................................22-25
VCO Unit.........................................................26
SPUnit............................................................26
MIC Unit..........................................................27
Mechanical Parts............................................27
Others.............................................................28
Packing............................................................28
Mic. Hanger Unit..............................................28
EJ20u..............................................................28
• ADJUSTMENT
1 Required Test Equipment ............................... 29
2 Adjustment for DR-150T/E .............................. 30
3 Adjustment Points ........................................... 31
4 Adjustment Quick Reference ........................... 31
• VOLTAGE TABLE
1 Transistor, FET ................................................32
2 Diode...............................................................33
3 Connector........................................................33
4 IC.....................................................................34
• PC BOARD VIEW
1 MIC Unit Side A...............................................35
2 MIC Unit Side B...............................................35
3 VCO Unit Side A.............................................35
4 CPU Unit Side A.............................................. 36
5 CPU Unit Side B............................................. 36
6
MAIN Unit Side A............................................ 37
7 MAIN Unit Side B............................................38
• BLOCK DIAGRAM....................................................39
• CIRCUIT DIAGRAM
1) MIC Unit...........................................................40
2 VCO Unit.........................................................41
3 Main Unit.........................................................42
4 CPU Unit.........................................................44
5 EJ20u Unit....................................................... 45
A U N C O , Inc

SPECIFICATIONS
1 General
Frequency Coverage:
Modulation:
Antenna Impedance:
Supply Voltage:
Current Consumption:
Frequency Stability:
Dimensions:
Weight:
Microphone:
(DR-150T
TX: 144.000- 147.995MHz (FM
RX: 108.000- 173.995MHz (FM/AM
RX: 440.000 ~ 449.995MHz (FM/AM
(DR-150E
TX: 144.000- 145.995MHz (FM
RX: 14 4.000- 145.995MHz (FM
RX: 430.000 - 439.995MHz (FM
F2, F3 (FM
50£2 unbalanced
13.8 V DC
Transmit (High 10.0A / Receive 0.6A
+/-I0ppm max.
140mm(W x 40mm(H x 129mm(D
approx. 800g (body only
(DR-150T EMS-12 (DTMF mic.
(DR-150E EMS-5A (plain mic.
2 Transmitter
Output Power (approx. :
Modulation System:
Spurious Emission:
Max. Deviation:
Distortion at 60% modulation:
Microphone Impedance:
High 50W / Mid 25W / Low 10W
Reactance Modulation
not more than -60dB
+/ -5kHz
not more than 3%
2.2kQ
3 Receiver
Receiving System:
Intermediate Frequency:
Sensitivity (12dB SINAD :
Selectivity:
Squelch Sensitivity:
AF Output:
AF Output Impedance:
Double Conversion Superheterodyne
First: 45.1MHz / Second: 455kHz
2m band: -16dBn or better, 70cm band: -10dBji or better
-6dB: 12kHz or more, -60dB: 28kHz or less
-20dB(i or better
1.5W
8Q
Specifications are subject to change without notice or obligation.
Specifications guaranteed in the amateur band only.
Operating temperature -10°C~+60°C

CIRCUIT DESCRIPTION
1 Receiver System
1. Preamp, Mixer Circuit
2. IF and AF Circuit
2 Transmitter System
1. Modulation Circuit
The signal from the antenna is passed through a low-pass filter and input to
L211. The signal from L211 is led to the base of Q208. The signal from
Q208 is led to the triple band pass filter (L212 L213 L214) and gets the
high image rejection ratio. The signal from the triple band pass filter is
converted into the first IF signal of 45.1 MHz. The receiving signal is led to
the gate 1 of Q209 and the first local oscillator signal is led to the gate 2 of
Q209. To reduce the high adjacent channel interference the band width of
the X203 is set to 20kHz. The signal from X203 is amplified by Q214 and
input to FM IF system IC201 ofTK10930.
The TK10930 has the second local oscillator circuit mixer circuit detector
circuit squelch circuit and so on. Pin1 and 2 are the terminals of the crystal
oscillator circuit. Pin3 of IC201 is connected to CFW201 directly because
the matching resistor for ceramic filter is built-in. The quadrature circuit
(pinl 1 of IC201) is connected to the L221. The signal from pin12 of IC201 is
connected to the LPF. The detected AF signal which has flat frequency
characteristics is led to the control unit and used as both squelch signal and
tone squelch signal. De-emphasis circuit consists of R257 R258 C282 and
C284. The amplifier consisting of Q215 and Q217 is located far away from
the VR in the control unit so it outputs the high voltage signal to prevent S/N
from the deterioration. The squelch switch circuit consists of Q216 and
Q235 and switches on/off at the point where there is no voltage to prevent
from the switching noise. The S meter signal from pin16 of IC201 is led to
the CPU in the control unit after adjusting the level at VR206. The noise
amplifier consists of pinl 9 and 20 the built-in OP amplifier in IC201. The
output signal of noise amplifier is amplified by Q218 rectified by D216 and
then led to the pin21 (hysteresis comparator input) of IC201. IC202 is about
5W audio power amplifier IC.
The microphone amplifier IC501(IDC LPF) consists of four operational
amplifiers. The signal from the microphone is led to amplifier circuit consist
ing of IC501C and then input to the pre-emphasis circuit consisting of C503.
And then input to the limiter circuit IC501B. The limiter circuit uses the
saturation of the OP amplifier. The amplified signal is input to the low-pass
filter IC501A. The output signal is led to amplifier circuit consisting of IC502
and the signal is passed through variable resistor VR204 for modulation
adjustment and input to the VCO unit. Sub tone signal is input to the low-
pass filter IC501D. Sub tone deviation is determined by VR205.

2. TX Amp. Circuit
3. PA Circuit
4. ALC Circuit
3 PLL Circuit
The signal from VCO is amplified by TX, RX wide band LO amplifier
Q207. The signal from Q207 is passed through the transmission/reception
selector, and amplified by Q206 and Q202. The PA unit is driven at
200mW driving power.
IC208 is 50W powered amplifier module. The output power is controlled
by the voltage of Pin3. The RF signal amplified 50W in PA is passed
through D201 and low-pass filter, and input to the antenna connector.
The power detection circuit consisting of D204 rectifies the output signal
voltage. VR201 is middle power adjust trimmer pot. VR202ishigh
power adjust trimmer pot. The detected DC voltage is amplified by Q203,
Q204 and Q205. Output power is controlled by voltage of Pin3 in IC5 and
collector voltage of Q202. When the temperature goes up unusually, the
power down circuit consisting of Q238, R316 and TH202 works to prevent
the device from the destruction.
The VHF-VCO circuit consisting of Q402, Q404, D404, D405, and D406.
The transmission/reception shift circuit consisting of Q404. The UHF-
VCO circuit consisting of Q401, D401, D402, and D403.
IC205 is pulse swallow system based PLL IC with the built-in prescaler,
which synthesizes 145MHz-band and 435MHz signal.
The loop filter consisting of R242, R243, R319, R320, C258, C350 and
C352.

4 Terminal Function of Microprocessor
No. Name Pin Name I/O Logic | Description
01 AVcc AVCC -A/D Power supply
02 ANQ BP1 IA/D Band planl (USA, General, EU A, EU B
03 AN1 BP2 IA/D Band plan 2 (RX, TX expansion
04 AN2 SMT IA/D S meter voltage input
05 AN2 XWR I-Command request, IF frequency switch
06 AVss AVss -A/D GND
07 TEST -Connected to Vcc
08 OSC1 OSC1 -4MHz OSC1
09 OSC2 OSC2 O -4MHz OSC2
10 RESET RESET I Active High CPU Reset
11 X1 I-Connected to Vcc
12 X2 o-Open
13 GND GND -CPU GND
14 DO SDA I/O PULSE EEPROM data (built-in, option ROM
15 D1 SCL1 oPULSE EEPROM clockl
16 D2 SCL2 oPULSE EEPROM clock2 (option board
17 D3 RMS IActive Low Microphone remote control input
18 D4 UP IActive Low Microphone up input
19 D5 DN I Active Low Microphone down input
20 D6 LMP 0 Active High Dimmer
21 D7 UNLK IActive High PLL unlock signal input
22 D8 STB2 oActive High CTCSS strobe
23 D9 TDO IActive Low CTCSS tone detection input
24 DIO/STOPC TID IActive Low CTCSS unit detection Input
25 D11/INT0 BUP IActive Low Back up signal detection Input
26 R00/INT1 SQD I Active Low Squelch Input
27 R01/INT2 ENC1 IActive Low Rotary encoder up input
28 R02/INT3 ENC2 IActive Low Rotary encoder down input
29 R03/INT4 DV IActive High DTMF signal detection input
30 RIO/TOB BEEP oPULSE Beep tone output
31 R11/TOC TB 0 PULSE Tone burst (1750Hz output (TX
RX BUSY oActive High Busy: Low out put (RX
32 R12/TOD TXLMP 0 Active High TX: High
33 R13/EVNB MSW 0 Active High Microphone mute output

No. Name Pin Name I/O Logic Description
34 R20/EVND TONE1 0 -Subtone output 1
35 R21/SCK TONE2 0 -Subtone output2
36 R22/SI TONE3 0 - Subtone output3
37 R23/SO TONE4 0 - Subtone output4
38 R30/SEG1 DT1 IActive High DTMF datal
39 R31/SEG2 DT2 IActive High DTMF data2
40 R32/SEG3 DT3 IActive High DTMF data3
41 R33/SEG4 DT4 IActive High DTMF data4
42 R4 0/S EG 5 CLK O Active High Clock (CTCSS,PLL, 4094
43 R41/SEG6 DATA 0 Active High Data (CTCSS,PLL, 4094
44 R42/SEG7 ST BP oActiva High PLL Strobe
45 R43/SEG8 STBS 0 Active High 4094 Strobe
46 R50/SEG9 PTT IActive Low PTT input
47 R51/SEG10 KR1 o-Key matrix outputl
48 R52/SEG11 KR2 0-Key matrix output2
49 R53/SEG12 KR3 0-Key matrix output3
50 R60/SEG13 KC1 I-Key matrix inputl
51 R61/SEG14 KC2 I -Key matrix input2
52 R62/SEG15 KC3 I-Key matrix input3
53 R63/SEG16 KC4 I -Key matrix input4
54 R70/SEG17 SEGO 0-LCD SEG0
55 R71/SEG18 SEG1 0-LCD SEG1
56 R72/SEG19 SEG2 0-LCD SEG2
57 R73/SEG20 SEG3 0-LCD SEG3
58 SEG21 SEG4 o-LCD SEG4
59 SEG22 SEG5 0-LCD SEG5
60 SEG23 SEG6 o- LCD SEG6
61 SEG24 SEG7 0 -LCD SEG7
62 SEG25 SEG8 0 - LCD SEG8
63 SEG26 SEG9 o-LCD SEG9
64 SEG27 SEG10 o-LCD SEG10
65 SEG28 SEG11 . o-LCD SEG11
66 SEG29 SEG12 o-LCDSEG12
67 SEG30 SEG13 o-LCD SEG13
68 SEG31 SEG14 0 -LCD SEG14

NO. Name Pin Name I/O Logic Description
69 SEG32 SEG15 0 -LCD SEG15
70 SEG33 SEG16 0 -LCD SEG16
71 SEG34 ■ SEG17 0 -LCD SEG17
72 SEG35 SEG18 0-LCD SEG18
73 SEG36 SEG19 O -LCD SEG19
74 SEG37 SEG20 O -LCD SEG20
75 SEG38 SEG21 O-LCD SEG21
76 SEG39 SEG22 O -LCD SEG22
77 SEG40 SEG23 O-LCD SEG23
78 SEG41 . SEG24 O -LCD SEG24
79 SEG42 SEG25 O -LCD SEG25
80 SEG43 SEG26 O -LCD SEG26
81 SEG44 SEG27 O -LCD SEG27
82 SEG45 SEG28 - O -LCD SEG28
83 SEG46 SEG29 O-LCD SEG29
84 SEG47 SEG30 O -LCD SEG30
85 SEG48 SEG31 0 -LCD SEG31
86 SEG49 SEG32 o-LCD SEG32
87 SEG50 , SEG33 0 -LCD SEG33
88 SEG51 SEG34 0-LCD SEG34
89 SEG52 SEG35 o-LCD SEG35
90 COM1 COM1 0- ; LCD SEG36
91 COM2 COM2 0 -LCD SEG37
92 COM3 COM3 0 -LCD SEG38
93 COM4 o-LCD SEG39
94 V1 LV1 -LCD Power supply
95 V2 LV2 -LCD Power supply
96 V3 LV3 -LCD Power supply
97 Vcc VCC -CPU Power supply
98 TON EC DTC 0-DTMF tone C output
99 TONER DTR O -DTMF tone R output
100 VTref ; VTR I-DTMF output reference level power supply

5 Terminal Function of 4094
No. Pin Name Function I/O Logic Description
P1-1 RFM RF power mid control 0 Active Low L=Power Mid
P1-2 RFL RF power low control oActive Low L=Power Low
P1-3 - - - --
P1-4 R145 RX 145 power control 0 Active Low L=RX 145 power ON
P1-5 R360 RX 360 power control 0 Active Low L=RX 360 power ON
PI-6 R440 RX 440 power control oActive Low L=RX 440 power ON
PI-7 R870 RX 870 power control 0 Active Low L=RX 870 power ON
PI-8 SIFT RX SIFT control 0 Active Low L=SHIFT ON
P2-1 -- - --
P2-2 AFMUTE AF mate control oActive High H=AF mute ON
P2-3 AM/FM AM/FM control oActive Low L=AM
P2-4 LIZH LIZH control oActive High H=LIZH ON
P2-5 VCOI VCOI power control 0 Active Low L=VC01 power ON
P2-6 VC02 VC02 power control oActive Low L=VC02 power ON
P2-7 RFATT RFATT control 0 Active Low L=RF ATT ON
P2-8 - - - - -

S E M I C O N D U C T O R D A T A
1 AT24C08-10SI-2.7 (XA0367
E E P R O M 1 0 2 4 x 8 B i t
NCI ----
114 ZDNC Pin Names
AO CZ 213 — 1 Vcc AO-A2
SDA Address inputs
Serial Data
A1 CZ 3
AT24C08
12 ZD TEST SCL
TEST Serial Clock
Hold at Vss
NCIZZ 411 IZlNC Vss
Vcc Ground +5V
A2 CH 510 ZZISCL
Vss CZ 6 ■ 9= IS D A
NCI— 7 8 ZZ1NC
2 BU4094BF (XA0246
8 - S t a g e S h i f t R e g i s t e r
Function Table
Clock Output
enable Strobe Data
Parallel outputs Serial outputs
Q1 Qn Qs Q's
_r~ L X X 2 2 Q7 No Chg.
—L - LXXZ Z No Chg. Qs
_ r ~ HLXNo Chg. No Chg. Q7 No Chg.
_r ~ H H L LQn-1 Q7 No Chg.
HH H H Qn-1 Q7 No Chg.
^—HXX No Chg. No Chg. No Chg. Qs Z=High Impedance
X= Don't Care
Vdd
Output
Enable
Block Diagram
Q1 PARALLEL qs
OUTPUT
SERIAL
OUTPUT

3 MB1504LPF-G-BND-TF (XA0145
F r e q u e n c y S y n t h e s i z e r
Function Table
FC input P.D.input Do oulput
High or Low fr=fp HiZ
High fr>fp . High
High fr<fp Low
Low fr>fp Low
Low fr<fp High
Reference
oscillator input
terminal OSCin IZZ 116 ZZ1 0R
Reference
oscillator output
terminal OSCout 1 215 = 1 0P
Power supply
terminal for
charge pump Vp IZZ 3214 = l f p
Power supply
terminal
3V 10mA Vcc CZ 403
Ü1 13 = l f r
Charge pump
output terminal Do 1 . 5©12 Z=I FC
Ground terminal GND IZZ 611 = 1 LE
Phase detector output
terminal LD 1—
when locked: LD=H 710 — 1 Data
Prescaler input
terminal fin IZZ 89ZZ1 Clock
Phase detector output
terminal for external
charge pump
Phase detector output
terminal for external
charge pump
Programmable
divider output
terminal
Reference divider
output terminal
Phase switch input
terminal of phase
comparator
Load enable signal
input terminal
terminal
Clock input
terminal
fmax =520MHz
4 NJM2902M (T1 (XA0265
O p e r a t i o n a l A m p l i f i e r s
A Output 1 14 l D Output
A -Input t=Z 213 i D -Input
A +lnput EZ 312 ID +lnput
C _ IO
V+ c z 4
O IO
11 IZIGND
B +lnput IZZ 5 10 __ 1C +lnput
B -Input d691 1C -Input
B Output IZZ 78 1C Output
10

5 NJM7809A (XA0264
9V 2.2A Voltage Regulator
c
Input
Common C
Output C
1c_ -*■ -g
A30»
o2§ 0
>>
6 RH5VA45AA-T1 (XA0208
C - M O S V o l t a g e D e t e c t o r
Equivalent Circuit
,VDD
" 0
HR
vss
J3UT
oin
Q
LI U U
OUT VDD VSS
RH5VA45AA
7 TA75S01F (XA0328
S i n g l e O p e r a t i o n a l A m p l i f i e r s
" ö B ~ t J b b ü
IN(+) Vee IN(-)
8 TA7806F (TE16L (XA0267
6 V 1 A V o l t a g e R e g u l a t o r
Test Circuit
11

Input Power (W Vcon (V
Output Power (W)
Efficiency y {%)
Outpul Power (W}
Efficiency ? (%}
Po , 7 - Vcon

145 147
Fin(Ground
Oulpul Power (W
S 8 3
i— m
T3
O
H TJ <
0 — 0
1 ■ 0
» § <
0 Î 0
*1
ro
s
è S S
Efficiency 7 (%
9 S-AV17 (XA0185
1 4 4 - 1 4 8 M H z 6 0 W RF P o w e r M o d u l e

10 TC35305F (TPI (XA0268
D T M F R e c e i v e r
D2 CZ 1w14 — I D3
D1 CZ 213 = □ D4
OE in 3H12
---- 1 DV
VDD n z 4O
CO
Of 11 ZU CLK
PD r z 5CO
o
cn 10 zu xiN
OSCE 6"n 9ZZI XOUT
SIGIN CZ 7 8 ZZI VSS
Function Table
FL FH Digit OE D4 D3 D2 D1
697 1209 1 H L L L H
697 1336 2 H L L HL
697 1477 3HLL H H
770 1209 4 HL H L L
77D 1336 5 H L HLH
770 1477 6 H LH H L
852 1209 7 H LHHH
B52 1336 eHHL L L
852 1477 9 H H LL H
941 1336 a H H L HL
941 1209 HH L H H
941 1477 #H H H L L
697 1633 A HH H LH
770 1633 0 H HHHL
852 1633 C H H H H H
941 1633 DHL L L L
- - ANY L ZZZ Z
Block Diagram
SIGIN © - Dial
lone
filter
CLK @
OSCE (6
No. Name I/O Description
2 Di O 0E«"L”; Hi impedance, "H"; data is output
D2 0 OE-"L'‘; Hi impedance, "H"; data is output
14 D3 0 OE«'V; Hi impedance, "H“; data is output
13 D4 0OE*"L"; Hi impedance, ”H"; data is output
3 OE 1 When OE is "High", D1-D4 are enable.
4VDD VPower Supply; 5V
5 PD IPD«"Low"; stand by mode
6OSCE 1ControJ terminal of Ihe oscillator stage
7SIGIN [Signal input terminal
BVSS G OV
9 XOUT 0 Crystal terminal (3.579545MH2
10 XIN 1 Crystal terminal (3.579545MHz
11 CLK I/O ”H"; external clock outpul
”L";exlernal clock input
12 DV 0 Data valid
XIN
XOUT■T<D
Timing
generation
circuit
Internal
clock
Reference
Bias circuit -power
supply
$
Timer
control
circuit
Data strobe
Signal -»
judge
circuit -► Latch
&circuit
Matrix
circuit >
Data clear
s
i: :
w
Vdd V ss -W
PD
g>DV
| D 1
2 0 2
Q>qz
3>D4
Do e
13

11 TK10930VTL (XA0223
Characteristic Symbol Min. Typical Max Typical Condition
Supply Current 1 Icc1 6.8 8.9 mA No signal, AM ON
Supply Current 2 Icc2 3.9 5.3 mA No signal, AM OFF
Mixer Conversion Gain Mg 20 dB
Mixer Input Impedance Mz 3.6 Kß DC Test
FM
Limiting Sensitivity Limit 2.0 8.0 MV -3.0dB
Output Voltage Vo1 85 150 230 mVrms 10mVin+/-3kHz DEV
Distortion THD1 1.0 2.0 % lOmVin +/-3kHz DEV
Output Impedance Zo 800 £2 10mVin
Filter Gain Gf 30 38 dB Fin=30kHz, Vo=l00mV
Scan Control Hi Voltage SH 2.3 V Squelch input=2.5V
Scan Control Low Voltage SL 0.3 VSquelch input-OV
Squelch Hysteresis Hys 30 mV
S meter Output Voltage SO 0.05 0.5 V Vin=0mV, RS=68kfl
S meter Output Voltage S1 0.05 0.5 0.9 V Vin=0.01mV, RS=68ki2
S meter Output Voltage S2 0.7 1.2 1.7 V Vin=0.1mV, RS=68k£2
S meter Output Voltage S3 1.2 1.8 2.5 V Vin=1mV, RS=68kQ
S meter Output Voltage S4 1.6 2.3 2.9 V Vin=10mV, RS=68k£2
S meter Output Voltage S5 1.8 2.4 2.9 V Vin=100mV, RS=68ki2
AM
Sensitivity US 20 15 fiV When output is 20mVrms.
Output Voltage Vo2 60 120 160 mVrms 1kHz, 30%, Vin=1mV
Distortion-1 THD2 1.0 2.0 %1kHz, 30%, Vin=1mV
Distortion-2 THD3 2.0 4.0 % 1kHz, 30%, Vin=1mV
S/N Vo1 40 48 dB 1 kHz, 30%, Vin=1 mV
AM OFF Vo -0.3 0.3 % OFF

12 TC4W66FU (TE12L (XA0306
D u a l B i l a t e r a l S w i t c h
IN/OUT 1 n z 1 •8 — 1 VDD
OUT/IN 1 r z 2£7m CONT1
CONT2 n z 305
o> ZH OUT/IN 2
VSS n z 45ZH IN/OUT 2
13 HPC1241H (XA0079
A u d i o P o w e r A m p l i f i e r s
15

14 Transistor, Diode and LED Outline Drawings
Top View

15 LCD Connection
(EL0025
/ e s g l T I s S I
ts s m KL E3 DIAL BBES3 PR! E VS AM iB
• : . i i i i T i T i T r r i n n n n n n T T [ T n n n n n T i T T r T n n n n n m n n n n n T i T T i T n ~ ~ ..........
— o>
00
o
Z o
z
(1 (2 (3 (4 15 {6 (7]
1 2 3 4 5 6 7 8
Pin No. Signal
Name Pin No. 90 COM1 Pin No. 91 COM2 Pin No. 92
COM3 Pin No. Signal Name Pin No. 90 COM1 Pin No. 91 COM2 Pin No. 92
COM3
1 0 >(3b (3 a 21 20 •6c 6b
21 SKIP (2 b (2 a 22 21 TS 7e 7f
32 ATT (1 b (1 a 23 22 7d 7g 7a
4 3 BUSY (1 c (1 d 24 23 VS 7c 7b
54M(2 c (2 d 25 24 AM 8e 8f
6 5 0(3 c (3 d 26 25 8d 8g 8a
76FUNC 2e 2f 27 26 M 8c 8b
872d 2g 2a 28 27 L 25 50
9 8 1b.c 2c 2b 29 COM.1
10 9 KL 3e 3f 30 COM.2
11 10 3d 3g 3a 31 COM.3
12 11 RC 3c 3b 32 28 75 (4 c (4 d
13 12 DIAL 4e 4f 33 29 —(5 c (5 d
14 13 4d 4g 4a 34 30 +(6 c (6 d
15 14 G4c 4b 35 31 RPT (7 c (7 d
16 15 P 5e 5f 36 32 T (7 b (7 a
17 16 5d 5g 5a 37 33 SQ (6 b (6 a
1B 17 DSQ 5c 5b 38 34 SPLIT (5 b (5 a
19 18 PRI 6e 6f 39 35 (4 b (4 a
20 19 6d 6g 6a
SPLIT
17

E X P L O D E D VIEW
1 Bottom View
2 LCD View
FF0031
18

« o * '® ''4
C t O ' '
- { O p * f ^ o c 3 '
« tss&