Alpha Micro AM-210 User manual

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TECHNICAL MANUAL
FOR
AM-21 0
FLOPPY DISK CONTROLLER
CIRCUIT BOARD
Manufactured By
ALPHA MICROSYSTEMS
178B1 SKY PARK NORTH
IRVINE, CALIFORNIA 8271 4

FIRST EDITION
AUGUST 8,1979
REVISIONS INCORPORATED:
EDITION I
DATE
ADI
8/11/80
PROPRIETARY NOTICE
This document and the Information herein disclosed Is the proprietaryprop-
erty of ALPHA MICRO, 17881 Sky Park North, Irvine, California 92714. Any
person
or entity to whom this document is furnished or having possession
thereof, by acceptance, assumes custody thereof and agrees that the doc-
ument Is given in confidence and will not be copied or reproduced in whole
or In part. nor used or revealed to any person In any mannerexcept to meet
the purposes for which It was delivered. Additional rights and obligations
regarding this document and Its contents may be defined by a separate
written
agreement with ALPHA MICROSYSTEMS, and If SO, such separate
written agreement shall be controlling.

USER COMMENTS
TECHNICAL PUBLICATIONS FILE REFERENCE
FROM:
NAME
NOTE: Use this form to communicate any errors,
ADDRESS
suggested changes, or general comments
about this document.
If necessary, ca II us at:
CITY
[phone]
STATE
ZIF-
DOCUMENT:
TITLE/NUMBER/REVISION_------------------------
COMMENTS:
,
. ',-------------------~----------------------------------------------------------------------------------------
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FOLD, STAPLE & MAIL
ZZ F .a0002'() 1

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~ ~ 17BRl Sky Park North
Irvine. California
tJ2714
ATTN: EDUCATIONAL SERVICES DIVISION
PLACE
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Paragraph
1.0
1.1
1.2
2.0
2.1
2.2
2.2. 1
2.2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3" 7
2 •
.3.8
3.0
3.1
3.2
3.3
3 .. 4
TABLE OF CONTENTS
Page
SECTION 1 GENERAL DESCRIPTION
. .. ..
1-1
Introduction • .. • . . . .
Circuit Board Description
Application • . • • .. .. .
. . . . . . 1- 1
• • . • . . 1- 1
SECTION 2 OPERATING DATA
Introduction . . . . .. . .. . .. .
Capabilities and Specifications
. . . .
2-1
Interface Description and Wiring • ..
S-100 Bus Inter ce .........
Floppy Drive Interface •.
User Options . • . . . .
• 2-1
2-1
• 2-1
· 2-6
• 2-9
Bootstrap Header Option
I/O Port Address . • • . . . . . . . . . • .
2-9
• • .. •• • 2- 9
2-9
Master Clock Frequency Option
Vectored Interrupt Option
. . . . . .
.. 2-9
Seek Complete Interface Line Option .. 2-10
Software Control Step Rate Option .•. 2-10
Data Separator Timing Opt~~n .• . .... 2-10
Write Pre-Compensation Options .. • . 2-11
SECTION 3 PROGRAMMING
In t roduct ion • ..
Addressing ....
. . . . . . . . . . . .
. . . . . . . . . . . .
External Control Registers .
Random Access Memory
Diskette Formatting
i
. ..
. . . .
. . . .
.. • 3- 1
. • 3-1
.. 3-1
• .. 3- 6
• 3- 7

, , 'J ,~
3.5
3.6
4.0
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4. 1. 8
4.1.9
4.1.10
4.1.11
4 .. 2
4.2 .. 1
4.2.1.2
4.2.1.3
4.2.1.4
4.2.1.5
4.2.1.6
4.2.1.7
4.2.1.8
4,,2.1.9
4.2.1.10
4.2.1.11
TABLE OF CONTENTS (Continued)
SECTION 3 PROGRAMMING (Continued)
Interrupts • .. • .. .
Bootstrap PROM. .. •..
• • 3- 7
3- 8
SECTION 4 FUNCTIONAL THUORY OF OPERATION
.. .. 4 - 1
In t roduct ion .. . . ..
Circuit Board Operation
Data Out Port . . •
.. • .. .. 4- 1
Da ta In Port . . .. . .
Bootstrap Circuitry~
I/O Address Circuitry
Command Generator
RAM and Control Circuitry
ternal Status and Control Registers
Data-Clock Separator . .. .. .. • .. . • ..
Write Pre-Compensation .
PRDY Control Logic ~ . ..
.. 4-18
.. . 4-18
.. .. 4- 18
.. .. .. 4- 19
.. 4 -19
.. • 4- 19
.. .. .. 4- 20
. 4-20
.. 4-22
.. 4-22
DRQ Processor .... .. .. . .. .. .. . 4-23
Circuit Module Description ............ 4-25
Floppy Disk Formatter/Controller Description
CUI) .. .. • .. • • .. • .. • • .. .. .. 4-25
Organization.. . .. .. . . ...... 4-30
Processor Interface .............. 4-33
Floppy Disk Interface .................... 4-34
Head Positioning.. .. .. • • ... .. ....... 4-35
Disk Read Operations .... .. ............ 4-37
Disk Write Operation ........
Command Description
Type I Cornman ds
Type I I Commands, .. ..
Type III Commands
ii
. . . . . . . . .
. . . . .. ...
. . . . . . . . .
.. 4- 38
. 4- 39
.. 4-40
.. 4- 46
4-51

~-.)
0
TABLE OF CONTENTS (Continued)
SECTION 4 FUNCTIONAL THEORY OF OPERATION (Continued)
4.2.1.12
4 .. 2.1.13
4.2.1.14
4.2.1.15
4.2.1.16
4.2.1.17
4.2.1.18
4.2.2
4,.2. 3
4.2.4
4.2.5
4.2.6
4.2. 7
4.2.B
4•2 .. 9
4.2. 10
4.2.11
4.2.12
4.2.13
4.2.14
4.2.15
4.2.16
4.2.17
4.2.18
4.2.19
4.2.20
4.2.21
4.2.22
Type IV Commands . . ..
. . . . . . . .
4-54
Status Description . . • .. . •... 4-54
Formatting the Disk . .... . ........ 4-56
IBM 3740 Fa rm at - 12 8 By t es / Sec tor . .... 4- 58
IBM System 34 Format -256 Bytes/Sector ... 4-58
Non IBM Formats .... ......... .. 4-59
Timing Characteristics ...... ..
1024 x 4 Bit Static RAM (U30, U31) ...
BK Erasable PROM (U21) .. .. .. .. • .. • ..
...... 4-60
.. 4-63
..... 4-66
BCD/Decimal Decoder/Driver (U13) ..
Tri-State Buffers (U16) ......
.. .. .. .. .. 4- 68
4-69
Bus Comparator (U25, U26) . . . . . .
4- 70
D Positive-Edge-Triggered Flip-Flops with
Preset and Clear (U12) .................. 4-71
Tri - State Oct al Buffers (U36) ........ .. I" .. 4- 71
Tri-State Buffers (U39)
Dual J-K Negative-Edge Triggered Flip-Flops
With Preset (UB) .. • .. .. ... .. ....
Dual Retriggerable One-Shots with Clear
(U14, UIS) ...................... ..
Decoder (U29) . . .
.". . . . . . . . .
Data Selector/Multiplexer (U17) . . . . .
.. 4- 72
4-72
• 4- 73
.. 4- 74
.. 4- 75
• 4- 76
TriMState Inverter Buffer (U33, U40) •
Tri-State Octal Buffer (U41) .......
• .. 4- 76
Four-Bit Binary Ripple Counter (U23). .. 4-77
Voltage Controlled Oscillator (U12) ........ 4-78
Tri-State D Flip-Flops (U43) ........... 4-79
Dual 4-Bit Binary Counter (U9, U20) ........ 4-80
Logic Delay Module (U6) ................ 4-81
Programmable Read Only Memory' (U19) .. 4-82
Octal D-Type Flip-Flop With Clear (U34~ U35) 4-83
iii

5.0
5. 1
5. 2
5 • .3
5• 3. 1
5.3.2
5.3.2.1
5.3.2.2
5.3.2.3
5 • .3.2.4
5.3.2.5
TABLE OF CONTENTS (Continued)
SECTION 5 MAINTENANCE AND TROUBLESHOOTING
Introduction . . . . . .
Circuit Board Checkout.
Warranty Procedures . . .
Troubleshooting Procedures .
Operational Test ...
. 5-1
.. 5- 1
5-2
5-2
5-2
Diagnostic Procedures ... ...• 5-3
Ini tial Register Check eDDTST) . . • .. 5- 4
Floppy Controller Chip Test (1791T) .•.. 5-6
Floppy Drive Seek Test and Data Separator
Calibration (SEEK) • • . • . • . • . 5-7
Floppy Interface Drive Test (FTST) . • • 5- 11
Evaluation Procedure ..
. . . . . . . . .
5-16
SECTION 6 SCHEMATIC AND PARTS LIST
iv

LIST OF ILLUSTRATIONS
Figure
Page
1-1 AM-2l0 Floppy Disk Controller Simplified
Block Diagram .....•.••••••..•. 1-3
4-1 AM-210 Floppy Disk Controller Functional Block
4-2
4-3
4-4
Diagram ..•. ~ • • •• .•• . . 4-3
Data Separator Timing • • • • • • • • • •
PRDY Control Logic Timing •• • •••
Floppy Disk Formatter/Controller Pin Connec-
tions . . • . . . . . . . . . . . .
.. . . . .
· 4- 21
• 4-23
· 4-25
4-5 Floppy Disk Formatter/Controller Module Block
4-6
4-7
4-8
4-9
4-10
Diagram • • . . . . • . . • .
4-31
Type I Command Flow • . • . .
Type II Command Flow •.••
Type III Command Write Track
. . . ...
· 4-41
• 4-47
· 4-53
IBM Track Format
Read Enable Timing
. . . . . . . .
. . . . • • • • • • 4- 57
. . . . . . • •
•. 4- 60
4-11 Write Enable Timing. .• . ••.••••• 4-61
4-12 Input Data Timing. . . •• • ••• 4-62
4-13 Miscellaneous Timing . • • • • • •• • 4-62
4-14
Static RAM Connections ..•.•••.•. 4-63
4-15
RAM Read and Write Timing • • • •• • ••• 4-64
4-16 8K UV Erasable PROM Connections ••••••. ~ 4-66
4-17 8K UV Erasable PROM Timing •••••••..• 4-66
4-18 Decoder/Driver Logic and Connections ••••• 4-68
4-19 Trl-State Buffer Connections ••• 4-69
4-20 Bus Comparator Connections ••..•••••• 4-70
4-21 D Flip-Flop Connections • • • . • • • • • • 4-71
4-22
4-23
4-24
Tri-State Octal Buffer Connections.
Tri-State Buffer Connections ••••
J-K Flip-Flop Connections .••••
v
4-71
· 4- 72
4-72

Figure
4-25
4-26
4-27
4-28
4- 29
4-30
4-31
4-32
4-33
4'- 34
4-35
4-36
LIST OF ILLUSTRATIONS (Continued)
One-Shot Connections
Decoder Connections . . . . . . . .
. . . . . .
Data Selector/Multiplexer Connections •.
Tri-State Inverter Bu
r Connections .
Tri-State Buffer Connections
Page
• . 4- 73
. . • 4- 74
• • • 4- 75
4- 76
4- 76
Four-Bit Binary Ripple Counter Connections .•. 4-77
Volt Controller Oscillator Connections. 4-78
Tri - ate D FI ip- Flop Connect ions . . . • • . • 4- 79
4-Bit Binary Counter Connections. • • • .. 4-80
Logic Delay Module Diagram and Connections .•• 4-81
PROM Connections and I/O Circuits •. . •. 4-82
D Flip-Flop Connections . • . • . . • • 4-83
vi

LIST OF TABLES
Table
Page
2-1 AM-210 Specifications •.•.•..•••
• 2- 2
2-2 5-100 Bus Interface Signals List ••••
• 2-3
2- 6
2-3 AM-2I0 Floppy Disk Interface Signals List.
3-1
I/O Port Definitions
. . • • 3- 2
3-2 External Control Register No. 1 Output Func-
t ions (X6) • • • • • •• • • • • • • • • • 3- 3
3-3 External Control Register No. I Input Functions
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4,-14
4-15
4-16
6-1
(X6)
. . . . . . . . . .
3-4
External Control Register No.2 Functions (X7). 3-5
AM-210 Signals List. •• .••.•• • 4-4
S-100 Bus Interface Signals List •.••••• 4-11
AM-210 Floppy Disk Interface Signals List ••• 4-14
Floppy Disk Formatter/Controller Signal List .• 4-26
AM- 210 Re gi s ter Addre s's es • • • • • • • • • • • 4- 30
Stepping Rates
• • • • • • 4- 35
• • • • • • • 4- 40
. . . . . . •
4-43
Command Summary • • • • • •
Flag Summary Type I Commands
Flag Summary Type II Commands . . . • •
4- 46
Control Bytes For Initialization
• • 4- 52
Status Register Summary • . . • • • • •• . 4-55
Status For Type I Commands •••••••••. 4-55
Status Bits for Type II and III Commands .•.• 4-56
Read Operations Timing
Write Operations Timing
Miscellaneous Timing
Component Cross-reference List
vii
· 4- 60
• • • 4- 61
4-62
• • 6-1

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SECTION 1
GENERAL DESCRIPTION
1 • 0
INTRODUCTION
This manual provides operating and maintenance instructions for
the AM-210 Floppy Disk Controller circuit board manufactured by
Alpha Microsystems located in Irvine, California. Circuit board
description, operating and usage instructions, programming, theory
of operation, and maintenance instructions are included to provide
the user with the information necessary to utilize this circuit board
to its full capability.
1.'1 CIRCUIT BOARD DESCRIPTION
The AM-210 circuit board provides interface capability between the
S-100 Bus system and several of the popular eight inch and five
inch floppy disk drives. A floppy controller microprocessor and a
102~ x 8 bit Random Access Memory (RAM) provide block transfers of
da tab et wee nth e s ys t em and up toe i gh t flo pPy dr i ve s • ARe adO n1y Me 1111
(ROM) is contained on the board to provide an optional boot load prograJ
A simplified block diagram of the circuit board is shown in
Figure 1-1. For a complete detailed description of circuit board
operation, see Section 4 of this manual.
1.2 APPLICATION
The AM-210 is fully compatible with the standard S-100 Bus system and
the Alpha Micro 8 and 16-bit bus systems. Jumpers on the circuit
board that provide for user selected 'features are described in
Section 2. The AM-210 controls both tIle standard 8" floppy and the
5" mini-floppy drives. Both single and double density formats are
accommodated with both single and double sided disk. Specific
configurations of the AM-210 are as follows:
AM-210-01
AM-210-02
AM-21 0-03·
AM-210-04
AM-210-05
PerSci 277 Drive
Wangco/Shugart Drives
Mini-floppy Drives
PerSci 299 Drive
CDC 9406-3 Drives
January 2, 1980
1-1

2.0 INTRODUCTION.
SECTION 2
OPERATING DATA
This section contains information on the use of the AM-2l0
Floppy Disk Controller circuit board. Capabilities, speci-
fications, interface wiring and user options are described
for the successful integration of the board into the user's
system.
2.1 CAPABILITIES AND SPECIFICATIONS.
This circuit board operates from the standard 5-100 Bus
structure and the Alpha Micro 16-bit Bus to provide interface
capability to several of the popular floppy disk drives.
The AM-2ID operates as a programmed I/O device to transfer
data between floppy disk drives and system memory under CPU
control. Specifications for the AM-210 circuit board are
contained in Table 2-1.
2.2 INTERFACE DESCRIPTION AND WIRING.
The AM-210 Floppy Disk Controller provides interface capability
between the standard S-100 Bus and floppy disk drives.
2.2.1 5-100 BUS INTERFACE.
The AM-21D circuit board is fully 5-100 Bus compatible. The
board and its associated floppy disk drives are addressed
through the standard address lines and data is transferred
through the standard data in and data out lines. The S-100
Bus connections are made via the bottom edge connector and
are listed in Table 2-2. For a complete description of these
signals and their operation in the AM-2IO, see Section 4.1
of this manual.
2-1
"'~':' """'~"'."Al ",..,·,,.,,..,....; ...... ~' .... ~I~'!~ ..... A~~_ •• ~ •• !_~~_ w, ,1_
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Table 2-1. AM-210 Specifications
PARAMETER SPECIFICATIONS
System Interface
Disk Interface
Number of Drives
I/O Ports
Disk Formats
Disk Types
Step Rate
Bootstrap Program
Interrupts
Standard S-lOO Bus or Alpha Micro Bus
for CPU and system memory.
Compatible with most 8
1t
floppy disk drives.
Separate connector interfaces with 5"
minifloppy drives.
Up to eight drives can be controlled by
one AM-2ID circuit board.*
Eight I/O ports utilized for data and
control.
Accommodates single and double density
formats: IBM 3740 Single Density (PM)
IBM 34 Double Density (MFM)
Compatible with single or double sided disks.
Variable step rate including sriftware
programmable.
8 x 1024 bit PROM containing bootstrap
program. Jumper block provides for
boot-no boot option.
Multiple level interrupt capability, user
selected.
*Eight drives with binary drive selection, four with radial drive
selection. Refer to drive manual for information.
2-2

Table 2-1 (Cont.).! AM-210 Secifications
PAHAMETER
SPECIFICATIONS
Read
Capability
Partial
or
full sector
read
capability.
Data
Buffer
Contains
1024
x 8 RAM memory
for
data
transfer
operations.
Data
Separator
PLO
data
separator-software
programmable
for both
single
and
double density formats
in
both
standard
and
mini-floppy
configu-
rations.
Write
Contains
write
precompensation
circuitry
Precompensation
that
is
jumper selectable
for
delays
from
50
to
greater than
500
nanoseconds.
~1emory
Control
SoftvJare control
of
PROM
and system
memory
contained
in the same
address
space.
Table 2-2.
$-100 Bus Interface Signals List
MNEMONIC
fJAHE
PIN
AO
Address
0
79
A1 Address
1 80
A2
Address
2
81
A3
Address
3
..
31
1\ 4
Address
4 30
A5
Address
5 29
A6 Address
6 82
1\7
Address
7 83
AS Address
8 84
A9 Address
9 34
A10
Address
10
37
~~anuary 2, 1980
2-3

Table 2-2 (Cant.). S-lOO Bus Interface Signals List
MNEMONIC
NAME
PIN
All
Address
11
87
Al2
Address
12
33
A13
Address
13
85
Al4
Address
14
86
A15
Address
15 32
DATAIN
0
Input Data Bit
0 95
DATAIN
1
Input Data Bit 1
94
DATAIN 2 Input Data
Bit
2 41
DATAIN 3
Input Data
Bit
3
42
DATAIN
4
Input Data
Bit 4 91
DATAIN 5
Input Data Bit
5
92
DATAIN
6
Input Data
Bit 6
93
DATAIN
7
Input
Data Bit
7
43
DATAOUT 0
Qutput
Data
Bit
0
36
DATAOUT 1
Output
Data
Bit 1 35
DATAOUT
2
Output
Data Bit 2 88
DATAOUT
3
Output
Data Bit 3
89
DATAOUT
4
Output
Data
Bit
4 38
DATAOUT
5
Output Data
Bit 5 39
~ .
DATAOUT
6
Output Data
Bit 6
40
DATAOUT
7
Output Data Bit
7
90
PDBIN
Data Bus
In
78
PHANTOM Phantom
67
PRDY
Ready
72
PWR Write St rob e 77
2-4

Table 2-2 (Cont.). 5-100 Bus Interface Signals List
MNEMONIC
NAME PIN
PRESET
Reset
7S
SINP
I/O
Input
Cycle
46
SOUT
I/O
Output Cycle 4S
I
VIa
Interrupt
0 4
VII
'Interrupt
1 S
VI2
Interrupt 2 6
VI3
Interrupt
3 7
--
VI4
Interrupt
4 B
VIS
Interrupt S 9
VI6
Interrupt
6
10
VI7
Interrupt
7
11
~2
Phase 2 clock
24
+8VDC +8VDC
1,51
+16VDC
+16VDC Z-
, .
-16VDC
-16VDC
52
GND Ground
SO,
100
2-5
,....."......,---,." ... _ ....... .