AMD XILINX 7 Series User manual

7 Series FPGAs and
Zynq-7000 SoC XADC Dual
12-Bit 1 MSPS
Analog-to-Digital Converter
User Guide
UG480 (v1.11) June 13, 2022
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Table of Contents
Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1: Introduction and Quick Start
XADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
XADC Pinout Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Instantiating the XADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: Analog-to-Digital Converter
ADC Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: XADC Register Interface
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DRP JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Zynq-7000 SoC Processing System (PS) to XADC Dedicated Interface . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 4: XADC Operating Modes
Single Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Automatic Channel Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Sequencer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Multiplexer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Maximum and Minimum Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Automatic Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5: XADC Timing
Continuous Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Event-Driven Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dynamic Reconfiguration Port (DRP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 6: Application Guidelines
Reference Inputs (VREFP and VREFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Analog Power Supply and Ground (VCCADC and GNDADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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External Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PC Board Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendix 7: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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Preface
About This Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a
common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family
is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is
optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high volume
applications. The Kintex®-7 family is an innovative class of FPGAs optimized for the best
price-performance. The Virtex®-7 family is optimized for highest system performance and capacity. The
Zynq®-7000 SoC device integrates a feature-rich dual-core Arm® Cortex™-A9 based processing system
(PS) and 28 nm Xilinx programmable logic (PL) in a single device.
This guide serves as a technical reference describing the 7 series FPGAs and Zynq-7000 SoC XADC, a dual
12-bit, 1 MSPS analog-to-digital converter with on-chip sensors. This user guide is part of an overall set of
documentation on the 7 series FPGAs and Zynq-7000 SoC devices, which is available on the Xilinx website
at
www.xilinx.com/documentation.
Guide Contents
This manual contains these chapters:
•Chapter 1, Introduction and Quick Start
•Chapter 2, Analog-to-Digital Converter
•Chapter 3, XADC Register Interface
•Chapter 4, XADC Operating Modes
•Chapter 5, XADC Timing
•Chapter 6, Application Guidelines
•Appendix 7, Additional Resources and Legal Notices
Example design files and Tcl console examples for the Vivado® Hardware Manager can be found in the ZIP
file that accompanies this user guide.
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Chapter 1
Introduction and Quick Start
This chapter provides a brief overview of the Xilinx 7 series FPGAs XADC functionality. The XADC is
available in all Artix®-7, Kintex®-7, Virtex®-7, and Zynq®-7000 SoC devices. The XADC is also available
in many, but not all Spartan®-7 devices. To identify specific devices that support the XADC block, consult
the Spartan-7 family overview in DS180, 7 Series FPGAs Overview [Ref 11].
The XADC is the basic building block that enables analog mixed signal (AMS) functionality which is new
to 7 series FPGAs. By combining high quality analog blocks with the flexibility of programmable logic, it is
possible to craft customized analog interfaces for a wide range of applications. See www.xilinx.com/ams
for more information.
This chapter contains only key information to allow a basic understanding of the XADC block. With this
introduction, you can learn the pinout requirements and determine how to instantiate basic functionality
in their designs. Subsequent chapters provide more detailed descriptions of the XADC functionality.
XADC Overview
The XADC includes a dual 12-bit, 1 Mega sample per second (MSPS) ADC and on-chip sensors. The ADCs
and sensors are fully tested and specified (see the respective 7 series FPGAs data sheet). The ADCs provide
a general-purpose, high-precision analog interface for a range of applications. Figure 1-1 shows a block
diagram of the XADC. The dual ADCs support a range of operating modes, for example, externally
triggered and simultaneous sampling on both ADCs (see Chapter 4, XADC Operating Modes) and various
analog input signal types, for example, unipolar and differential (see Chapter 2, Analog-to-Digital
Converter). The ADCs can access up to 17 external analog input channels.
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Chapter 1: Introduction and Quick Start
Notes relevant to Figure 1-1:
1. Zynq-7000 SoC devices only.
The XADC also includes several on-chip sensors that support measurement of the on-chip power supply
voltages and die temperature. The ADC conversion data is stored in dedicated registers called status
registers. These registers are accessible through the FPGA interconnect using a 16-bit synchronous read
and write port called the dynamic reconfiguration port (DRP). ADC conversion data is also accessible
through the JTAG TAP, either before (pre-configuration) or after configuration. For JTAG TAP, users are not
required to instantiate the XADC because it is a dedicated interface that uses the existing FPGA JTAG
infrastructure. As discussed later, if the XADC is not instantiated in a design, the device operates in a
predefined mode (called default mode) that monitors on-chip temperature and supply voltages.
XADC operation is user defined by writing to the control registers using either the DRP or JTAG interface.
It is also possible to initialize these register contents when the XADC is instantiated in a design using the
block attributes.
Differences between Virtex-5 and Virtex-6 System Monitors
For Virtex-5 and Virtex-6 FPGA System Monitor users, the XADC functionality is fully backward
compatible with legacy System Monitor designs. The XADC functionality and interface are familiar to
those who have previously designed with the System Monitor. System Monitor designs are automatically
retargeted to the XADC site by the software tools.
However, the XADC block in 7 series FPGAs contains a large number of new features and enhancements
detailed in subsequent chapters. The new functionality is enabled by initializing previously undefined
status registers and bit locations. Old System Monitor designs that did not initialize these new registers or
bit locations behave exactly the same way as before.
X-Ref Target - Figure 1-1
Figure 1-1: XADC Block Diagram
Mux
VP_0
VREP_0
Die
Temperature
VCCINT
VCCAUX
VCCBRAM
VCCPINT(1)
VCCPAUX(1)
VCCO_DDR(1)
VREFN_0
Mux
Temperature
Sensor
Supply
Sensors
VN_0
VAUXP[0]
VAUXN[0]
12-bit,
1 MSPS
ADC A
°C
VAUXP[12]
VAUXN[12]
VAUXP[13]
VAUXN[13]
VAUXP[14]
VAUXN[14]
VAUXP[15]
VAUXN[15]
12-bit,
1 MSPS
ADC B
64 x 16 bits
Read/Write
64 x 16 bits
Read Only
Control
Registers
Status
Registers
On-Chip Ref
1.25V
JTAG FPGA
Interconnect
External
Analog
Inputs
DRP
X17015-110817
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Chapter 1: Introduction and Quick Start
XADC Pinout Requirements
Dedicated Package Pins
All XADC dedicated pins are located in bank 0 and thus have the _0 suffix in the package file names.
Figure 1-2 shows the basic pinout requirements for the XADC. There are two recommended
configurations. On the left, the XADC is powered from VCCAUX (1.8V) and uses an external 1.25V reference
source. The external reference delivers the best performance in terms of accuracy and thermal drift. A
ferrite bead is used to isolate the ground reference for the analog circuits and system ground. An additional
low-pass filter for VCCAUX supply will similarly improve the ADC performance. See Chapter 6,
Application Guidelines for more information. Shared or common ground impedance is the most common
way to introduce unwanted noise into analog circuits.
It is also possible to use an on-chip reference for the ADCs. To enable the on-chip reference source, the
VREFP pin must be connected to ground as shown on the right of Figure 1-2. Where only basic on-chip
thermal and supply monitoring is required, using the on-chip reference provides good performance. Users
should consult the respective data sheet to see the accuracy specifications when using the external and
on-chip reference sources. Table 1-1 lists the pins associated with the XADC and the recommended
connectivity.
Note: It is also important to place the 100 nF decoupling capacitors as close as possible to the package balls to
minimize inductance between the decoupling and package balls.
X-Ref Target - Figure 1-2
Figure 1-2: XADC Pinout Requirements
ADC
Filter VCCAUX Supply
GNDADC
VREFN
10 μF
1.25V + 0.2%
50 ppm/°C 100 nF
VN
VP
100 nF 470 nF
VREFP VCCADC
1.8V – 5V
ADC
Filter VCCAUX Supply
GNDADC
VREFN
VN
VP
100 nF 470 nF
VREFP VCCADC
Ferrite bead for high frequency
noise isolation GND GND
Ferrite bead for high frequency
noise isolation
Package Pins
Use External Reference IC Enable On-Chip Reference
VCCAUX (1.8V ± 5%)
VCCAUX (1.8V ± 5%)
X17016-072318
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Table 1-1: XADC Package Pins
Package Pin Type Description
VCCADC_0 Power supply
This is the analog supply pin for the ADCs and other analog circuits in the
XADC. It can be tied to the 1.8V VCCAUX supply; however, in a mixed-signal
system, the supply should be connected to a separate 1.8V analog, if available.
See Analog Power Supply and Ground (VCCADC and GNDADC), page 64 for more
information. This pin should never be tied to GND. The pin should be tied to
VCCAUX even if the XADC is not being used.
GNDADC_0 Power supply
This is the ground reference pin for the ADCs and other analog circuits in the
XADC. It can be tied to the system ground through an isolating ferrite bead as
shown in Figure 1-2. In a mixed-signal system this pin should be tied to an
analog ground plane if available, in which case the ferrite bean is not required.
See Analog Power Supply and Ground (VCCADC and GNDADC), page 64 for more
information. This pin should always be tied to GND even if the XADC is not
being used.
VREFP_0 Reference voltage
input
This pin can be tied to an external 1.25V accurate reference IC (±0.2% or
±9 LSBs at 12 bits) for best performance of the ADCs. It should be treated as an
analog signal that together with the VREFN signal provides a differential 1.25V
voltage. By connecting this pin to GNDADC (see Figure 1-2), an on-chip
reference source (±1% or ±41 LSBs at 12 bits) is activated. This pin should
always be connected to GNDADC if an external reference is not supplied. See
Reference Inputs (VREFP and VREFN), page 64 for more information.
VREFN_0 Reference voltage
input
This pin should be tied to the GND pin of an external 1.25V accurate reference
IC (±0.2%) for best performance of the ADCs. It should be treated as an analog
signal that together with the VREFP signal provides a differential 1.25V
voltage. This pin should always be connected to GND even if an external
reference is not supplied. See Reference Inputs (VREFP and VREFN), page 64 for
more information.
VP_0 Dedicated analog
input
This is the positive input terminal of the dedicated differential analog input
channel (VP/VN). The analog input channels are very flexible and support
multiple analog input signal types. For more information, see Analog Inputs,
page 20. This pin should be connected to GND if not used.
VN_0 Dedicated analog
input
This is the negative input terminal of the dedicated differential analog input
channel (VP/VN). The analog input channels are very flexible and support
multiple analog input signal types. For more information, see Analog Inputs,
page 20. This pin should be connected to GND if not used.
_AD0P_ to
_AD15P_(1)(2)
Auxiliary analog
inputs/digital
I/O
These are multi-function pins that can support analog inputs or can be used as
regular digital I/O (see Figure 1-1). These pins support up to 16 positive input
terminals of the differential auxiliary analog input channels (VAUXP/VAUXN).
The analog input channels are very flexible and support multiple analog input
signal types. For more information, see Analog Inputs, page 20. When not
being used as analog inputs, these pins can be treated like any other digital
I/O.
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Chapter 1: Introduction and Quick Start
Note: Chapter 6, Application Guidelines, should be consulted before commencing any PC board layout. Board layout
and external component choices can greatly impact the performance of the ADCs.
External Analog Inputs
Apart from a single dedicated analog input pair (VP/VN), the external analog inputs use dual-purpose
I/O. These FPGA digital I/Os are individually nominated as analog inputs when the XADC is instantiated
in a design. This document refers to these analog inputs as auxiliary analog inputs. A maximum of 16
auxiliary analog inputs are available. The auxiliary analog inputs are enabled by connecting the analog
inputs on the XADC primitive to the top level of the design. When enabled as analog inputs, these package
balls are unavailable as digital I/Os. It is also possible to enable the auxiliary analog inputs
preconfiguration (for example, for PCB diagnostics) through the JTAG TAP (see JTAG DRP Commands for
more information.)
All analog input channels are differential and require two package balls. Typically, the auxiliary analog
inputs are allocated evenly over banks 15 and 35. However, users should consult the pinout information in
UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide [Ref 2] for a particular device
and package combination. Analog-capable I/O have the ADxP or ADxN suffix on the I/O name in the
package files. For example, auxiliary analog input channel 8 has associated package ball names ending
with AD8P and AD8N. See UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide
[Ref 2] for more information. The auxiliary analog inputs have a fixed package ball assignment and cannot
be moved.
Auxiliary analog inputs are supported differently in Vivado® tools when compared to ISE tools. The
auxiliary analog inputs do not require any user-specified constraints or pin locations in ISE tools. ISE
external auxiliary inputs do not need an I/O standard setting to be added to your constraints file (UCF) or
in the PlanAhead™ design tool. In Vivado design tools, the auxiliary analog inputs must be assigned to the
associated pin location.
_AD0N_ to
_AD15N_(1)(2)
Auxiliary analog
inputs/digital
I/O
These are multi-function pins that can support analog inputs or can be used
as regular digital I/O (see Figure 1-1). These pins support up to 16 negative
input terminals of the differential auxiliary analog input channels
(VAUXP/VAUXN). The analog input channels are very flexible and support
multiple analog input signal types. For more information, see Analog Inputs,
page 20. When not being used as analog inputs, these pins can be treated like
any other digital I/O.
Notes:
1. FPGA I/Os that are analog input-enabled contain the _ADxP_ and _ADxN_ designation in the package file name, for example,
IO_L1P_T0_AD0P_35 is the input pin for analog auxiliary channel VAUXP[0]. IO_L1N_T0_AD0N_35 is the input pin for analog
auxiliary channel VAUXN[0]. For more information, see UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide
[Ref 2].
2. Auxiliary channels 6, 7, 13, 14, and 15 are not supported in Kintex-7 devices. Some auxiliary analog channels might also not be
supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. You should consult the package file for
the device.
Table 1-1: XADC Package Pins (Cont’d)
Package Pin Type Description
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Chapter 1: Introduction and Quick Start
Auxiliary analog inputs must be connected to the top level of the design.
Note: Auxiliary channels 6, 7, 13, 14, and 15 are not supported on Kintex-7 devices. Some auxiliary analog channels
might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. Users
should consult the package file for the device.
Instantiating the XADC
As mentioned previously, it is not necessary to instantiate the XADC in a design to access the on-chip
monitoring capability. However, if the XADC is not instantiated in a design, the only way to access this
information is through the JTAG test access port (TAP). To allow access to the status registers
(measurement results) from the FPGA logic, the XADC must be instantiated. These subsections give a brief
overview of the XADC primitive (ports and attributes).
XADC Ports
Figure 1-3 shows the ports on the XADC primitive, and Table 1-2 describes the functionality of the ports.
X-Ref Target - Figure 1-3
Figure 1-3: XADC Primitive Ports
RESET
CONVSTCLK
CONVST
DI[15:0]
DO[15:0]
DADDR[6:0]
DWE
DEN
DCLK
DRDY
Dynamic
Reconfiguration Port
(DRP)
CONTROL
and CLOCK CHANNEL[4:0]
MUXADDR[4:0]
JTAGBUSY
JTAGMODIFIED
JTAGLOCKED
OT
ALM[7:0]
EOC
EOS
BUSY
XADC
STATUS
ALARMS
External
Analog
Inputs
VP
VN
VAUXP[15:0]
VAUXN[15:0]
X17017-050422
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Chapter 1: Introduction and Quick Start
Table 1-2: XADC Port Descriptions
Port I/O Description
DI[15:0] Inputs Input data bus for the DRP.(1)
DO[15:0] Outputs Output data bus for the DRP.(1)
DADDR[6:0] Input Address bus for the DRP.(1)
DEN(2) Input Enable signal for the DRP.(1)
DWE(2) Input Write enable for the DRP.(1)
DCLK Input Clock input for the DRP.(1)
DRDY(2) Output Data ready signal for the DRP.(1)
RESET(2) Input
Asynchronous reset signal for the XADC control logic.
RESET will be deasserted synchronously to DCLK or the
internal configuration clock when DCLK is stopped.
CONVST(3) Input
Convert start input. This input controls the sampling
instant on the ADC(s) inputs and is only used in event
mode timing (see Event-Driven Sampling, page 61). This
input comes from the general-purpose interconnect in the
FPGA logic.
CONVSTCLK(3) Input
Convert start clock input. This input is connected to a clock
net. Like CONVST, this input controls the sampling instant
on the ADC(s) inputs and is only used in event mode
timing. This input comes from the local clock distribution
network in the FPGA logic. Thus, for the best control over
the sampling instant (delay and jitter), a global clock input
can be used as the CONVST source.
VP, VNInput
One dedicated analog input pair. The XADC has one pair of
dedicated analog input pins that provide a differential
analog input. When designing with the XADC feature but
not using the dedicated external channel of VPand VN, you
should connect both VPand VNto analog ground.
VAUXP[15:0],
VAUXN[15:0] Inputs
Sixteen auxiliary analog input pairs. In addition to the
dedicated differential analog input, the XADC can access
16 differential analog inputs by configuring digital I/O as
analog inputs. These inputs can also be enabled
pre-configuration through the JTAG port (see DRP JTAG
Interface, page 39).
ALM[0](2) Output Temperature sensor alarm output.
ALM[1](2) Output VCCINT sensor alarm output.
ALM[2](2) Output VCCAUX sensor alarm output.
ALM[3](2) Output VCCBRAM sensor alarm output.
ALM[4](4) Output VCCPINT sensor alarm output.
ALM[5](4) Output VCCPAUX sensor alarm output.
ALM[6](4) Output VCCO_DDR sensor alarm output.
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ALM[7](2) Output Logic OR of bus ALM[6:0]. Can be used to flag the
occurrence of any alarm.
OT(2) Output Over-Temperature alarm output.
MUXADDR[4:0] Outputs
These outputs are used in external multiplexer mode. They
indicate the address of the next channel in a sequence to be
converted. They provide the channel address for an
external multiplexer (see External Multiplexer Mode,
page 52).
CHANNEL[4:0] Outputs
Channel selection outputs. The ADC input MUX channel
selection for the current ADC conversion is placed on these
outputs at the end of an ADC conversion.
EOC(2) Output
End of conversion signal. This signal transitions to
active-High at the end of an ADC conversion when the
measurement is written to the status registers (see
Chapter 5, XADC Timing).
EOS(2) Output
End of sequence. This signal transitions to active-High
when the measurement data from the last channel in an
automatic channel sequence is written to the status
registers (see Chapter 5, XADC Timing).
BUSY(2) Output
ADC busy signal. This signal transitions High during an
ADC conversion. This signal also transitions High for an
extended period during an ADC or sensor calibration.
JTAGLOCKED(2) Output
Indicates that a DRP port lock request has been made by the
JTAG interface (see DRP JTAG Interface, page 39). This
signal is also used to indicate that the DRP is ready for
access (when Low).
JTAGMODIFIED(2) Output Used to indicate that a JTAG write to the DRP has occurred.
JTAGBUSY(2) Output Used to indicate that a JTAG DRP transaction is in progress.
Notes:
1. The DRP is the interface between the XADC and FPGA. All XADC registers can be accessed from the
FPGA logic using this interface. For more details on the timing for these DRP signals, see Figure 5-3,
page 63.
2. Active-High signal.
3. Rising edge triggered signal.
4. Only available on Zynq-7000 SoC devices.
Table 1-2: XADC Port Descriptions (Cont’d)
Port I/O Description
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Chapter 1: Introduction and Quick Start
XADC Attributes
The block diagram in Figure 1-1 shows the control registers that define the operation of the XADC. The
control registers are a set of 32 16-bit registers. As mentioned, these registers can be read and written
through the DRP or JTAG ports. It is also possible to initialize the contents of these registers during the
configuration of the FPGA. This enables the XADC to start operating in a user-defined mode after
configuration is complete. There are 32 attributes associated with the XADC primitive that allow users to
initialize these registers. Table 1-3 lists these attributes. The attributes are called INIT_xx, where xx
corresponds to the hexadecimal address of the register on the DRP. For example, INIT_40 corresponds to
the first control register at address 40h on the DRP.
The XADC primitive also has an attribute called SIM_MONITOR_FILE that points to the analog stimulus
file. This attribute is required to support simulation. This attribute points to the path and file name of a text
file that contains analog information (for example, temperature and voltage). UNISIM and SIMPRIM
models use this text file during simulation. This is the only way analog signals can be introduced into a
simulation of the XADC. For more information see XADC Software Support, page 69.
Example Instantiation
Instantiating the XADC involves connecting the required I/O (including analog inputs) to the design and
optionally initializing the control registers to define the XADC operation after configuration. Alternatively,
users can write to the control registers through the DRP after device configuration. The timing diagram for
DRP read and write operations is shown in Figure 5-3.
Note: The read/write operation is not valid or complete until the DRDY signal goes active.
This subsection provides a brief example of an XADC instantiation using Verilog. First, the control registers
are initialized, and then the required XADC I/Os are connected to the design. The software correctly ties
off unconnected I/Os on the primitive.
Table 1-3: XADC Primitive Attributes
Attribute Name Control Register
Address Description
INIT_40 Configuration
register 0 40h XADC configuration registers (see Control Registers, page 34).
INIT_41 Configuration
register 1 41h
INIT_42 Configuration
register 2 42h
INIT_43 to
INIT_47 Test registers 43h to 47h
XADC Test registers for factory use
only. The default initialization is
0000h.
INIT_48 to
INIT_4F
Sequence
registers 48h to 4Fh
Sequence registers used to program
the XADC Channel Sequencer
function (see Automatic Channel
Sequencer, page 45).
INIT_50 to
INIT_5F
Alarm limit
registers 50h to 5Fh
Alarm threshold registers for the
XADC alarm function (see
Automatic Alarms, page 55).
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Chapter 1: Introduction and Quick Start
This design assumes an external 50 MHz clock is used for DCLK, and the XADC is configured to monitor
temperature, supply voltages, and activate alarms if safe limits are exceeded. This example is explained in
detail in XADC Software Support, page 69.
XADC #(
// Initializing the XADC Control Registers
.INIT_40(16'h9000),// Calibration coefficient averaging disabled
// averaging of 16 selected for external channels
.INIT_41(16'h2ef0),// Continuous Sequencer Mode, Disable unused ALMs,
// Enable calibration
.INIT_42(16'h0400),// Set DCLK divider to 4, ADC = 500Ksps, DCLK = 50MHz
.INIT_48(16'h4701),// Sequencer channel - enable Temp sensor, VCCINT, VCCAUX,
// VCCBRAM, and calibration
.INIT_49(16'h000f),// Sequencer channel - enable aux analog channels 0 - 3
.INIT_4A(16'h4700),// Averaging enabled for Temp sensor, VCCINT, VCCAUX,
// VCCBRAM
.INIT_4B(16'h0000),// No averaging on external channels
.INIT_4C(16'h0000),// Sequencer Bipolar selection
.INIT_4D(16'h0000),// Sequencer Bipolar selection
.INIT_4E(16'h0000),// Sequencer Acq time selection
.INIT_4F(16'h0000),// Sequencer Acq time selection
.INIT_50(16'hb5ed),// Temp upper alarm trigger 85°C
.INIT_51(16'h5999),// Vccint upper alarm limit 1.05V
.INIT_52(16'hA147),// Vccaux upper alarm limit 1.89V
.INIT_53(16'h0000),// OT upper alarm limit 125°C using automatic shutdown
.INIT_54(16'ha93a),// Temp lower alarm reset 60°C
.INIT_55(16'h5111),// Vccint lower alarm limit 0.95V
.INIT_56(16'h91Eb),// Vccaux lower alarm limit 1.71V
.INIT_57(16'hae4e),// OT lower alarm reset 70°C
.INIT_58(16'h5999),// VCCBRAM upper alarm limit 1.05V
.INIT_5C(16'h5111),// VCCBRAM lower alarm limit 0.95V
.SIM_MONITOR_FILE("sensor_input.txt")
// Analog Stimulus file. Analog input values for simulation
)
XADC_INST ( // Connect up instance IO. See UG480 for port descriptions
.CONVST(GND_BIT), // not used
.CONVSTCLK(GND_BIT), // not used
.DADDR(DADDR_IN[6:0]),
.DCLK(DCLK_IN),
.DEN(DEN_IN),
.DI(DI_IN[15:0]),
.DWE(DWE_IN),
.RESET(RESET_IN),
.VAUXN(aux_channel_n[15:0]),
.VAUXP(aux_channel_p[15:0]),
.ALM(alm_int),
.BUSY(BUSY_OUT),
.CHANNEL(CHANNEL_OUT[4:0]),
.DO(DO_OUT[15:0]),
.DRDY(DRDY_OUT),
.EOC(EOC_OUT),
.EOS(EOS_OUT),
.JTAGBUSY(),// not used
.JTAGLOCKED(),// not used
.JTAGMODIFIED(),// not used
.OT(OT_OUT),
.MUXADDR(),// not used
.VP(VP_IN),
.VN(VN_IN)
);
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Chapter 1: Introduction and Quick Start
ADC and Sensors
More comprehensive information regarding the operation of the ADCs and on-chip sensors can be found
in Chapter 2, Analog-to-Digital Converter. This section provides a brief overview to help users to quickly
interpret data read from the status registers and verify the operation of the XADC.
Analog-to-Digital Converter
The ADCs have a nominal analog input range from 0V to 1V. In unipolar mode (default), the analog inputs
of the ADCs produce a full scale code of FFFh (12 bits) when the input is 1V. Thus, an analog input signal
of 200 mV in unipolar mode produces and outputs code of Equation 1-1.
Equation 1-1
In bipolar mode, the ADCs use two’s complement coding and produces a full scale code of 7FFh with
+0.5V input and 800h with –0.5V input.
Temperature Sensor
The temperature sensor has a transfer function given by Equation 1-2.
Equation 1-2
For example, ADC Code 2423 (977h) = 25°C.
The temperature sensor result can be found in status register 00h.
Power Supply Sensors
The XADC power supply sensors have a transfer function that generates a full scale ADC output code of
FFFh with a 3V input voltage. This voltage is outside the allowed supply range, but the FPGA supply
measurements map into this measurement range. Thus, VCCINT = 1V generates an output code of
1/3 x 4096 = 1365 = 555h. The XADC monitors VCCINT, VCCAUX, and VCCBRAM. The measurement results
are stored in status registers 01h, 02h, and 06h, respectively.
Zynq-7000 SoC
The XADC monitors three additional power supplies on the Zynq-7000 SoC devices. The supplies are
VCCPINT, VCCPAUX, and VCCO_DDR. These measurements are stored in status registers 0Dh, 0Eh, and 0Fh,
respectively.
0.2 1.0FFFh819 or 333h=
Temp C ADC Code 503.975
4096
------------------------------------------------------ 273.15–=
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Chapter 2
Analog-to-Digital Converter
The XADC block contains two 12-bit, 1 MSPS ADCs. These ADCs are available for use with both external
analog inputs and on-chip sensors. Several predefined operating modes are available that cover the most
typical use cases for these ADCs. The various operating modes are covered in Chapter 4, XADC Operating
Modes. This chapter focuses on the detailed operation of the ADC and the on-chip sensors. The various
input configurations for the external analog inputs are also covered. All operating modes of the ADC,
sensors, and analog inputs are configured using the XADC control registers. A detailed description of the
control registers is covered in Chapter 3, XADC Register Interface.
ADC Transfer Functions
The ADCs have transfer functions as shown in Figure 2-2 and Figure 2-3. These transfer functions reflect
unipolar and bipolar operating modes, respectively. All on-chip sensors use the unipolar mode of
operation for the ADC. Users can optionally configure the external analog input channels to operate in
unipolar or bipolar modes (see Analog Inputs, page 20).
For the ADCs to function as specified, the power supplies and reference options must be configured
correctly. The required package ball connections are shown in Figure 1-2. Other important aspects to
ensure optimal ADC performance are the PCB layout and external component selection. These issues are
covered in Chapter 6, Application Guidelines. It is recommended that you read this chapter is before the
board design is started.
Note: The ADCs always produce a 16-bit conversion result. The 12-bit data correspond to the 12 MSBs (most
significant) in the 16-bit status registers. The unreferenced LSBs can be used to minimize quantization effects or
improve resolution through averaging or filtering. See Figure 2-1.
X-Ref Target - Figure 2-1
Figure 2-1: Status Registers
Status Registers
DADDR[6:0] = (00h-07h, 10h-2Fh)
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
NoteDATA[11:0]
X17018-110817
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Chapter 2: Analog-to-Digital Converter
Unipolar Mode
Figure 2-2 shows the 12-bit unipolar transfer function for the ADCs. The nominal analog input range to the
ADCs is 0V to 1V in this mode. The ADC produces a zero code (000h) when 0V is present on the ADC
input and a full scale code of all 1s (FFFh) when 1V is present on the input.
The ADC output coding in unipolar mode is straight binary. The designed code transitions occur at
successive integer LSB values such as one LSB, two LSBs, and three LSBs, etc. The LSB size in volts is equal
to 1V/212 or 1V/4096 = 244 µV. The analog input channels are differential in nature and require both the
positive (VP) and negative (VN) inputs of the differential input to be driven. More details on the analog
inputs and the kinds of inputs signals that can be accommodated are covered in the Analog Inputs section.
X-Ref Target - Figure 2-2
Figure 2-2: Unipolar Transfer Function
Input Voltage (mV)
12-Bit Output Code (Hex)
000
001
003
004
FFF
Output Code Full Scale
Transition
FFE
FFD
002
+0.244 +0.488 +0.732
+999.75
Full Scale Input = 1V1
LSB = 1V / 4096 = 244 μV
X17064-110817
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Chapter 2: Analog-to-Digital Converter
Bipolar Mode
When the external analog input channels of the ADCs are configured as bipolar, they can accommodate
true differential and bipolar analog signal types (see the Analog Inputs section). When dealing with
differential signal types, it is useful to have both sign and magnitude information about the analog input
signal. Figure 2-3 shows the ideal transfer function for bipolar mode operation. The output coding of the
ADC in bipolar mode is two’s complement and is intended to indicate the sign of the input signal on VP
relative to VN. The designed code transitions occur at successive integer LSB values, that is, one LSB,
two LSBs, three LSBs, etc. The LSB size in volts is equal to 1V/212 or 1V/4096 = 244 µV.
X-Ref Target - Figure 2-3
Figure 2-3: Bipolar Transfer Function
Output Code
(Two’s Complement Coding)
Full Scale Input = 1V
1 LSB = 1V / 4096 = 244 μV
800h
801h
000h
001h
002h
7FEh
7FFh
FFFh
FFEh
FFDh
12-Bit Output Code (Hex)
Input Voltage (mV)
-500
0
-0.488
+0.488
+499.75
-0.244
+0.244
X17019-110817
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Chapter 2: Analog-to-Digital Converter
Analog Inputs
The analog inputs of the ADC use a differential sampling scheme to reduce the effects of common-mode
noise signals. This common-mode rejection improves the ADC performance in noisy digital environments.
Figure 2-4 shows the benefits of a differential sampling scheme. Common ground impedances (RG) couple
noise voltages (switching digital currents) into other parts of a system. These noise signals can be 100 mV
or more. For the ADCs, this noise voltage is equivalent to hundreds of LSBs, thus inducing large
measurement errors. The differential sampling scheme samples both the signal and any common mode
noise voltages at both analog inputs (VPand VN). The common mode signal is effectively subtracted
because the Track-and-Hold amplifier captures the difference between VPand VNor VPminus VN. To take
advantage of the high common mode rejection, users need only connect VPand VNin a differential
configuration.
X-Ref Target - Figure 2-4
Figure 2-4: Common Mode Noise Rejection
Noise
Current T/H
VP
VN
Note 1: RGis Common Ground Impedance.
RG
(1)
Differential
Sampling
Common Mode
Rejection removes
noise
0V
1V
VP
VN
0V
1V VP– VN
Common Noise
on VPand VN
+
–
Noise
Voltage
X17020-110817
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