AMD XILINX 7 Series User manual

7 Series FPGAs and
Zynq-7000 SoC XADC Dual
12-Bit 1 MSPS
Analog-to-Digital Converter
User Guide
UG480 (v1.11) June 13, 2022
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Table of Contents
Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1: Introduction and Quick Start
XADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
XADC Pinout Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Instantiating the XADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: Analog-to-Digital Converter
ADC Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: XADC Register Interface
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DRP JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Zynq-7000 SoC Processing System (PS) to XADC Dedicated Interface . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 4: XADC Operating Modes
Single Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Automatic Channel Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Sequencer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Multiplexer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Maximum and Minimum Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Automatic Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5: XADC Timing
Continuous Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Event-Driven Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dynamic Reconfiguration Port (DRP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 6: Application Guidelines
Reference Inputs (VREFP and VREFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Analog Power Supply and Ground (VCCADC and GNDADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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External Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PC Board Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendix 7: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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Preface
About This Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a
common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family
is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is
optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high volume
applications. The Kintex®-7 family is an innovative class of FPGAs optimized for the best
price-performance. The Virtex®-7 family is optimized for highest system performance and capacity. The
Zynq®-7000 SoC device integrates a feature-rich dual-core Arm® Cortex™-A9 based processing system
(PS) and 28 nm Xilinx programmable logic (PL) in a single device.
This guide serves as a technical reference describing the 7 series FPGAs and Zynq-7000 SoC XADC, a dual
12-bit, 1 MSPS analog-to-digital converter with on-chip sensors. This user guide is part of an overall set of
documentation on the 7 series FPGAs and Zynq-7000 SoC devices, which is available on the Xilinx website
at
www.xilinx.com/documentation.
Guide Contents
This manual contains these chapters:
•Chapter 1, Introduction and Quick Start
•Chapter 2, Analog-to-Digital Converter
•Chapter 3, XADC Register Interface
•Chapter 4, XADC Operating Modes
•Chapter 5, XADC Timing
•Chapter 6, Application Guidelines
•Appendix 7, Additional Resources and Legal Notices
Example design files and Tcl console examples for the Vivado® Hardware Manager can be found in the ZIP
file that accompanies this user guide.
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Chapter 1
Introduction and Quick Start
This chapter provides a brief overview of the Xilinx 7 series FPGAs XADC functionality. The XADC is
available in all Artix®-7, Kintex®-7, Virtex®-7, and Zynq®-7000 SoC devices. The XADC is also available
in many, but not all Spartan®-7 devices. To identify specific devices that support the XADC block, consult
the Spartan-7 family overview in DS180, 7 Series FPGAs Overview [Ref 11].
The XADC is the basic building block that enables analog mixed signal (AMS) functionality which is new
to 7 series FPGAs. By combining high quality analog blocks with the flexibility of programmable logic, it is
possible to craft customized analog interfaces for a wide range of applications. See www.xilinx.com/ams
for more information.
This chapter contains only key information to allow a basic understanding of the XADC block. With this
introduction, you can learn the pinout requirements and determine how to instantiate basic functionality
in their designs. Subsequent chapters provide more detailed descriptions of the XADC functionality.
XADC Overview
The XADC includes a dual 12-bit, 1 Mega sample per second (MSPS) ADC and on-chip sensors. The ADCs
and sensors are fully tested and specified (see the respective 7 series FPGAs data sheet). The ADCs provide
a general-purpose, high-precision analog interface for a range of applications. Figure 1-1 shows a block
diagram of the XADC. The dual ADCs support a range of operating modes, for example, externally
triggered and simultaneous sampling on both ADCs (see Chapter 4, XADC Operating Modes) and various
analog input signal types, for example, unipolar and differential (see Chapter 2, Analog-to-Digital
Converter). The ADCs can access up to 17 external analog input channels.
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Chapter 1: Introduction and Quick Start
Notes relevant to Figure 1-1:
1. Zynq-7000 SoC devices only.
The XADC also includes several on-chip sensors that support measurement of the on-chip power supply
voltages and die temperature. The ADC conversion data is stored in dedicated registers called status
registers. These registers are accessible through the FPGA interconnect using a 16-bit synchronous read
and write port called the dynamic reconfiguration port (DRP). ADC conversion data is also accessible
through the JTAG TAP, either before (pre-configuration) or after configuration. For JTAG TAP, users are not
required to instantiate the XADC because it is a dedicated interface that uses the existing FPGA JTAG
infrastructure. As discussed later, if the XADC is not instantiated in a design, the device operates in a
predefined mode (called default mode) that monitors on-chip temperature and supply voltages.
XADC operation is user defined by writing to the control registers using either the DRP or JTAG interface.
It is also possible to initialize these register contents when the XADC is instantiated in a design using the
block attributes.
Differences between Virtex-5 and Virtex-6 System Monitors
For Virtex-5 and Virtex-6 FPGA System Monitor users, the XADC functionality is fully backward
compatible with legacy System Monitor designs. The XADC functionality and interface are familiar to
those who have previously designed with the System Monitor. System Monitor designs are automatically
retargeted to the XADC site by the software tools.
However, the XADC block in 7 series FPGAs contains a large number of new features and enhancements
detailed in subsequent chapters. The new functionality is enabled by initializing previously undefined
status registers and bit locations. Old System Monitor designs that did not initialize these new registers or
bit locations behave exactly the same way as before.
X-Ref Target - Figure 1-1
Figure 1-1: XADC Block Diagram
Mux
VP_0
VREP_0
Die
Temperature
VCCINT
VCCAUX
VCCBRAM
VCCPINT(1)
VCCPAUX(1)
VCCO_DDR(1)
VREFN_0
Mux
Temperature
Sensor
Supply
Sensors
VN_0
VAUXP[0]
VAUXN[0]
12-bit,
1 MSPS
ADC A
°C
VAUXP[12]
VAUXN[12]
VAUXP[13]
VAUXN[13]
VAUXP[14]
VAUXN[14]
VAUXP[15]
VAUXN[15]
12-bit,
1 MSPS
ADC B
64 x 16 bits
Read/Write
64 x 16 bits
Read Only
Control
Registers
Status
Registers
On-Chip Ref
1.25V
JTAG FPGA
Interconnect
External
Analog
Inputs
DRP
X17015-110817
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Chapter 1: Introduction and Quick Start
XADC Pinout Requirements
Dedicated Package Pins
All XADC dedicated pins are located in bank 0 and thus have the _0 suffix in the package file names.
Figure 1-2 shows the basic pinout requirements for the XADC. There are two recommended
configurations. On the left, the XADC is powered from VCCAUX (1.8V) and uses an external 1.25V reference
source. The external reference delivers the best performance in terms of accuracy and thermal drift. A
ferrite bead is used to isolate the ground reference for the analog circuits and system ground. An additional
low-pass filter for VCCAUX supply will similarly improve the ADC performance. See Chapter 6,
Application Guidelines for more information. Shared or common ground impedance is the most common
way to introduce unwanted noise into analog circuits.
It is also possible to use an on-chip reference for the ADCs. To enable the on-chip reference source, the
VREFP pin must be connected to ground as shown on the right of Figure 1-2. Where only basic on-chip
thermal and supply monitoring is required, using the on-chip reference provides good performance. Users
should consult the respective data sheet to see the accuracy specifications when using the external and
on-chip reference sources. Table 1-1 lists the pins associated with the XADC and the recommended
connectivity.
Note: It is also important to place the 100 nF decoupling capacitors as close as possible to the package balls to
minimize inductance between the decoupling and package balls.
X-Ref Target - Figure 1-2
Figure 1-2: XADC Pinout Requirements
ADC
Filter VCCAUX Supply
GNDADC
VREFN
10 μF
1.25V + 0.2%
50 ppm/°C 100 nF
VN
VP
100 nF 470 nF
VREFP VCCADC
1.8V – 5V
ADC
Filter VCCAUX Supply
GNDADC
VREFN
VN
VP
100 nF 470 nF
VREFP VCCADC
Ferrite bead for high frequency
noise isolation GND GND
Ferrite bead for high frequency
noise isolation
Package Pins
Use External Reference IC Enable On-Chip Reference
VCCAUX (1.8V ± 5%)
VCCAUX (1.8V ± 5%)
X17016-072318
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Chapter 1: Introduction and Quick Start
Table 1-1: XADC Package Pins
Package Pin Type Description
VCCADC_0 Power supply
This is the analog supply pin for the ADCs and other analog circuits in the
XADC. It can be tied to the 1.8V VCCAUX supply; however, in a mixed-signal
system, the supply should be connected to a separate 1.8V analog, if available.
See Analog Power Supply and Ground (VCCADC and GNDADC), page 64 for more
information. This pin should never be tied to GND. The pin should be tied to
VCCAUX even if the XADC is not being used.
GNDADC_0 Power supply
This is the ground reference pin for the ADCs and other analog circuits in the
XADC. It can be tied to the system ground through an isolating ferrite bead as
shown in Figure 1-2. In a mixed-signal system this pin should be tied to an
analog ground plane if available, in which case the ferrite bean is not required.
See Analog Power Supply and Ground (VCCADC and GNDADC), page 64 for more
information. This pin should always be tied to GND even if the XADC is not
being used.
VREFP_0 Reference voltage
input
This pin can be tied to an external 1.25V accurate reference IC (±0.2% or
±9 LSBs at 12 bits) for best performance of the ADCs. It should be treated as an
analog signal that together with the VREFN signal provides a differential 1.25V
voltage. By connecting this pin to GNDADC (see Figure 1-2), an on-chip
reference source (±1% or ±41 LSBs at 12 bits) is activated. This pin should
always be connected to GNDADC if an external reference is not supplied. See
Reference Inputs (VREFP and VREFN), page 64 for more information.
VREFN_0 Reference voltage
input
This pin should be tied to the GND pin of an external 1.25V accurate reference
IC (±0.2%) for best performance of the ADCs. It should be treated as an analog
signal that together with the VREFP signal provides a differential 1.25V
voltage. This pin should always be connected to GND even if an external
reference is not supplied. See Reference Inputs (VREFP and VREFN), page 64 for
more information.
VP_0 Dedicated analog
input
This is the positive input terminal of the dedicated differential analog input
channel (VP/VN). The analog input channels are very flexible and support
multiple analog input signal types. For more information, see Analog Inputs,
page 20. This pin should be connected to GND if not used.
VN_0 Dedicated analog
input
This is the negative input terminal of the dedicated differential analog input
channel (VP/VN). The analog input channels are very flexible and support
multiple analog input signal types. For more information, see Analog Inputs,
page 20. This pin should be connected to GND if not used.
_AD0P_ to
_AD15P_(1)(2)
Auxiliary analog
inputs/digital
I/O
These are multi-function pins that can support analog inputs or can be used as
regular digital I/O (see Figure 1-1). These pins support up to 16 positive input
terminals of the differential auxiliary analog input channels (VAUXP/VAUXN).
The analog input channels are very flexible and support multiple analog input
signal types. For more information, see Analog Inputs, page 20. When not
being used as analog inputs, these pins can be treated like any other digital
I/O.
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Chapter 1: Introduction and Quick Start
Note: Chapter 6, Application Guidelines, should be consulted before commencing any PC board layout. Board layout
and external component choices can greatly impact the performance of the ADCs.
External Analog Inputs
Apart from a single dedicated analog input pair (VP/VN), the external analog inputs use dual-purpose
I/O. These FPGA digital I/Os are individually nominated as analog inputs when the XADC is instantiated
in a design. This document refers to these analog inputs as auxiliary analog inputs. A maximum of 16
auxiliary analog inputs are available. The auxiliary analog inputs are enabled by connecting the analog
inputs on the XADC primitive to the top level of the design. When enabled as analog inputs, these package
balls are unavailable as digital I/Os. It is also possible to enable the auxiliary analog inputs
preconfiguration (for example, for PCB diagnostics) through the JTAG TAP (see JTAG DRP Commands for
more information.)
All analog input channels are differential and require two package balls. Typically, the auxiliary analog
inputs are allocated evenly over banks 15 and 35. However, users should consult the pinout information in
UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide [Ref 2] for a particular device
and package combination. Analog-capable I/O have the ADxP or ADxN suffix on the I/O name in the
package files. For example, auxiliary analog input channel 8 has associated package ball names ending
with AD8P and AD8N. See UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide
[Ref 2] for more information. The auxiliary analog inputs have a fixed package ball assignment and cannot
be moved.
Auxiliary analog inputs are supported differently in Vivado® tools when compared to ISE tools. The
auxiliary analog inputs do not require any user-specified constraints or pin locations in ISE tools. ISE
external auxiliary inputs do not need an I/O standard setting to be added to your constraints file (UCF) or
in the PlanAhead™ design tool. In Vivado design tools, the auxiliary analog inputs must be assigned to the
associated pin location.
_AD0N_ to
_AD15N_(1)(2)
Auxiliary analog
inputs/digital
I/O
These are multi-function pins that can support analog inputs or can be used
as regular digital I/O (see Figure 1-1). These pins support up to 16 negative
input terminals of the differential auxiliary analog input channels
(VAUXP/VAUXN). The analog input channels are very flexible and support
multiple analog input signal types. For more information, see Analog Inputs,
page 20. When not being used as analog inputs, these pins can be treated like
any other digital I/O.
Notes:
1. FPGA I/Os that are analog input-enabled contain the _ADxP_ and _ADxN_ designation in the package file name, for example,
IO_L1P_T0_AD0P_35 is the input pin for analog auxiliary channel VAUXP[0]. IO_L1N_T0_AD0N_35 is the input pin for analog
auxiliary channel VAUXN[0]. For more information, see UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide
[Ref 2].
2. Auxiliary channels 6, 7, 13, 14, and 15 are not supported in Kintex-7 devices. Some auxiliary analog channels might also not be
supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. You should consult the package file for
the device.
Table 1-1: XADC Package Pins (Cont’d)
Package Pin Type Description
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