Analog Devices AD9776 User manual

Dual, 12-/14-/16-Bit,
1.0 GSPS D/A Converter
AD9776/AD9778/AD9779
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
DAC output sample rate: 1 GSPS
1.8 V/3.3 V single supply operation
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
CMOS data input interface with adjustable setup and hold
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications systems
point-to-point wireless, LMDS
Multicarrier WCDMA
Multicarrier GSM
GENERAL DESCRIPTION
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range DACs that provide a sample rate of 1 GSPS, thus
permitting multicarrier generation up to its Nyquist frequency.
They include features optimized for direct conversion transmit
applications, including complex digital modulation, and gain
and offset compensation. The DAC outputs are optimized to
interface seamlessly with analog quadrature modulators such as
the AD8349. A serial peripheral interface (SPI) provides for
programming/readback of many internal parameters. The
output current can be programmed over a range of 10 mA to
30 mA. The devices are manufactured on an advanced 0.18 m
CMOS process and operate from 1.8 V and 3.3 V supplies for
a total power consumption of 1.0 W. They are enclosed in
100-lead TQFP packages.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs can be easily configured for various
single-ended or differential circuit topologies.

AD9776/AD9778/AD9779
Rev. 0 | Page 2 of 56
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
Serial Peripheral Interface......................................................... 23
MSB/LSB Transfers..................................................................... 24
SPI Register Map............................................................................. 25
Interpolation Filter Architecture .................................................. 29
Interpolation Filter Minimum and Maximum Bandwidth
Specifications .............................................................................. 33
Driving the DACCLK Input ..................................................... 33
Full-Scale Current Generation ................................................. 36
Power Dissipation....................................................................... 37
Power-Down and Sleep Modes................................................. 38
Interleaved Data Mode .............................................................. 39
Timing Information................................................................... 39
Evaluation Board Operation ......................................................... 45
Modifying the Evaluation Board to Use the AD8349 On-
Board Quadrature Modulator................................................... 47
Evaluation Board Schematics ................................................... 48
Outline Dimensions....................................................................... 55
Ordering Guide .......................................................................... 55
REVISION HISTORY
7/05—Revision 0: Initial Version

AD9776/AD9778/AD9779
Rev. 0 | Page 3 of 56
FUNCTIONAL BLOCK DIAGRAM
10
10
10
10
CLOCK GENERATION/DISTRIBUTION
DATA
ASSEMBLER
DIGITAL CONTROLLER
2×2×
SYNC
1
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
IDAC
CLK+
CLK–
IOUT1_P
IOUT1_N
AUX1_P
AUX1_N
AUX2_P
AUX2_N
IOUT2_P
IOUT2_N
VREF
RSET
GAIN
GAIN
GAIN
GAIN
16-BIT
QDAC
2×
SYNC
1
I LATCH
DELAY LINE
Q LATCH
P2D(15:0)
P1D(15:0)
SYNC_O
SYNC_I
DATACLK_OUT
2×2×2×
n× f
DAC
/8
n = 1 TO 7
POWER-ON
RESET
SDO
SDIO
SCLK
CSB
REFERENCE
AND BIAS
SERIAL
PERIPHERAL
INTERFACE
COMPLEX
MODULATOR
DELAY LINE
05361-001
Figure 1.

AD9776/AD9778/AD9779
Rev. 0 | Page 4 of 56
SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 1. AD9776, AD9778, and AD9779 DC Specifications
AD9776 AD9778 AD9779
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 14 16 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.1 ±0.65 ±2.1 LSB
Integral Nonlinearity (INL) ±0.6 ±1 ±3.7 LSB
MAIN DAC OUTPUTS
Offset Error –0.001 0 +0.001 –0.001 0 +0.001 –0.001 0 +0.001 % FSR
Gain Error (with Internal
Reference) ±2 ±2 ±2 % FSR
Full-Scale Output Current18.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA
Output Compliance Range –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 V
Output Resistance 10 10 10 MΩ
Gain DAC Monotonicity
Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset 0.04 0.04 0.04 ppm/°C
Gain 100 100 100 ppm/°C
Reference Voltage 30 30 30 ppm/°C
AUX DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current1–1.998 +1.998 –1.998 +1.998 –1.998 +1.998 mA
Output Compliance Range
(Source) 0 1.6 0 1.6 0 1.6 V
Output Compliance Range
(Sink) 0.8 1.6 0.8 1.6 0.8 1.6 V
Output Resistance 1 1 1 MΩ
Aux DAC Monotonicity
Guaranteed
REFERENCE
Internal Reference Voltage 1.2 1.2 1.2 V
Output Resistance 5 5 5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
POWER CONSUMPTION
1× Mode, fDAC = 100 MSPS,
IF = 1 MHz 250 300 250 300 250 300 mW
2× Mode, fDAC = 320 MSPS,
IF = 16 MHz, PLL Off 498 498 498 mW
2× Mode, fDAC = 320 MSPS,
IF = 16 MHz, PLL On 588 588 588 mW
4× Mode, fDAC/4 Mod,
fDAC = 500 MSPS,
IF = 137.5 MHz, Q DAC Off
572 572 572 mW

AD9776/AD9778/AD9779
Rev. 0 | Page 5 of 56
AD9776 AD9778 AD9779
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
8× Mode, fDAC/4 Mod,
fDAC = 1 GSPS, IF = 262.5 MHz 980 980 980 mW
Power-Down Mode 2 3.7 2 3.7 2 3.7 mW
Power Supply Rejection Ratio—
AVDD33 –0.3 +0.3 –0.3 +0.3 –0.3 +0.3 % FSR/V
OPERATING RANGE –40 +25 +85 –40 +25 +85 –40 +25 +85 °C
1Based on a 10 k external resistor.
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter Min Typ Max Unit
LVDS RECEIVER INPUTS
(SYNC_I+, SYNC_I–), SYNC_I+ = VIA, SYNC_I– = VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH –100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN180 120 Ω
LVDS Input Rate 125 MSPS
Set-Up Time, Sync_I to DAC Clock –0.2 ns
Hold Time, Sync_I to DAC Clock 1 ns
LVDS DRIVER OUTPUTS
(SYNC_O+, SYNC_O–), SYNC_O+ = VOA, SYNC_O– = VOB, 100 Ω Termination
Output Voltage High, VOA or VOB 825 1575 mV
Output Voltage Low, VOA or VOB 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, Single-Ended, RO80 100 120 Ω
Maximum Clock Rate 1 GHz
DAC CLOCK INPUT (CLK+, CLK–)
Peak-to-Peak Voltage at CLK+ and CLK–2400 800 1600 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate31 GSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
INPUT DATA
Set-Up Time, Input Data To DATACLK (All Modes) 3.0 ns
Hold Time, Input Data To DATACLK (All Modes) –0.78 ns
1Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C.
2When using the PLL, a minimum 1 V swing is recommended.
3Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.

AD9776/AD9778/AD9779
Rev. 0 | Page 6 of 56
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3. AD9776, AD9778, and AD9779 AC Specifications
AD9776 AD9778 AD9779
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 100 MSPS, fOUT = 20 MHz 82 82 82 dBc
fDAC = 200 MSPS, fOUT = 50 MHz 81 81 82 dBc
fDAC = 400 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 800 MSPS, fOUT = 70 MHz 85 85 87 dBc
TWO-TONE INTERMODULATION DISTORTION
(IMD)
fDAC = 200 MSPS, fOUT = 50 MHz 87 87 91 dBc
fDAC = 400 MSPS, fOUT = 60 MHz 80 85 85 dBc
fDAC = 400 MSPS, fOUT = 80 MHz 75 81 81 dBc
fDAC = 800 MSPS, fOUT = 100 MHz 75 80 81 dBc
NOISE SPECTRAL DENSITY (NSD) Eight-Tone,
500 kHz Tone Spacing
fDAC = 200 MSPS, fOUT = 80 MHz –152 –155 –158 dBm/Hz
fDAC = 400 MSPS, fOUT = 80 MHz –155 –159 –160 dBm/Hz
fDAC = 800 MSPS, fOUT = 80 MHz –157.5 –160 –161 dBm/Hz
WCDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz 76 78 79 dBc
fDAC = 491.52 MSPS, fOUT = 200 MHz 69 73 74 dBc
WCDMA SECOND ADJACENT CHANNEL
LEAKAGE RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz 77.5 80 81 dBc
fDAC = 491.52 MSPS, fOUT = 200 MHz 76 78 78 dBc

AD9776/AD9778/AD9779
Rev. 0 | Page 7 of 56
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
With
Respect
to Rating
AVDD33 AGND
DGND
CGND
−0.3 V to +3.6 V
DVDD33, DVDD18, CVDD18 AGND
DGND
CGND
−0.3 V to +1.98 V
AGND DGND
CGND −0.3 V to +0.3 V
DGND AGND
CGND −0.3 V to +0.3 V
CGND AGND
DGND −0.3 V to +0.3 V
I120, VREF, IPTAT AGND −0.3V to AVDD33 + 0.3 V
IOUT1-P, IOUT1-N, IOUT2-P,
IOUT2-N, Aux1-P, Aux1-N, Aux2-P,
Aux2-N
AGND −1.0 V to AVDD33 + 0.3 V
P1D15 to P1D0,
P2D15 to P2D0 DGND −0.3 V toDVDD33 + 0.3 V
DATACLK, TXENABLE DGND −0.3 VtoDVDD33+ 0.3V
CLK+, CLK−, RESET, IRQ,
PLL_LOCK, SYNC_O+,
SYNC_O−, SYNC_I+, SYNC_I–
CGND −0.3 V to CVDD18 + 0.3 V
RESET, IRQ, PLL_LOCK,
SYNC_O+, SYNC_O–,
SYNC_I+, SYNC_I–, CSB,
SCLK, SDIO, SDO
DGND –0.3 V to DVDD33 + 0.3 V
Junction Temperature +125°C
Storage Temperature −65°C to +150°C
Thermal Resistance
100-lead, thermally enhanced TQFP Package θJA = 27.4°C/W
(with no airflow movement).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD9776/AD9778/AD9779
Rev. 0 | Page 8 of 56
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
NC
58
NC
57
NC
56
NC
55
P2D<0>
54
DGND
53
DVDD18
52
P2D<1>
51
P2D<2>
65
PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<4>
27
P1D<3>
28
P1D<2>
29
P1D<1>
30
P1D<0>
31
NC
32
DGND
33
DVDD18
34
NC
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<11>
41
P2D<10>
42
P2D<9>
43
DVDD18
44
DGND
45
P2D<8>
46
P2D<7>
47
P2D<6>
48
P2D<5>
49
P2D<4>
50
P2D<3>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
CLK–
5
CLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<11>
18
P1D<10>
19
P1D<9>
20
P1D<8>
21
P1D<7>
22
DGND
23
DVDD18
24
P1D<6>
25
P1D<5>
11
CGND
AD9776
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
05361-004
Figure 2. AD9776 Pin Configuration
Table 5. AD 9776 Pin Function Description
Pin No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply
2 CVDD18 1.8 V Clock Supply
3 CGND Clock Common
4 CGND Clock Common
5 CLK+1Differential Clock Input
6 CLK–1Differential Clock Input
7 CGND Clock Common
8 CGND Clock Common
9 CVDD18 1.8 V Clock Supply
10 CVDD18 1.8 V Clock Supply
11 CGND Clock Common
12 AGND Analog Common
13 SYNC_I+ Differential Synchronization Input
14 SYNC_I– Differential Synchronization Input
15 DGND Digital Common
16 DVDD18 1.8 V Digital Supply
17 P1D <11> Port 1, Data Input D11 (MSB)
18 P1D <10> Port 1, Data Input D10
Pin No. Mnemonic Description
19 P1D <9> Port 1, Data Input D9
20 P1D <8> Port 1, Data Input D8
21 P1D <7> Port 1, Data Input D7
22 DGND Digital Common
23 DVDD18 1.8 V Digital Supply
24 P1D <6> Port 1, Data Input D6
25 P1D <5> Port 1, Data Input D5
26 P1D <4> Port 1, Data Input D4
27 P1D <3> Port 1, Data Input D3
28 P1D <2> Port 1, Data Input D2
29 P1D <1> Port 1, Data Input D1
30 P1D <0> Port 1, Data Input D0
31 NC No Connect
32 DGND Digital Common
33 DVDD18 1.8 V Digital Supply
34 NC No Connect
35 NC No Connect
36 NC No Connect

AD9776/AD9778/AD9779
Rev. 0 | Page 9 of 56
Pin No. Mnemonic Description
37 DATACLK Data Clock Output
38 DVDD33 3.3 V Digital Supply
39 TXENABLE Transmit Enable
40 P2D <11> Port 2, Data Input D11 (MSB)
41 P2D <10> Port 2, Data Input D10
42 P2D <9> Port 2, Data Input D9
43 DVDD18 1.8 V Digital Supply
44 DGND Digital Common
45 P2D <8> Port 2, Data Input D8
46 P2D <7> Port 2, Data Input D7
47 P2D <6> Port 2, Data Input D6
48 P2D <5> Port 2, Data Input D5
49 P2D <4> Port 2, Data Input D4
50 P2D <3> Port 2, Data Input D3
51 P2D <2> Port 2, Data Input D2
52 P2D <1> Port 2, Data Input D1
53 DVDD18 1.8 V Digital Supply
54 DGND Digital Common
55 P2D <0> Port 2, Data Input D0
56 NC No Connect
57 NC No Connect
58 NC No Connect
59 NC No Connect
60 DVDD18 1.8 V Digital Supply
61 DVDD33 3.3 V Digital Supply
62 SYNC_O– Differential Synchronization Output
63 SYNC_O+ Differential Synchronization Output
64 DGND Digital Common
65 PLL_LOCK PLL Lock Indicator
66 SDO SPI Port Data Output
67 SDIO SPI Port Data Input/Output
68 SCLK SPI Port Clock
69 CSB SPI Port Chip Select Bar
70 RESET Reset, Active High
71 IRQ Interrupt Request
72 AGND Analog Common
73 IPTAT Reference Current
Pin No. Mnemonic Description
74 VREF Voltage Reference Output
75 I120 120 μA Reference Current
76 AVDD33 3.3 V Analog Supply
77 AGND Analog Common
78 AVDD33 3.3 V Analog Supply
79 AGND Analog Common
80 AVDD33 3.3 V Analog Supply
81 AGND Analog Common
82 AGND Analog Common
83 OUT2_P Differential DAC Current Output,
Channel 2
84 OUT2_N Differential DAC Current Output,
Channel 2
85 AGND Analog Common
86 AUX2_P Auxiliary DAC Voltage Output,
Channel 2
87 AUX2_N Auxiliary DAC Voltage Output,
Channel 2
88 AGND Analog Common
89 AUX1_N Auxiliary DAC Voltage Output,
Channel 1
90 AUX1_P Auxiliary DAC Voltage Output,
Channel 1
91 AGND Analog Common
92 OUT1_N Differential DAC Current Output,
Channel 1
93 OUT1_P Differential DAC Current Output,
Channel 1
94 AGND Analog Common
95 AGND Analog Common
96 AVDD33 3.3 V Analog Supply
97 AGND Analog Common
98 AVDD33 3.3 V Analog Supply
99 AGND Analog Common
100 AVDD33 3.3 V Analog Supply
1The combined differential clock input at the CLK+ and CLK– pins are referred
to as DACCLK.

AD9776/AD9778/AD9779
Rev. 0 | Page 10 of 56
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
NC
58
NC
57
P2D<0>
56
P2D<1>
55
P2D<2>
54
DGND
53
DVDD18
52
P2D<3>
51
P2D<4>
65
PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<6>
27
P1D<5>
28
P1D<4>
29
P1D<3>
30
P1D<2>
31
P1D<1>
32
DGND
33
DVDD18
34
P1D<0>
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<13>
41
P2D<12>
42
P2D<11>
43
DVDD18
44
DGND
45
P2D<10>
46
P2D<9>
47
P2D<8>
48
P2D<7>
49
P2D<6>
50
P2D<5>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
CLK–
5
CLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<13>
18
P1D<12>
19
P1D<11>
20
P1D<10>
21
P1D<9>
22
DGND
23
DVDD18
24
P1D<8>
25
P1D<7>
11
CGND
AD9778
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
05361-003
Figure 3. AD9778 Pin Configuration
Table 6. AD 9778 Pin Function Description
Pin No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply
2 CVDD18 1.8 V Clock Supply
3 CGND Clock Common
4 CGND Clock Common
5 CLK+1Differential Clock Input
6 CLK–1Differential Clock Input
7 CGND Clock Common
8 CGND Clock Common
9 CVDD18 1.8 V Clock Supply
10 CVDD18 1.8 V Clock Supply
11 CGND Clock Common
12 AGND Analog Common
13 SYNC_I+ Differential Synchronization Input
14 SYNC_I– Differential Synchronization Input
15 DGND Digital Common
16 DVDD18 1.8 V Digital Supply
17 P1D <13> Port 1, Data Input D13 (MSB)
18 P1D <12> Port 1, Data Input D12
19 P1D <11> Port 1, Data Input D11
20 P1D <10> Port 1, Data Input D10
Pin No. Mnemonic Description
21 P1D <9> Port 1, Data Input D9
22 DGND Digital Common
23 DVDD18 1.8 V Digital Supply
24 P1D <8> Port 1, Data Input D8
25 P1D <7> Port 1, Data Input D7
26 P1D <6> Port 1, Data Input D6
27 P1D <5> Port 1, Data Input D5
28 P1D <4> Port 1, Data Input D4
29 P1D <3> Port 1, Data Input D3
30 P1D <2> Port 1, Data Input D2
31 P1D <1> Port 1, Data Input D1
32 DGND Digital Common
33 DVDD18 1.8 V Digital Supply
34 P1D <0> Port 1, Data Input D0
35 NC No Connect
36 NC No Connect
37 DATACLK Data Clock Output
38 DVDD33 3.3 V Digital Supply
39 TXENABLE Transmit Enable
40 P2D <13> Port 2, Data Input D13 (MSB)

AD9776/AD9778/AD9779
Rev. 0 | Page 11 of 56
Pin No. Mnemonic Description
41 P2D <12> Port 2, Data Input D12
42 P2D <11> Port 2, Data Input D11
43 DVDD18 1.8 V Digital Supply
44 DGND Digital Common
45 P2D <10> Port 2, Data Input D10
46 P2D <9> Port 2, Data Input D9
47 P2D <8> Port 2, Data Input D8
48 P2D <7> Port 2, Data Input D7
49 P2D <6> Port 2, Data Input D6
50 P2D <5> Port 2, Data Input D5
51 P2D <4> Port 2, Data Input D4
52 P2D <3> Port 2, Data Input D3
53 DVDD18 1.8 V Digital Supply
54 DGND Digital Common
55 P2D <2> Port 2, Data Input D2
56 P2D <1> Port 2, Data Input D1
57 P2D <0> Port 2, Data Input D0
58 NC No Connect
59 NC No Connect
60 DVDD18 1.8 V Digital Supply
61 DVDD33 3.3 V Digital Supply
62 SYNC_O– Differential Synchronization Output
63 SYNC_O+ Differential Synchronization Output
64 DGND Digital Common
65 PLL_LOCK PLL Lock Indicator
66 SDO SPI Port Data Output
67 SDIO SPI Port Data Input/Output
68 SCLK SPI Port Clock
69 CSB SPI Port Chip Select Bar
70 RESET Reset, Active High
71 IRQ Interrupt Request
72 AGND Analog Common
73 IPTAT Reference Current
74 VREF Voltage Reference Output
75 I120 120 μA Reference Current
Pin No. Mnemonic Description
76 AVDD33 3.3 V Analog Supply
77 AGND Analog Common
78 AVDD33 3.3 V Analog Supply
79 AGND Analog Common
80 AVDD33 3.3 V Analog Supply
81 AGND Analog Common
82 AGND Analog Common
83 OUT2_P Differential DAC Current Output,
Channel 2
84 OUT2_N Differential DAC Current Output,
Channel 2
85 AGND Analog Common
86 AUX2_P Auxiliary DAC Voltage Output,
Channel 2
87 AUX2_N Auxiliary DAC Voltage Output,
Channel 2
88 AGND Analog Common
89 AUX1_N Auxiliary DAC Voltage Output,
Channel 1
90 AUX1_P Auxiliary DAC Voltage Output,
Channel 1
91 AGND Analog Common
92 OUT1_N Differential DAC Current Output,
Channel 1
93 OUT1_P Differential DAC Current Output,
Channel 1
94 AGND Analog Common
95 AGND Analog Common
96 AVDD33 3.3 V Analog Supply
97 AGND Analog Common
98 AVDD33 3.3 V Analog Supply
99 AGND Analog Common
100 AVDD33 3.3 V Analog Supply
1The combined differential clock input at the CLK+ and CLK– pins are referred
to as DACCLK.

AD9776/AD9778/AD9779
Rev. 0 | Page 12 of 56
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
NC
58
NC
57
NC
56
NC
55
P2D<0>
54
DGND
53
DVDD18
52
P2D<1>
51
P2D<2>
65
PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<4>
27
P1D<3>
28
P1D<2>
29
P1D<1>
30
P1D<0>
31
NC
32
DGND
33
DVDD18
34
NC
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<11>
41
P2D<10>
42
P2D<9>
43
DVDD18
44
DGND
45
P2D<8>
46
P2D<7>
47
P2D<6>
48
P2D<5>
49
P2D<4>
50
P2D<3>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
CLK–
5
CLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<11>
18
P1D<10>
19
P1D<9>
20
P1D<8>
21
P1D<7>
22
DGND
23
DVDD18
24
P1D<6>
25
P1D<5>
11
CGND
AD9776
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
05361-004
Figure 4. AD9779 Pin Configuration
Table 7. AD9779 Pin Function Descriptions
Pin No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply
2 CVDD18 1.8 V Clock Supply
3 CGND Clock Common
4 CGND Clock Common
5 CLK+1Differential Clock Input
6 CLK–1Differential Clock Input
7 CGND Clock Common
8 CGND Clock Common
9 CVDD18 1.8 V Clock Supply
10 CVDD18 1.8 V Clock Supply
11 CGND Clock Common
12 AGND Analog Common
13 SYNC_I+ Differential Synchronization Input
14 SYNC_I– Differential Synchronization Input
15 DGND Digital Common
16 DVDD18 1.8 V Digital Supply
17 P1D <15> Port 1, Data Input D15 (MSB)
18 P1D <14> Port 1, Data Input D14
19 P1D <13> Port 1, Data Input D13
Pin No. Mnemonic Description
20 P1D <12> Port 1, Data Input D12
21 P1D <11> Port 1, Data Input D11
22 DGND Digital Common
23 DVDD18 1.8 V Digital Supply
24 P1D <10> Port 1, Data Input D10
25 P1D <9> Port 1, Data Input D9
26 P1D <8> Port 1, Data Input D8
27 P1D <7> Port 1, Data Input D7
28 P1D <6> Port 1, Data Input D6
29 P1D <5> Port 1, Data Input D5
30 P1D <4> Port 1, Data Input D4
31 P1D <3> Port 1, Data Input D3
32 DGND Digital Common
33 DVDD18 1.8 V Digital Supply
34 P1D <2> Port 1, Data Input D2
35 P1D <1> Port 1, Data Input D1
36 P1D <0> Port 1, Data Input D0 (LSB)
37 DATACLK Data Clock Output
38 DVDD33 3.3 V Digital Supply

AD9776/AD9778/AD9779
Rev. 0 | Page 13 of 56
Pin No. Mnemonic Description
39 TXENABLE Transmit Enable
40 P2D <15> Port 2, Data Input D15 (MSB)
41 P2D <14> Port 2, Data Input D14
42 P2D <13> Port 2, Data Input D13
43 DVDD18 1.8 V Digital Supply
44 DGND Digital Common
45 P2D <12> Port 2, Data Input D12
46 P2D <11> Port 2, Data Input D11
47 P2D <10> Port 2, Data Input D10
48 P2D <9> Port 2, Data Input D9
49 P2D <8> Port 2, Data Input D8
50 P2D <7> Port 2, Data Input D7
51 P2D <6> Port 2, Data Input D6
52 P2D <5> Port 2, Data Input D5
53 DVDD18 1.8 V Digital Supply
54 DGND Digital Common
55 P2D <4> Port 2, Data Input D4
56 P2D <3> Port 2, Data Input D3
57 P2D <2> Port 2, Data Input D2
58 P2D <1> Port 2, Data Input D1
59 P2D <0> Port 2, Data Input D0 (LSB)
60 DVDD18 1.8 V Digital Supply
61 DVDD33 3.3 V Digital Supply
62 SYNC_O– Differential Synchronization Output
63 SYNC_O+ Differential Synchronization Output
64 DGND Digital Common
65 PLL_LOCK PLL Lock Indicator
66 SPI_SDO SPI Port Data Output
67 SPI_SDIO SPI Port Data Input/Output
68 SCLK SPI Port Clock
69 SPI_CSB SPI Port Chip Select Bar
70 RESET Reset, Active High
71 IRQ Interrupt Request
72 AGND Analog Common
73 IPTAT Reference Current
74 VREF Voltage Reference Output
Pin No. Mnemonic Description
75 I120 120 μA Reference Current
76 AVDD33 3.3 V Analog Supply
77 AGND Analog Common
78 AVDD33 3.3 V Analog Supply
79 AGND Analog Common
80 AVDD33 3.3 V Analog Supply
81 AGND Analog Common
82 AGND Analog Common
83 OUT2_P Differential DAC Current Output,
Channel 2
84 OUT2_N Differential DAC Current Output,
Channel 2
85 AGND Analog Common
86 AUX2_P Auxiliary DAC Voltage Output,
Channel 2
87 AUX2_N Auxiliary DAC Voltage Output,
Channel 2
88 AGND Analog Common
89 AUX1_N Auxiliary DAC Voltage Output,
Channel 1
90 AUX1_P Auxiliary DAC Voltage Output,
Channel 1
91 AGND Analog Common
92 OUT1_N Differential DAC Current Output,
Channel 1
93 OUT1_P Differential DAC Current Output,
Channel 1
94 AGND Analog Common
95 AGND Analog Common
96 AVDD33 3.3 V Analog Supply
97 AGND Analog Common
98 AVDD33 3.3 V Analog Supply
99 AGND Analog Common
100 AVDD33 3.3 V Analog Supply
1The combined differential clock input at the CLK+ and CLK– pins are referred
to as DACCLK.

AD9776/AD9778/AD9779
Rev. 0 | Page 14 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
–6.0080k
CODE
INL (16-BIT LSB)
3.0
2.0
1.0
0
–1.0
–2.0
–3.0
–4.0
–5.0
10k 20k 30k 40k 50k 60k 70k
05361-005
Figure 5. AD9779 Typical INL
1.0
–2.00 80k
CODE
DNL (16-BIT LSB)
10k 20k 30k 40k 50k 60k 70k
0.5
0
–0.5
–1.0
–1.5
05361-006
Figure 6. AD9779 Typical DNL
100
500100
fOUT (MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
fDATA = 160MSPS
fDATA = 200MSPS
fDATA = 250MSPS
05361-007
Figure 7. AD9779 In-Band SFDR vs. fOUT, 1x Interpolation
100
500100
fOUT (MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
fDATA = 160MSPS
fDATA = 200MSPS
fDATA = 250MSPS
05361-008
Figure 8. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation
100
500100
fOUT (MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
fDATA = 100MSPS
fDATA = 200MSPS
fDATA = 150MSPS
05361-009
Figure 9. AD9779 In-Band SFDR vs. fOUT, 4× Interpolation
100
500
50
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30 40
f
DATA
= 50MSPS
f
DATA
= 100MSPS
f
DATA
= 125MSPS
05361-010
Figure 10. AD9779 In-Band SFDR vs. fOUT, 8× Interpolation

AD9776/AD9778/AD9779
Rev. 0 | Page 15 of 56
100
500
100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 200MSPS
f
DATA
= 160MSPS
f
DATA
= 250MSPS
05361-011
Figure 11. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation
100
500
100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 150MSPS
f
DATA
= 100MSPS
f
DATA
= 200MSPS
05361-012
Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 4× Interpolation
100
500
50
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30 40
f
DATA
= 50MSPS
f
DATA
= 100MSPS
f
DATA
= 125MSPS
05361-013
Figure 13. AD9779 Out-of-Band SFDR vs. fOUT, 8× Interpolation
100
50040
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30
PLL OFF
PLL ON
05361-014
Figure 14. AD9779 In-Band SFDR, 4× Interpolation,
fDATA = 100 MSPS, PLL On/Off
100
50080
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60
–3dBFS
0dBFS
–6dBFS
05361-015
Figure 15. AD9779 In-Band SFDR vs. Digital Full-Scale Input
100
50080
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60
10mA
20mA
30mA
05361-016
Figure 16. AD9779 In-Band SFDR vs. Output Full-Scale Current

AD9776/AD9778/AD9779
Rev. 0 | Page 16 of 56
100
500120
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
20 40 60 80 100
f
DATA
= 200MSPS
f
DATA
= 250MSPS
f
DATA
= 160MSPS
05361-017
Figure 17. AD9779 Third Order IMD vs. fOUT, 1× Interpolation
100
500 20 40 60 80 100 120 140 160 180 200 220
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
f
DATA
= 160MSPS
f
DATA
= 250MSPS
f
DATA
= 200MSPS
05361-018
Figure 18. AD9779 Third Order IMD vs. fOUT, 2× Interpolation
100
500400
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
40 80 120 160 200 240 280 320 360
f
DATA
= 150MSPS
f
DATA
= 200MSPS
f
DATA
= 100MSPS
05361-019
Figure 19. AD9779 Third Order IMD vs. fOUT, 4× Interpolation
f
OUT
(MHz)
IMD (dBc)
f
DATA
= 75MSPS
f
DATA
= 125MSPS
f
DATA
= 100MSPS
90
100
80
70
60
50
450 425 400 375 350 325 300 275 250 225 200 175 150 125 100
75 50 25
0
f
DATA
= 50MSPS
05361-020
Figure 20. AD9779 Third Order IMD vs. fOUT, 8× Interpolation
100
500200
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
100
20 40 60 80 120 140 160 180
PLL OFF
PLL ON
05361-021
Figure 21. AD9779 Third Order IMD vs. fOUT, 4× Interpolation,
fDATA = 100 MSPS, PLL On vs. PLL Off
100
95
50
55
0400360
f
OUT
(MHz)
IMD (dBc)
90
80
85
70
75
60
65
40 80 120 160 200 240 280 320
05361-022
Figure 22. AD9779 Third Order IMD vs. fOUT, over 50 Parts,4× Interpolation,
fDATA = 200 MSPS

AD9776/AD9778/AD9779
Rev. 0 | Page 17 of 56
STOP 400.0MHz
SWEEP 1.203s (601 pts)VBW 20kHz
START 1.0MHz
*RES BW 20kHz
REF 0dBm
*PEAK
Log
10dB/
LGAV
51
W1
S3
£(f):
FTUN
SWP
S2
FC
AA
*ATTEN 20dB
EXT REF
DC COUPLED
05361-023
Figure 23. AD9779 Single Tone, 4× Interpolation, fDATA = 100 MSPS,
fOUT = 30 MHz
STOP 400.0MHz
SWEEP 1.203s (601 pts)VBW 20kHz
START 1.0MHz
*RES BW 20kHz
REF 0dBm
*PEAK
Log
10dB/
LGAV
51
W1
S3
£(f):
FTUN
SWP
S2
FC
AA
*ATTEN 20dB
EXT REF
DC COUPLED
05361-024
Figure 24. AD9779 Two-Tone Spectrum, 4× Interpolation, fDATA = 100 MSPS,
fOUT = 30,35 MHz
–142
–146
–150
–154
–158
–162
–166
–1700fOUT (MHz)
NSD (dBm/Hz)
20 40 60 80
0dBFS
–3dBFS
–6dBFS
05361-025
Figure 25. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone
Input, fDATA = 200 MSPS, 2× Interpolation
–150
–1700100
fOUT (MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
fDAC = 800MSPS
fDAC = 400MSPS
fDAC = 200MSPS
05361-026
Figure 26. AD9779 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
–150
–1700100
fOUT (MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
fDAC = 800MSPS
fDAC = 400MSPS
fDAC = 200MSPS
05361-027
Figure 27. AD9779 Noise Spectral Density vs. fDAC,
Single-Tone Input at –6 dBFS
–55
–900260
fOUT (MHz)
ACLR (dBc)
–60
–65
–70
–75
–80
–85
20 40 60 80 100 120 140 160 180 200 220 240
–6dBFS
–3dBFS
0dBFS – PLL ON
0dBFS
05361-028
Figure 28. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF

AD9776/AD9778/AD9779
Rev. 0 | Page 18 of 56
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.49dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
dBc
–76.75
–80.94
–79.95
dBm
–89.23
–93.43
–92.44
LOWER dBc
–77.42
–80.47
–78.96
dBm
–89.91
–92.96
–91.45
UPPER
REF –25.28dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
EXT REF
05361-031
Figure 29. AD9779 WCDMA Signal, 4× Interpolation,
fDATA =122.88 MSPS, fDAC/4 Modulation
–55
–900260
f
OUT
(MHz)
ACLR (dBc)
–60
–65
–70
–75
–80
–85
20 40 60 80 100 120 140 160 180 200 220 240
–6dBFS
–3dBFS
0dBFS – PLL ON
0dBFS
05361-030
Figure 30. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
–55
–900260
f
OUT
(MHz)
ACLR (dBc)
–60
–65
–70
–75
–80
–85
20 40 60 80 100 120 140 160 180 200 220 240
–6dBFS
–3dBFS
0dBFS – PLL ON
0dBFS
05361-029
Figure 31. AD9779 ACLR for Second Adjacent Band WCDMA, 4×
Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates
Baseband Signal to IF
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 151.38MHz
*RES BW 30kHz
1 –17.87dBm
2 –20.65dBm
3 –18.26dBm
4 –18.23dBm
TOTAL CARRIER POWER –12.61dBm/15.3600MHz
REF CARRIER POWER –17.87dBm/3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
INTEG BW
3.840MHz
3.840MHz
3.840MHz
dBc
–67.70
–70.00
–71.65
dBm
–85.57
–97.87
–99.52
LOWER dBc
–67.70
–69.32
–71.00
dBm
–85.57
–87.19
–88.88
UPPER
REF –30.28dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
EXT REF
05361-032
Figure 32. AD9779 Multicarrier WCDMA Signal, 4× Interpolation,
fDAC =122.88 MSPS, fDAC/4 Modulation
1.5
0 20k
CODE
INL (14-BIT LSB)
10k
1.0
0.5
0
–0.5
–1.0
–1.5 2k 4k 6k 8k 12k 14k 16k 18k
05361-033
Figure 33. AD778 Typical INL
0.6
0 18k
CODE
DNL (14-BIT LSB)
–0.2
–1.0 2k 4k 6k 8k 10k 12k 14k 16k
0.4
0.2
0
–0.4
–0.6
–0.8
05361-034
Figure 34. AD9778 Typical DNL

AD9776/AD9778/AD9779
Rev. 0 | Page 19 of 56
100
500400
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
40 80 120 160 200 240 280 320 360
4 × 200MSPS
4 × 150MSPS
4 × 100MSPS
05361-035
Figure 35. AD9778 IMD, 4× Interpolation
100
500100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 250MSPS
f
DATA
= 200MSPS
f
DATA
= 160MSPS
05361-036
Figure 36. AD9778 In-Band SFDR, 2× Interpolation
–900 250
f
OUT
(MHz)
ACLR (dBc)
–70
–80
–60
25 50 75 100 125 150 175 200 225
1ST ADJ CHAN
2ND ADJ CHAN
3RD ADJ CHAN
05361-037
Figure 37. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = –3 dBFS
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.74dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.884MHz
3.840MHz
3.840MHz
dBc
–76.49
–80.13
–80.90
dBm
–89.23
–92.87
–93.64
LOWER dBc
–76.89
–80.02
–79.53
dBm
–89.63
–92.76
–92.27
UPPER
REF –25.39dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
05361-038
Figure 38. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
–150
–1700100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
05361-039
Figure 39. AD9778 Noise Spectral Density vs. fDAC Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
–150
–1700100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
05361-040
Figure 40. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input
at –6 dBFS, fDATA = 200 MSPS

AD9776/AD9778/AD9779
Rev. 0 | Page 20 of 56
0.4
0 4096
CODE
INL (12-BIT LSB)
–0.4 512 1024 256020481536 3072 3584
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
05361-041
Figure 41. AD9776 Typical INL
0.20
0 4096
CODE
DNL (12-BIT LSB)
2048
–0.20 512 1024 1536 2560 3072 3584
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
05361-042
Figure 42. AD9776 Typical DNL
100
500400
f
OUT
(MHz)
IMD (dBc)
40 80 120 160 200 240 280 320 360
4 × 200MSPS
4 × 100MSPS
4 × 150MSPS
95
90
85
80
75
70
65
60
55
05361-043
Figure 43. AD9776 IMD, 4× Interpolation
100
500100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 250MSPS
f
DATA
= 200MSPS
f
DATA
= 160MSPS
05361-044
Figure 44. AD9776 In-Band SFDR, 2× Interpolation
–900250
f
OUT
(MHz)
ACLR (dBc)
–55
25 50 75 100 125 150 175 200 225
1ST ADJ CHAN
2ND ADJ CHAN
3RD ADJ CHAN
–60
–65
–70
–75
–80
–85
05361-045
Figure 45. AD9776, Single Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = –3 dBFS
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.67dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.884MHz
3.840MHz
3.840MHz
dBc
–75.00
–78.05
–77.73
dBm
–87.67
–90.73
–90.41
LOWER dBc
–75.30
–77.99
–77.50
dBm
–87.97
–90.66
–90.17
UPPER
REF –25.29dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
05361-046
Figure 46. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation