Analog Devices AD9779 Instruction manual

Rev. PrD
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Dual 16-Bit, 1.0 GSPS
D/A Converter
Preliminary Technical Data AD9779
FEATURES
•1.8/3.3 V Single Supply Operation
•Low power: 950mW (IOUTFS = 20 mA; fDAC = 1 GSPS, 4×
Interpolation
•DNL = ± 1.5 LSB, INL = ± 5.0 LSB
•SFDR =82 dBc to fOUT = 100 MHz
•ACLR = 87 dBc @ 80 MHz IF
•CMOS data interface with Autotracking Input Timing
•Analog Output: Adjustable 10-30mA (RL=25 Ωto 50 Ω)
•100-lead Exposed Paddle TQFP Package
•Multiple Chip Synchronization Interface
•84dB Digital Interpolation Filter Stopband Attenuation
•Digital Inverse Sinc Filter
APPLICATIONS
•Wireless Infrastructure
Direct Conversion
Transmit Diversity
•Wideband Communications Systems:
Point-to-Point Wireless, LMDS
PRODUCT DESCRIPTION
The AD9779 is a dual 16-bit high performance, high frequency
DAC that provides a sample rate of 1 GSPS, permitting multi
carrier generation up to its Nyquist frequency. It includes features
optimized for direct conversion transmit applications, including
complex digital modulation and gain and offset compensation. The
DAC outputs are optimized to interface seamlessly with analog
quadrature modulators such as the AD8349. A serial peripheral
interface (SPI) provides for programming many internal
parameters and also enables read-back of status registers. The
output current can be programmed over a range of 10mA to 30mA.
The AD9779 is manufactured on an advanced 0.18µm CMOS
process and operates from 1.8V and 3.3V supplies for a total power
consumption of 950mW. It is supplied in a 100-lead QFP package.
PRODUCT HIGHLIGHTS
Ultra-low noise and Intermodulation Distortion (IMD) enable
high quality synthesis of wideband signals from baseband to high
intermediate frequencies.
Single-ended CMOS interface supports a maximum input rate of
300 MSPS with 1x interpolation.
Manufactured on a CMOS process, the AD9779 uses a proprietary
switching technique that enhances dynamic performance.
The current outputs of the AD9779 can be easily configured for
various single-ended or differential circuit topologies.
FUNCTIONAL BLOCK DIAGRAM
Complex
Modulator
Clock Generation/Distribution
2X
n * Fdac/8
n = 1, 2, 3… 7
P2D[15:0]
IOUT2_P
IOUT2_N
CLK+
CLK-
DATACLK_OUT
2X2X
2X2X2X
Sinc-1
Sinc-1
16-Bit
IDAC
16-Bit
QDAC
Digital Controller
Clock
Multiplier
2X/4X/8X
Gain
Gain
Offset
Offset
Reference
& Bias
10
10
10
10
Power-On
Reset
Serial
Peripheral
Interface
Q Latch
I Latch
Delay Line
Delay Line
Data
Assembler
SDIO
SDO
SCLK
CSB
IOUT1_P
IOUT1_N
VREF
RSET
AUX1_P
AUX1_N
AUX2_P
AUX2_N
P1D[15:0]
SYNC_I
SYNC_O
Figure 1 Functional Block Diagram

AD9779 Preliminary Technical Data
Rev. PrD | Page 2 of 34
TABLE OF CONTENTS
Specifications............................................................................................3
DC SPECIFICATIONS ......................................................................3
DIGITAL SPECIFICATIONS............................................................4
AC SPECIFICATIONS.......................................................................4
Pin Function Descriptions .....................................................................5
Pin Configuration....................................................................................6
Interpolation Filter Coefficients............................................................7
INTERPOLATION Filter RESPONSE CURVES ................................8
CHARACTERIZATION DATA ............................................................9
General Description..............................................................................12
Serial Peripheral Interface................................................................12
General Operation of the Serial Interface......................................12
Instruction Byte .................................................................................12
Serial Interface Port Pin Descriptions............................................12
MSB/LSB Transfers ...........................................................................13
Notes on Serial Port Operation .......................................................13
SPI Register Map ...............................................................................14
Internal Reference/Full Scale Current Generation.......................22
Auxiliary DACs..................................................................................22
Power Down and Sleep Modes........................................................22
Internal PLL Clock Multiplier / Clock Distribution.....................23
Timing Information ..........................................................................23
Interpolation Filter Architecture.....................................................25
EvaLuation Board Schematics..............................................................27
REVISION HISTORY
Revision PrA: Initial Version
Revision PrB: Updated Page 1 Features, added eval board schematics, SPI register map, filter coefficients and filter response curves
Revision PrC: Added characterization data, description of modulation modes, internal clock distribution architecture, timing information
Revision PrD: Added more ac characterization data, power dissipation

Preliminary Technical Data AD9779
Rev. PrD | Page 3 of 34
SPECIFICATIONS1
DC SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter Temp Test Level Min Typ Max Unit
RESOLUTION 16 Bits
Integral Nonlinearity (DNL) ±1.5 LSB
ACCURACY Differential Nonlinearity (INL) ±5 LSB
Offset Error ±TBD % FSR
Gain Error (With Internal Reference) ±TBD % FSR
Gain Error (Without Internal Reference) ±TBD % FSR
Full Scale Output Current 10 20 30 mA
Output Compliance Range 1.0 V
Output Resistance TBD kΩ
ANALOG OUTPUTS
Output Capacitance TBD pF
Offset TBD ppm/°C
Gain TBD ppm/°C TEMPERATURE DRIFT
Reference Voltage TBD ppm/°C
Internal Reference Voltage 1.2 V
REFERENCE Output Current 100 nA
VDDA33 3.13 3.3 3.47 V
ANALOG SUPPLY
VOLTAGES VDDA18 1.70 1.8 1.90 V
VDDD33 3.13 3.3 3.47 V
VDDD18 1.70 1.8 1.90 V
DIGITAL SUPPLY
VOLTAGES VDDCLK 1.70 1.8 1.90 V
600 MSPS TBD mWPOWER CONSUMPTION
Standby Power TBD mW
Table 1: DC Specifications
1Specifications subject to change without notice

AD9779 Preliminary Technical Data
Rev. PrD | Page 4 of 34
DIGITAL SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter Temp Test Level Min Typ Max Unit
Differential peak-to-peak Voltage 800 mV
Common Mode Voltage 400 mV
DAC CLOCK INPUT
(CLK+, CLK-) Maximum Clock Rate 1 GSPS
Maximum Clock Rate (SCLK) 40 MHz
Maximum Pulse width high TBD ns
SERIAL PERIPHERAL
INTERFACE Maximum pulse width low TBD ns
Table 2: Digital Specifications
AC SPECIFICATIONS
(VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED)
Parameter Temp Test Level Min Typ Max Unit
Output Settling Time (tst) (to 0.025%) TBD ns
Output Rise Time (10% to 90%) TBD ns
Output Fall Time (90% to 10%) TBD ns
DYNAMIC
PERFORMANCE
Output Noise (IoutFS=20mA) TBD pA/rtHz
fDAC = 100 MSPS, fOUT = 20 MHz 82 dBc
fDAC = 200 MSPS, fOUT = 50 MHz 82 dBc
fDAC = 400 MSPS, fOUT = 70 MHz 84 dBc
SPURIOUS FREE
DYNAMIC RANGE
(SFDR)
fDAC = 800 MSPS, fOUT = 70 MHz 87 dBc
fDAC = 200 MSPS, fOUT = 50 MHz 91 dBc
fDAC = 400 MSPS, fOUT = 60 MHz 88 dBc
fDAC = 400 MSPS, fOUT = 80 MHz 81 dBc
TWO-TONE
INTERMODULATION
DISTORTION (IMD)
fDAC = 800 MSPS, fOUT = 100 MHz 88 dBc
fDAC = 156 MSPS, fOUT = 60 MHz -158 dBm/Hz
fDAC = 200 MSPS, fOUT = 80 MHz -157 dBm/Hz
fDAC = 312 MSPS, fOUT = 100 MHz -159 dBm/Hz
NOISE SPECTRAL
DENSITY (NSD)
fDAC = 400 MSPS, fOUT = 100 MHz -159 dBm/Hz
fDAC = 245.76 MSPS, fOUT = 20 MHz 80 dBc
fDAC = 491.52 MSPS, fOUT = 100 MHz 79 dBc
WCDMA ADJACENT
CHANNEL LEAKAGE
RATIO (ACLR), SINGLE
CARRIER fDAC = 491.52 MSPS, fOUT = 200 MHz 74 dBc
fDAC = 245.76 MSPS, fOUT = 60 MHz 78 dBc
fDAC = 491.52 MSPS, fOUT = 100 MHz 80 dBc
WCDMA SECOND
ADJACENT CHANNEL
LEAKAGE RATIO
(ACLR), SINGLE
CARRIER
fDAC = 491.52 MSPS, fOUT = 200 MHz 76 dBc
Table 3: AC Specifications

Preliminary Technical Data AD9779
Rev. PrD | Page 5 of 34
PIN FUNCTION DESCRIPTIONS
Pin
No.
Name Description Pin
No.
Name Description
1 VDDC18 1.8 V Clock Supply 51 P2D<6> Port 2 Data Input D6
2 VDDC18 1.8 V Clock Supply 52 P2D<5> Port 2 Data Input D5
3 VSSC Clock Common 53 VDDD18 1.8 V Digital Supply
4 VSSC Clock Common 54 VSSD Digital Common
5 CLK+ Differential Clock Input 55 P1D<4> Port 2 Data Input D4
6 CLK- Differential Clock Input 56 P1D<3> Port 2 Data Input D3
7 VSSC Clock Common 57 P1D<2> Port 2 Data Input D2
8 VSSC Clock Common 58 P1D<1> Port 2 Data Input D1
9 VDDC18 1.8 V Clock Supply 59 P1D<0> Port 2 Data Input D0 (LSB)
10 VDDC18 1.8 V Clock Supply 60 VDDD18 1.8 V Digital Supply
11 VSSC Clock Common 61 VDDD33 3.3 V Digital Supply
12 VSSC Clock Common 62 SYNC_O- Differential Synchronization Output
13 SYNC_I+ Differential Synchronization Input 63 SYNC_O+ Differential Synchronization Output
14 SYNC_I- Differential Synchronization Input 64 VSSD Digital Common
15 VSSD Digital Common 65 PLL_LOCK PLL Lock Indicator
16 VDDD33 3.3 V Digital Supply 66 SPI_SDO SPI Port Data Output
17 P1D<15> Port 1 Data Input D15 (MSB) 67 SPI_SDIO SPI Port Data Input/Output
18 P1D<14> Port 1 Data Input D14 68 SPI_CLK SPI Port Clock
19 P1D<13> Port 1 Data Input D13 69 SPI_CSB SPI Port Chip Select Bar
20 P1D<12> Port 1 Data Input D12 70 RESET Reset
21 P1D<11> Port 1 Data Input D11 71 IRQ Interrupt Request
22 VSSD Digital Common 72 VSS Analog Common
23 VDDD18 1.8 V Digital Supply 73 IPTAT Reference Current
24 P1D<10> Port 1 Data Input D10 74 VREF Voltage Reference Output
25 P1D<9> Port 1 Data Input D9 75 I120 120 µA Reference Current
26 P1D<8> Port 1 Data Input D8 76 VDDA33 3.3 V Analog Supply
27 P1D<7> Port 1 Data Input D7 77 VSSA Analog Common
28 P1D<6> Port 1 Data Input D6 78 VDDA33 3.3 V Analog Supply
29 P1D<5> Port 1 Data Input D5 79 VSSA Analog Common
30 P1D<4> Port 1 Data Input D4 80 VDDA33 3.3 V Analog Supply
31 P1D<3> Port 1 Data Input D3 81 VSSA Analog Common
32 VSSD Digital Common 82 VSSA Analog Common
33 VDDD18 1.8 V Digital Supply 83 IOUT2_P Differential DAC Current Output, Channel 2
34 P1D<2> Port 1 Data Input D2 84 IOUT2_N Differential DAC Current Output, Channel 2
35 P1D<1> Port 1 Data Input D1 85 VSSA Analog Common
36 P1D<0> Port 1 Data Input D0 (LSB) 86 AUX2_P Auxiliary DAC Voltage Output, Channel 2
37 DATACLK_OUT Data Clock Output 87 AUX2_N Auxiliary DAC Voltage Output, Channel 2
38 VDDD33 3.3 V Digital Supply 88 VSSA Analog Common
39 TXENABLE Transmit Enable 89 AUX1_N Auxiliary DAC Voltage Output, Channel 1
40 P2D<15> Port 2 Data Input D15 (MSB) 90 AUX1_P Auxiliary DAC Voltage Output, Channel 1
41 P2D<14> Port 2 Data Input D14 91 VSSA Analog Common
42 P2D<13> Port 2 Data Input D13 92 IOUT1_N Differential DAC Current Output, Channel 1
43 VDDD18 1.8 V Digital Supply 93 IOUT1_P Differential DAC Current Output, Channel 1
44 VSSD Digital Common 94 VSSA Analog Common
45 P2D<12> Port 2 Data Input D12 95 VSSA Analog Common
46 P2D<11> Port 2 Data Input D11 96 VDDA33 3.3 V Analog Supply
47 P2D<10> Port 2 Data Input D10 97 VSSA Analog Common
48 P2D<9> Port 2 Data Input D9 98 VDDA33 3.3 V Analog Supply
49 P2D<8> Port 2 Data Input D8 99 VSSA Analog Common
50 P2D<7> Port 2 Data Input D7 100 VDDA33 3.3 V Analog Supply
Table 4: Pin Function Descriptions

AD9779 Preliminary Technical Data
Rev. PrD | Page 6 of 34
PIN CONFIGURATION
VDDD18
VDDD18
VSSD
P2D<5>
P2D<4>
P2D<3>
P2D<2>
P2D<1>
P2D<0>
SYNC_O-
SPI_SDO
SPI_SDI
51
52
53
54
VDDA33
VSSA
VDDA33
VSSA
VDDA33
VSSA
AUX2_P
AUX2_N
VSSA
IOUT2_P
IOUT2_N
VSSA VSSA VSSA
IOUT1_N
IOUT1_P
VSSA
AUX1_N
76 77 78 79
VSSD
VDDD33
VSSD
VDDD18
P1D<10>
P1D<11>
P1D<12>
P1D<13>
P1D<14>
P1D<15>
SYNC_I-
SYNC_I+
VSSC
VSSC
P2D<11>
VDDD33
P2D<12> P2D<13> P2D<14> P2D<15>
DCLK
P1D<0> P1D<1> P1D<2> P1D<3>
VDDD18
VSSD
P1D<4> P1D<5> P1D<6> P1D<7> P1D<8>
P1D<9>
27 26
P2D<7> P2D<8> P2D<9>
P2D<10>
50 49
AUX1_P
VSSA
VDDA33
VSSA
VDDA33
CLK-
CLK+
VDDC18
VSSC
VSSC
3
2
VDDC18
VSSC
VSSC
VDDC18
1
VDDC18
25
24
75
74
100
99
SPI_CLK
SPI_CSB
RESET
IPTAT
VREF
IRQ
AD9779
VSSA
VDDA33
SYNC_O+
VSSD
VSS
TXEnable
P2D<6>
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
6
5
4
9
8
7
12
11
10
15
14
13
18
17
16
21
20
19
23
22
34 33 30 29 28 32 31 36 35 43 42 39 38 37 41 40 48 47 44 46 45
80 81 84 82 83 85 86 89 87 88 90 91 94 92 93 95 98 96 97
I120
PLL_LOCK
Analog Domain
Digital Domain
VDDD18
VSSD
VDDD33
Figure 2. Pin Configuration

Preliminary Technical Data AD9779
Rev. PrD | Page 7 of 34
INTERPOLATION FILTER COEFFICIENTS
Table 5: Halfband Filter 1
Lower
Coefficient
Upper
Coefficient
Integer
Valu e
H(1) H(55) -4
H(2) H(54) 0
H(3) H(53) 13
H(4) H(52) 0
H(5) H(51) -34
H(6) H(50) 0
H(7) H(49) 72
H(8) H(48) 0
H(9) H(47) -138
H(10) H(46) 0
H(11) H(45) 245
H(12) H(44) 0
H(13) H(43) -408
H(14) H(42) 0
H(15) H(41) 650
H(16) H(40) 0
H(17) H(39) -1003
H(18) H(38) 0
H(19) H(37) 1521
H(20) H(36) 0
H(21) H(35) -2315
H(22) H(34) 0
H(23) H(33) 3671
H(24) H(32) 0
H(25) H(31) -6642
H(26) H(30) 0
H(27) H(29) 20755
H(28) 32768
Table 6: Halfband Filter 2
Lower
Coefficient
Upper
Coefficient
Integer
Valu e
H(1) H(23) -2
H(2) H(22) 0
H(3) H(21) 17
H(4) H(20) 0
H(5) H(19) -75
H(6) H(18) 0
H(7) H(17) 238
H(8) H(16) 0
H(9) H(15) -660
H(10) H(14) 0
H(11) H(13) 2530
H(12) 4096
Table 7: Halfband Filter 3
Lower
Coefficient
Upper
Coefficient
Integer
Valu e
H(1) H(15) -39
H(2) H(14) 0
H(3) H(13) 273
H(4) H(12) 0
H(5) H(11) -1102
H(6) H(10) 0
H(7) H(9) 4964
H(8) 8192
Table 8: Inverse Sinc Filter
Lower
Coefficient
Upper
Coefficient
Integer
Valu e
H(1) H(9) 2
H(2) H(8) -4
H(3) H(7) 10
H(4) H(6) -35
H(5) 401

AD9779 Preliminary Technical Data
Rev. PrD | Page 8 of 34
INTERPOLATION FILTER RESPONSE CURVES
-4 -3 -2 -1 01234
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Figure 3. AD9779 2x Interpolation, Low Pass Response to
±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off)
-4 -3 -2 -1 01234
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Figure 4. AD9779 4x Interpolation, Low Pass Response to
±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off)
-4 -3 -2 -1 01234
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Figure 5.AD9779 8x Interpolation, Low Pass Response to
±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off)

Preliminary Technical Data AD9779
Rev. PrD | Page 9 of 34
CHARACTERIZATION DATA
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 8192 16384 24576 32768 40960 49152 57344 65536
Code
INL (LSBs)
Figure 6. AD9779 Typical INL
-1
-0.5
0
0.5
1
1.5
2
0 8192 16384 24576 32768 40960 49152 57344 65536
Code
DNL (LSBs)
Figure 7. AD9779 Typical DNL
50
60
70
80
90
100
020406080100
Fout - MHz
SFDR - dBm
F
DATA
=100MSPS F
DATA
=160MSPS F
DATA
=200MSPS
Figure 8. SFDR vs. FOUT, 1x Interpolation
50
55
60
65
70
75
80
85
90
95
100
0 20406080100
Fout - MHz
SFDR -dBm
F
DATA
=100MSPS F
DATA
=160MSPS F
DATA
=200MSPS
Figure 9. SFDR vs. FOUT, 2x Interpolation
50
55
60
65
70
75
80
85
90
95
100
0 20406080
Fout - MHz
SFDR - dBm
F
DATA
=100MSPS F
DATA
=125MSPS
F
DATA
=150MSPS
F
DATA
=200MSPS
Figure 10. SFDR vs. FOUT, 4x Interpolation
50
60
70
80
90
100
0 1020304050
Fout - MHz
SFDR - dBm
50MSPS
75MSPS
FDATA=62.5MSPS
100MSPS
Figure 11. SFDR vs. FOUT, 8x Interpolation

AD9779 Preliminary Technical Data
Rev. PrD | Page 10 of 34
50.0
60.0
70.0
80.0
90.0
100.0
020406080
Fout - MHz
IMD - dBc
F
DATA
=160MSPS
F
DATA
=200MSPS
Figure 12. Third Order IMD vs. FOUT, 1x Interpolation
50.0
60.0
70.0
80.0
90.0
100.0
0 20 40 60 80 100 120 140 160 180 200
Fout - MHz
IMD - dBc
F
DATA
=160MSPS
F
DATA
=200MSPS
Figure 13. Third Order IMD vs. FOUT, 2x Interpolation
50
60
70
80
90
100
0 40 80 120 160 200 240 280 320 360 400
Fout - MHz
IMD - dBc
F
DATA
=100MSPS
F
DATA
=125MSPS
F
DATA
=150MSPS
F
DATA
=200MSPS
Figure 14. Third Order IMD vs. FOUT, 4x Interpolation
50
60
70
80
90
100
0 50 100 150 200 250 300 350 400 450
Fout - MHz
IMD - dBc
50MSPS
100MSPS
F
DATA
=62.5MSPS
112.5MSPS
75MSPS
Figure 15. Third Order IMD vs. FOUT, 8x Interpolation
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
0 102030405060708090
Fout - MHz
NSD - dBm/Hz
F
DATA
=78MSPS F
DATA
=156MSPS
F
DATA
=200MSPS
Figure 16. Noise Spectral Density vs. FOUT, 1x Interpolation
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
0 20 40 60 80 100 120 140 160 180
Fout - MHz
NSD - dBm/Hz
FDATA=78MSPS
FDATA=156MSPS
FDATA=200MSPS
Figure 17. Noise Spectral Density vs. FOUT, 2x Interpolation