Analog Devices AD9776A User manual

Dual 12-/14-/16-Bit,1 GSPS,
Digital-to-Analog Converters
AD9776A/AD9778A/AD9779A
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
Single carrier W-CDMA ACLR = 7 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL= 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit,
high dynamic range, digital-to-analog converters (DACs) that
provide a sample rate of 1 GSPS, permitting a multicarrier
generation up to the Nyquist frequency. They include features
optimized for direct conversion transmit applications, including
complex digital modulation, and gain and offset compensation.
The DAC outputs are optimized to interface seamlessly with
analog quadrature modulators such as the ADL537x FMOD
series from Analog Devices, Inc. A serial peripheral interface
(SPI) provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The devices are manufactured on
an advanced 0.18 m CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in a 100-lead TQFP.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable setup and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
TYPICAL SIGNAL CHAIN
FPGA/ASIC/DSP
DC
COMPLEX I AND Q
DC LO
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
I DAC
Q DAC
DIGITAL INTERPOLATION FILTERS
AD9776A/AD9778A/AD9779A
POST DAC
ANALOG FILTER
A
0
6452-114
Figure 1.
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AD9776A/AD9778A/AD9779A
Rev. A | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Digital Input Data Timing Specifications ................................. 6
AC Specifications.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
Differences Between AD9776/AD9778/ AD9779 and
AD9776A/AD9778A/AD9779A............................................... 23
Serial Peripheral Interface ............................................................. 24
General Operation of the Serial Interface ............................... 24
Instruction Byte .......................................................................... 24
Serial Interface Port Pin Descriptions ..................................... 25
MSB/LSB Transfers..................................................................... 25
SPI Register Map............................................................................. 26
Interpolation Filter Architecture .................................................. 31
Interpolation Filter Bandwidth Limits .................................... 35
Sourcing the DAC Sample Clock ................................................. 36
Direct Clocking .......................................................................... 36
Clock Multiplication .................................................................. 36
Driving the REFCLK Input....................................................... 38
Full-Scale Current Generation ..................................................... 39
Internal Reference ...................................................................... 39
Transmit Path Gain and Offset Correction................................. 40
I/Q Channel Gain Matching..................................................... 40
Auxiliary DAC Operation......................................................... 40
LO Feedthrough Compensation .............................................. 41
Results of Gain and Offset Correction .................................... 41
Input Data Ports ............................................................................. 42
Single Port Mode ........................................................................ 42
Dual Port Mode .......................................................................... 42
Input Data Referenced to DATACLK...................................... 42
Input Data Referenced to REFCLK ......................................... 43
Optimizing the Data Input Timing.......................................... 44
Device Synchronization................................................................. 45
Synchronization Logic Overview............................................. 45
Synchronizing Devices to a System Clock .............................. 46
Interrupt Request Operation .................................................... 46
Power Dissipation........................................................................... 47
Power-Down and Sleep Modes................................................. 48
Evaluation Board Operation......................................................... 49
Using the ADL5372 Quadrature Modulator .......................... 51
Evaluation Board Schematics ................................................... 52
Outline Dimensions....................................................................... 60
Ordering Guide .......................................................................... 60
REVISION HISTORY
3/08—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Added Note 2 .................................................................................... 4
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 6
Changes to Thermal Resistance Section........................................ 7
Inserted Table 6................................................................................. 8
Changes to Pin 39 Description, Table 7......................................... 9
Changes to Pin 39 Description, Table 8....................................... 10
Changes to Pin 39 Description, Table 9....................................... 12
Changes to Theory of Operation Section.................................... 23
Changes to Table 10 ....................................................................... 23
Changes to Table 13 ....................................................................... 26
Changes to Table 14 ....................................................................... 27
Changes to Interpolation Filter Architecture Section ............... 33
Replaced Sourcing the DAC Sample Clock Section .................. 36
Replaced Transmit Path Gain and Offset Correction Section . 40
Replaced Input Data Ports Section .............................................. 42
Replaced Device Synchronization Section.................................. 45
Deleted Figure 112 to Figure 117 ................................................. 58
8/07—Revision 0: Initial Version
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AD9776A/AD9778A/AD9779A
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FUNCTIONAL BLOCK DIAGRAM
10
10
10
10
CLOCK GENERATION/DISTRIBUTION
DATA
ASSEMBLER
DIGITAL CONTROLLER
2× 2×
SYNC
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
I DAC
REFCLK+
REFCLK–
OUT1_P
OUT1_N
AUX1_P
AUX1_N
AUX2_P
AUX2_N
OUT2_P
OUT2_N
GAIN
GAIN
GAIN
GAIN
16-BIT
Q DAC
2×
SYNC
I
LATCH
DELAY
LINE
Q
LATCH
P2D<15:0>
P1D<15:0>
SYNC_O
SYNC_I
DATACLK
2× 2× 2×
n × fDAC/8
n = 0, 1, 2 ... 7
POWER-ON
RESET
SDO
SDIO
SCL
K
CSB
SERIAL
PERIPHERAL
INTERFACE
COMPLEX
MODULATOR
REFERENCE
AND BIAS
VREF
I120
DELAY
LINE
AD9779A
0
6452-001
Figure 2. AD9779A Functional Block Diagram
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AD9776A/AD9778A/AD9779A
Rev. A | Page 4 of 60
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless
otherwise noted.
Table 1.
AD9776A AD9778A AD9779A
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 14 16 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.1 ±0.65 ±2.1 LSB
Integral Nonlinearity (INL) ±0.6 ±1 ±3.7 LSB
MAIN DAC OUTPUTS
Offset Error −0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR
Gain Error (With Internal Reference) ±2 ±2 ±2 % FSR
Full-Scale Output Current18.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA
Output Compliance Range −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V
Output Resistance 10 10 10 MΩ
Gain DAC Monotonicity Guaranteed Guaranteed Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset 0.04 0.04 0.04 ppm/°C
Gain 100 100 100 ppm/°C
Reference Voltage 30 30 30 ppm/°C
AUX DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current1 −1.998 +1.998 −1.998 +1.998 −1.998 +1.998 mA
Output Compliance Range (Source) 0 1.6 0 1.6 0 1.6 V
Output Compliance Range (Sink) 0.8 1.6 0.8 1.6 0.8 1.6 V
Output Resistance 1 1 1 MΩ
AUX DAC Monotonicity Guaranteed Guaranteed Guaranteed
REFERENCE
Internal Reference Voltage 1.2 1.2 1.2 V
Output Resistance 5 5 5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
CVDD18 1.70 1.8 2.05 1.70 1.8 2.05 1.70 1.8 2.05 V
DIGITAL SUPPLY VOLTAGES
DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
DVDD18 1.70 1.8 2.05 1.70 1.8 2.05 1.70 1.8 2.05 V
POWER CONSUMPTION2
1× Mode, fDAC = 100 MSPS, IF = 1 MHz 250 300 250 300 250 300 mW
2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL Off 498 498 498 mW
2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL On 588 588 588 mW
4× Mode, fDAC/4 Modulation, fDAC = 500 MSPS,
IF = 137.5 MHz, Q DAC Off
572 572 572 mW
8× Mode, fDAC/4 Modulation, fDAC = 1 GSPS,
IF = 262.5 MHz
980 980 980 mW
Power-Down Mode 2.5 9.8 2.5 9.8 2.5 9.8 mW
Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 % FSR/V
OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 °C
1Based on a 10 kΩ external resistor.
2See the Power Dissipation section for more details.
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DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High 2.0 V
Input VIN Logic Low 0.8 V
Maximum Input Data Rate at Interpolation
1× 300 MSPS
2× 250 MSPS
4× 200 MSPS
8× DVDD18, CVDD18 = 1.8 V ± 5% 112.5 MSPS
DVDD18, CVDD18 = 1.9 V ± 5% 125 MSPS
DVDD18, CVDD18 = 2.0 V ± 2% 137.5 MSPS
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1
Output VOUT Logic High 2.4 V
Output VOUT Logic Low 0.4 V
DATACLK Output Duty Cycle At 250 MHz, into 5 pF load 40 50 60 %
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = VIA, SYNC_I− = VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN 80 120 Ω
LVDS Input Rate Additional limits on fSYNC_I apply; see description of
Register 5, Bits<3:1> in Table 14
250 MSPS
Setup Time, SYNC_I to REFCLK 0.4 ns
Hold Time, SYNC_I to REFCLK 0.55 ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Output Voltage High, VOA or VOB 1375 mV
Output Voltage Low, VOA or VOB 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, ROSingle-ended 80 100 120 Ω
DAC CLOCK INPUT (REFCLK+, REFCLK−)
Differential Peak-to-Peak Voltage 400 800 2000 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate DVDD18, CVDD18 = 1.8 V ± 5% 900 MSPS
DVDD18, CVDD18 = 1.9 V ± 5% 1000 MSPS
DVDD18, CVDD18 = 2.0 V ± 2% 1100 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
Setup Time, SDI to SCLK 1.6 ns
Hold Time, SDI to SCLK 0.0 ns
Data Valid, SDO to SCLK 2.0 ns
1Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
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DIGITAL INPUT DATA TIMING SPECIFICATIONS
All modes, −40°C to +85°C.
Table 3.
Parameter Conditions Min Typ Max Unit
Input Data1
Setup Time Input data to DATACLK 3.0 ns
Hold Time Input data to DATACLK 0.0 ns
Setup Time Input data to REFCLK −0.8 ns
Hold Time Input data to REFCLK 3.7 ns
Latency
1× Interpolation With or without modulation 25 DACCLK Cycles
2× Interpolation With or without modulation 70 DACCLK Cycles
4× Interpolation With or without modulation 146 DACCLK Cycles
8× Interpolation With or without modulation 297 DACCLK Cycles
Inverse Sync 18 DACCLK Cycles
Power-Up Time2260 ms
1Timing vs. temperature and data valid keep out windows are delineated in Table 25.
2Measured from CSB rising edge on Register 0x00, Bit 4 write from 0 to 1. VREF decoupling capacitor equal to 0.1 μF.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless
otherwise noted.
Table 4.
AD9776A AD9778A AD9779A
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 100 MSPS, fOUT = 20 MHz 82 82 82 dBc
fDAC = 200 MSPS, fOUT = 50 MHz 81 81 82 dBc
fDAC = 400 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 800 MSPS, fOUT = 70 MHz 85 85 87 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 200 MSPS, fOUT = 50 MHz 87 87 91 dBc
fDAC = 400 MSPS, fOUT = 60 MHz 80 85 85 dBc
fDAC = 400 MSPS, fOUT = 80 MHz 75 81 81 dBc
fDAC = 800 MSPS, fOUT = 100 MHz 75 80 81 dBc
NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz
TONE SPACING
fDAC = 200 MSPS, fOUT = 80 MHz −152 −155 −158 dBm/Hz
fDAC = 400 MSPS, fOUT = 80 MHz −155 −159 −160 dBm/Hz
fDAC = 800 MSPS, fOUT = 80 MHz −157.5 −160 −161 dBm/Hz
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz 76 78 79 dBc
fDAC = 491.52 MSPS, fOUT = 200 MHz 69 73 74 dBc
W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO
(ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz 77.5 80 81 dBc
fDAC = 491.52 MSPS, fOUT = 200 MHz 76 78 78 dBc
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AD9776A/AD9778A/AD9779A
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ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter With Respect To Rating
AVDD33, DVDD33 AGND, DGND,
CGND
−0.3 V to +3.6 V
DVDD18, CVDD18 AGND, DGND,
CGND
−0.3 V to +2.1 V
AGND DGND, CGND −0.3 V to +0.3 V
DGND AGND, CGND −0.3 V to +0.3 V
CGND AGND, DGND −0.3 V to +0.3 V
I120, VREF, IPTAT AGND −0.3 V to
AVDD33 + 0.3 V
OUT1_P, OUT1_N,
OUT2_P, OUT2_N,
AUX1_P, AUX1_N,
AUX2_P, AUX2_N
AGND −1.0 V to
AVDD33 + 0.3 V
P1D<15> to P1D<0>,
P2D<15> to P2D<0>
DGND −0.3 V to
DVDD33 + 0.3 V
DATACLK, TXENABLE DGND −0.3 V to
DVDD33 + 0.3 V
REFCLK+, REFCLK− CGND −0.3 V to
CVDD18 + 0.3 V
RESET, IRQ, PLL_LOCK,
SYNC_O+, SYNC_O−,
SYNC_I+, SYNC_I−,
CSB, SCLK, SDIO, SDO
DGND −0.3 V to
DVDD33 + 0.3 V
Junction Temperature +125°C
Storage Temperature
Range
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
For optimal thermal performance, the exposed paddle (EPAD)
should be soldered to the ground plane for the 100-lead,
thermally enhanced TQFP_EP package.
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation effectively reducing θJA.
Table 6. Thermal Resistance
Package Type θJA θ
JB θ JC Unit
100-Lead TQFP_EP
EPAD Soldered 19.1 12.4 7.1 °C/W
EPAD Not Soldered 27.4 °C/W
ESD CAUTION
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
74 VREF
73 IPTAT
72 AGND
69 CSB
70 RESET
71 IRQ
75 I120
68 SCLK
67 SDIO
66 SDO
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 NC
58 NC
57 NC
56 NC
55 P2D<0>
54 DGND
53 DVDD18
52 P2D<1>
51 P2D<2>
65 PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<4>
27
P1D<3>
28
P1D<2>
29
P1D<1>
30
P1D<0>
31
NC
32
DGND
33
DVDD18
34
NC
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<11>
41
P2D<10>
42
P2D<9>
43
DVDD18
44
DGND
45
P2D<8>
46
P2D<7>
47
P2D<6>
48
P2D<5>
49
P2D<4>
50
P2D<3>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<11>
18
P1D<10>
19
P1D<9>
20
P1D<8>
21
P1D<7>
22
DGND
23
DVDD18
24
P1D<6>
25
P1D<5>
11
CGND
AD9776A
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
06452-002
Figure 3. AD9776A Pin Configuration
Table 7. AD9776A Pin Function Descriptions
Pin
No. Mnemonic Description
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply. 20 P1D<8> Port 1, Data Input D8.
2 CVDD18 1.8 V Clock Supply. 21 P1D<7> Port 1, Data Input D7.
3 CGND Clock Ground. 22 DGND Digital Ground.
4 CGND Clock Ground. 23 DVDD18 1.8 V Digital Supply.
5 REFCLK+ Differential Clock Input. 24 P1D<6> Port 1, Data Input D6.
6 REFCLK− Differential Clock Input. 25 P1D<5> Port 1, Data Input D5.
7 CGND Clock Ground. 26 P1D<4> Port 1, Data Input D4.
8 CGND Clock Ground. 27 P1D<3> Port 1, Data Input D3.
9 CVDD18 1.8 V Clock Supply. 28 P1D<2> Port 1, Data Input D2.
10 CVDD18 1.8 V Clock Supply. 29 P1D<1> Port 1, Data Input D1.
11 CGND Clock Ground. 30 P1D<0> Port 1, Data Input D0 (LSB).
12 AGND Analog Ground. 31 NC No Connect.
13 SYNC_I+ Differential Synchronization Input. 32 DGND Digital Ground.
14 SYNC_I− Differential Synchronization Input. 33 DVDD18 1.8 V Digital Supply.
15 DGND Digital Ground. 34 NC No Connect.
16 DVDD18 1.8 V Digital Supply. 35 NC No Connect.
17 P1D<11> Port 1, Data Input D11 (MSB). 36 NC No Connect.
18 P1D<10> Port 1, Data Input D10. 37 DATACLK Data Clock Output.
19 P1D<9> Port 1, Data Input D9. 38 DVDD33 3.3 V Digital Supply.
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AD9776A/AD9778A/AD9779A
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Pin
No. Mnemonic Description
39 TXENABLE
Transmit Enable. In single port mode, this
pin also functions as IQSELECT.
40 P2D<11> Port 2, Data Input D11 (MSB).
41 P2D<10> Port 2, Data Input D10.
42 P2D<9> Port 2, Data Input D9.
43 DVDD18 1.8 V Digital Supply.
44 DGND Digital Ground.
45 P2D<8> Port 2, Data Input D8.
46 P2D<7> Port 2, Data Input D7.
47 P2D<6> Port 2, Data Input D6.
48 P2D<5> Port 2, Data Input D5.
49 P2D<4> Port 2, Data Input D4.
50 P2D<3> Port 2, Data Input D3.
51 P2D<2> Port 2, Data Input D2.
52 P2D<1> Port 2, Data Input D1.
53 DVDD18 1.8 V Digital Supply.
54 DGND Digital Ground.
55 P2D<0> Port 2, Data Input D0 (LSB).
56 NC No Connect.
57 NC No Connect.
58 NC No Connect.
59 NC No Connect.
60 DVDD18 1.8 V Digital Supply.
61 DVDD33 3.3 V Digital Supply.
62 SYNC_O− Differential Synchronization Output.
63 SYNC_O+ Differential Synchronization Output.
64 DGND Digital Ground.
65 PLL_LOCK PLL Lock Indicator.
66 SDO SPI Port Data Output.
67 SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
Pin
No. Mnemonic Description
72 AGND Analog Ground.
73 IPTAT Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 14 μA at 25°C with
approximately 20 nA/°C slope. This pin
should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 μA Reference Current.
76 AVDD33 3.3 V Analog Supply.
77 AGND Analog Ground.
78 AVDD33 3.3 V Analog Supply.
79 AGND Analog Ground.
80 AVDD33 3.3 V Analog Supply.
81 AGND Analog Ground.
82 AGND Analog Ground.
83 OUT2_P Differential DAC Current Output, Channel 2.
84 OUT2_N Differential DAC Current Output, Channel 2.
85 AGND Analog Ground.
86 AUX2_P Auxiliary DAC Current Output, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Channel 2.
88 AGND Analog Ground.
89 AUX1_N Auxiliary DAC Current Output, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Channel 1.
91 AGND Analog Ground.
92 OUT1_N Differential DAC Current Output, Channel 1.
93 OUT1_P Differential DAC Current Output, Channel 1.
94 AGND Analog Ground.
95 AGND Analog Ground.
96 AVDD33 3.3 V Analog Supply.
97 AGND Analog Ground.
98 AVDD33 3.3 V Analog Supply.
99 AGND Analog Ground.
100 AVDD33 3.3 V Analog Supply.
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AD9776A/AD9778A/AD9779A
Rev. A | Page 10 of 60
74 VREF
73 IPTAT
72 AGND
69 CSB
70 RESET
71 IRQ
75 I120
68 SCLK
67 SDIO
66 SDO
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 NC
58 NC
57 P2D<0>
56 P2D<1>
55 P2D<2>
54 DGND
53 DVDD18
52 P2D<3>
51 P2D<4>
65 PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<6>
27
P1D<5>
28
P1D<4>
29
P1D<3>
30
P1D<2>
31
P1D<1>
32
DGND
33
DVDD18
34
P1D<0>
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<13>
41
P2D<12>
42
P2D<11>
43
DVDD18
44
DGND
45
P2D<10>
46
P2D<9>
47
P2D<8>
48
P2D<7>
49
P2D<6>
50
P2D<5>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<13>
18
P1D<12>
19
P1D<11>
20
P1D<10>
21
P1D<9>
22
DGND
23
DVDD18
24
P1D<8>
25
P1D<7>
11
CGND
AD9778A
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
06452-003
Figure 4. AD9778A Pin Configuration
Table 8. AD9778A Pin Function Descriptions
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply.
2 CVDD18 1.8 V Clock Supply.
3 CGND Clock Ground.
4 CGND Clock Common.
5 REFCLK+ Differential Clock Input.
6 REFCLK− Differential Clock Input.
7 CGND Clock Ground.
8 CGND Clock Ground.
9 CVDD18 1.8 V Clock Supply.
10 CVDD18 1.8 V Clock Supply.
11 CGND Clock Ground.
12 AGND Analog Ground.
13 SYNC_I+ Differential Synchronization Input.
14 SYNC_I− Differential Synchronization Input.
15 DGND Digital Ground.
16 DVDD18 1.8 V Digital Supply.
17 P1D<13> Port 1, Data Input D13 (MSB).
18 P1D<12> Port 1, Data Input D12.
19 P1D<11> Port 1, Data Input D11.
20 P1D<10> Port 1, Data Input D10.
21 P1D<9> Port 1, Data Input D9.
Pin
No. Mnemonic Description
22 DGND Digital Ground.
23 DVDD18 1.8 V Digital Supply.
24 P1D<8> Port 1, Data Input D8.
25 P1D<7> Port 1, Data Input D7.
26 P1D<6> Port 1, Data Input D6.
27 P1D<5> Port 1, Data Input D5.
28 P1D<4> Port 1, Data Input D4.
29 P1D<3> Port 1, Data Input D3.
30 P1D<2> Port 1, Data Input D2.
31 P1D<1> Port 1, Data Input D1.
32 DGND Digital Ground.
33 DVDD18 1.8 V Digital Supply.
34 P1D<0> Port 1, Data Input D0 (LSB).
35 NC No Connect.
36 NC No Connect.
37 DATACLK Data Clock Output.
38 DVDD33 3.3 V Digital Supply.
39 TXENABLE
Transmit Enable. In single port mode, this
pin also functions as IQSELECT.
40 P2D<13> Port 2, Data Input D13 (MSB).
41 P2D<12> Port 2, Data Input D12.
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AD9776A/AD9778A/AD9779A
Rev. A | Page 11 of 60
Pin
No. Mnemonic Description
42 P2D<11> Port 2, Data Input D11.
43 DVDD18 1.8 V Digital Supply.
44 DGND Digital Ground.
45 P2D<10> Port 2, Data Input D10.
46 P2D<9> Port 2, Data Input D9.
47 P2D<8> Port 2, Data Input D8.
48 P2D<7> Port 2, Data Input D7.
49 P2D<6> Port 2, Data Input D6.
50 P2D<5> Port 2, Data Input D5.
51 P2D<4> Port 2, Data Input D4.
52 P2D<3> Port 2, Data Input D3.
53 DVDD18 1.8 V Digital Supply.
54 DGND Digital Ground.
55 P2D<2> Port 2, Data Input D2.
56 P2D<1> Port 2, Data Input D1.
57 P2D<0> Port 2, Data Input D0 (LSB).
58 NC No Connect.
59 NC No Connect.
60 DVDD18 1.8 V Digital Supply.
61 DVDD33 3.3 V Digital Supply.
62 SYNC_O− Differential Synchronization Output.
63 SYNC_O+ Differential Synchronization Output.
64 DGND Digital Ground.
65 PLL_LOCK PLL Lock Indicator.
66 SDO SPI Port Data Output.
67 SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
72 AGND Analog Ground.
Pin
No. Mnemonic Description
73 IPTAT Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 14 μA at 25°C with
approximately 20 nA/°C slope. This pin
should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 μA Reference Current.
76 AVDD33 3.3 V Analog Supply.
77 AGND Analog Ground.
78 AVDD33 3.3 V Analog Supply.
79 AGND Analog Ground.
80 AVDD33 3.3 V Analog Supply.
81 AGND Analog Ground.
82 AGND Analog Ground.
83 OUT2_P Differential DAC Current Output, Channel 2.
84 OUT2_N Differential DAC Current Output, Channel 2.
85 AGND Analog Ground.
86 AUX2_P Auxiliary DAC Current Output, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Channel 2.
88 AGND Analog Ground.
89 AUX1_N Auxiliary DAC Current Output, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Channel 1.
91 AGND Analog Ground.
92 OUT1_N Differential DAC Current Output, Channel 1.
93 OUT1_P Differential DAC Current Output, Channel 1.
94 AGND Analog Ground.
95 AGND Analog Ground.
96 AVDD33 3.3 V Analog Supply.
97 AGND Analog Ground.
98 AVDD33 3.3 V Analog Supply.
99 AGND Analog Ground.
100 AVDD33 3.3 V Analog Supply.
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AD9776A/AD9778A/AD9779A
Rev. A | Page 12 of 60
74 VREF
73 IPTAT
72 AGND
69 CSB
70 RESET
71 IRQ
75 I120
68 SCLK
67 SDIO
66 SDO
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 P2D<0>
58 P2D<1>
57 P2D<2>
56 P2D<3>
55 P2D<4>
54 DGND
53 DVDD18
52 P2D<5>
51 P2D<6>
65 PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<8>
27
P1D<7>
28
P1D<6>
29
P1D<5>
30
P1D<4>
31
P1D<3>
32
DGND
33
DVDD18
34
P1D<2>
35
P1D<1>
36
P1D<0>
37
DATACLK
38
DVDD33
39
T
XENABLE
40
P2D<15>
41
P2D<14>
42
P2D<13>
43
DVDD18
44
DGND
45
P2D<12>
46
P2D<11>
47
P2D<10>
48
P2D<9>
49
P2D<8>
50
P2D<7>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<15>
18
P1D<14>
19
P1D<13>
20
P1D<12>
21
P1D<11>
22
DGND
23
DVDD18
24
P1D<10>
25
P1D<9>
11
CGND
AD9779A
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
0
6452-004
Figure 5. AD9779A Pin Configuration
Table 9. AD9779A Pin Function Descriptions
Pin
No. Mnemonic Description
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply. 22 DGND Digital Ground.
2 CVDD18 1.8 V Clock Supply.
3 CGND Clock Ground.
4 CGND Clock Ground.
5 REFCLK+ Differential Clock Input.
6 REFCLK− Differential Clock Input.
7 CGND Clock Ground.
8 CGND Clock Ground.
9 CVDD18 1.8 V Clock Supply.
10 CVDD18 1.8 V Clock Supply.
11 CGND Clock Ground.
12 AGND Analog Ground.
13 SYNC_I+ Differential Synchronization Input.
14 SYNC_I− Differential Synchronization Input.
15 DGND Digital Ground.
16 DVDD18 1.8 V Digital Supply.
17 P1D<15> Port 1, Data Input D15 (MSB).
18 P1D<14> Port 1, Data Input D14.
19 P1D<13> Port 1, Data Input D13.
20 P1D<12> Port 1, Data Input D12.
21 P1D<11> Port 1, Data Input D11.
23 DVDD18 1.8 V Digital Supply.
24 P1D<10> Port 1, Data Input D10.
25 P1D<9> Port 1, Data Input D9.
26 P1D<8> Port 1, Data Input D8.
27 P1D<7> Port 1, Data Input D7.
28 P1D<6> Port 1, Data Input D6.
29 P1D<5> Port 1, Data Input D5.
30 P1D<4> Port 1, Data Input D4.
31 P1D<3> Port 1, Data Input D3.
32 DGND Digital Ground.
33 DVDD18 1.8 V Digital Supply.
34 P1D<2> Port 1, Data Input D2.
35 P1D<1> Port 1, Data Input D1.
36 P1D<0> Port 1, Data Input D0 (LSB).
37 DATACLK Data Clock Output.
38 DVDD33 3.3 V Digital Supply.
39 TXENABLE
Transmit Enable. In single port mode, this
pin also functions as IQSELECT.
40 P2D<15> Port 2, Data Input D15 (MSB).
41 P2D<14> Port 2, Data Input D14.
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AD9776A/AD9778A/AD9779A
Rev. A | Page 13 of 60
Pin
No. Mnemonic Description
42 P2D<13> Port 2, Data Input D13.
43 DVDD18 1.8 V Digital Supply.
44 DGND Digital Ground.
45 P2D<12> Port 2, Data Input D12.
46 P2D<11> Port 2, Data Input D11.
47 P2D<10> Port 2, Data Input D10.
48 P2D<9> Port 2, Data Input D9.
49 P2D<8> Port 2, Data Input D8.
50 P2D<7> Port 2, Data Input D7.
51 P2D<6> Port 2, Data Input D6.
52 P2D<5> Port 2, Data Input D5.
53 DVDD18 1.8 V Digital Supply.
54 DGND Digital Ground.
55 P2D<4> Port 2, Data Input D4.
56 P2D<3> Port 2, Data Input D3.
57 P2D<2> Port 2, Data Input D2.
58 P2D<1> Port 2, Data Input D1.
59 P2D<0> Port 2, Data Input D0 (LSB).
60 DVDD18 1.8 V Digital Supply.
61 DVDD33 3.3 V Digital Supply.
62 SYNC_O− Differential Synchronization Output.
63 SYNC_O+ Differential Synchronization Output.
64 DGND Digital Ground.
65 PLL_LOCK PLL Lock Indicator.
66 SDO SPI Port Data Output.
67 SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
72 AGND Analog Ground.
Pin
No. Mnemonic Description
73 IPTAT Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 14 μA at 25°C with
approximately 20 nA/°C slope. This pin
should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 μA Reference Current.
76 AVDD33 3.3 V Analog Supply.
77 AGND Analog Ground.
78 AVDD33 3.3 V Analog Supply.
79 AGND Analog Ground.
80 AVDD33 3.3 V Analog Supply.
81 AGND Analog Ground.
82 AGND Analog Ground.
83 OUT2_P Differential DAC Current Output, Channel 2.
84 OUT2_N Differential DAC Current Output, Channel 2.
85 AGND Analog Ground.
86 AUX2_P Auxiliary DAC Current Output, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Channel 2.
88 AGND Analog Ground.
89 AUX1_N Auxiliary DAC Current Output, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Channel 1.
91 AGND Analog Ground.
92 OUT1_N Differential DAC Current Output, Channel 1.
93 OUT1_P Differential DAC Current Output, Channel 1.
94 AGND Analog Ground.
95 AGND Analog Ground.
96 AVDD33 3.3 V Analog Supply.
97 AGND Analog Ground.
98 AVDD33 3.3 V Analog Supply.
99 AGND Analog Ground.
100 AVDD33 3.3 V Analog Supply.
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AD9776A/AD9778A/AD9779A
Rev. A | Page 14 of 60
TYPICAL PERFORMANCE CHARACTERISTICS
4
–6
0
CODE
INL (16-BIT LSB)
3
2
1
0
–1
–2
–3
–4
–5
10k 20k 30k 60k50k
40k
06452-005
Figure 6. AD9779A Typical INL
1.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0 60k50k40k30k20k10k
CODE
DNL (16-BIT LSB)
0
6452-006
Figure 7. AD9779A Typical DNL
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 160MSPS
f
DATA
= 200MSPS
f
DATA
= 250MSPS
06452-007
Figure 8. AD9779A In-Band SFDR vs. fOUT,
1× Interpolation
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 160MSPS
f
DATA
= 200MSPS
f
DATA
= 250MSPS
06452-008
Figure 9. AD9779A In-Band SFDR vs. fOUT,
2× Interpolation
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 100MSPS f
DATA
= 200MSPS
f
DATA
= 150MSPS
06452-009
Figure 10. AD9779A In-Band SFDR vs. fOUT,
4× Interpolation
100
50
050
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30 40
f
DATA
= 50MSPS
f
DATA
= 100MSPS
f
DATA
= 125MSPS
06452-010
Figure 11. AD9779A In-Band SFDR vs. fOUT,
8× Interpolation
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AD9776A/AD9778A/AD9779A
Rev. A | Page 15 of 60
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 200MSPS
f
DATA
= 160MSPS
f
DATA
= 250MSPS
06452-011
Figure 12. AD9779A Out-of-Band SFDR vs. fOUT,
2× Interpolation
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 150MSPS
f
DATA
= 100MSPS
f
DATA
= 200MSPS
06452-012
Figure 13. AD9779A Out-of-Band SFDR vs. fOUT,
4× Interpolation
100
50
050
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30 40
f
DATA
= 50MSPS
f
DATA
= 100MSPS
f
DATA
= 125MSPS
06452-013
Figure 14. AD9779A Out-of-Band SFDR vs. fOUT,
8× Interpolation
100
50
040
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30
PLL OFF
PLL ON
06452-014
Figure 15. AD9779A In-Band SFDR, 4× Interpolation,
fDATA = 100 MSPS, PLL On/Off
100
50
080
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60
–3dBFS
0dBFS
–6dBFS
06452-015
Figure 16. AD9779A In-Band SFDR vs. fOUT,
Digital Full Scale
100
50
080
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60
10mA
20mA
30mA
06452-016
Figure 17. AD9779A In-Band SFDR vs. fOUT,
Output Full-Scale Current
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AD9776A/AD9778A/AD9779A
Rev. A | Page 16 of 60
100
50
0120
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
20 40 60 80 100
f
DATA
= 200MSPS
f
DATA
= 250MSPS
f
DATA
= 160MSPS
06452-017
Figure 18. AD9779A Third-Order IMD vs. fOUT,
1× Interpolation
100
50
0 20 40 60 80 100 120 140 160 180 200 220
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
f
DATA
= 160MSPS
f
DATA
= 250MSPS
f
DATA
= 200MSPS
06452-018
Figure 19. AD9779A Third-Order IMD vs. fOUT,
2× Interpolation
100
50
0400
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
40 80 120 160 200 240 280 320 360
f
DATA
= 150MSPS
f
DATA
= 200MSPS
f
DATA
= 100MSPS
06452-019
Figure 20. AD9779A Third-Order IMD vs. fOUT,
4× Interpolation
f
OUT
(MHz)
IMD (dBc)
f
DATA
= 75MSPS
f
DATA
= 125MSPS
f
DATA
= 100MSPS
90
100
80
70
60
50
450 425 400 375 350 325 300 275 250 225 200 175 150 125 100
75 50 25
0
f
DATA
= 50MSPS
06452-020
Figure 21. AD9779A Third-Order IMD vs. fOUT,
8× Interpolation
100
50
0200
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
100
20 40 60 80 120 140 160 180
PLL OFF
PLL ON
06452-021
Figure 22. AD9779A Third-Order IMD vs. fOUT,
4× Interpolation, fDATA = 100 MSPS, PLL On vs. PLL Off
100
95
50
55
0400360
f
OUT
(MHz)
IMD (dBc)
90
80
85
70
75
60
65
40 80 120 160 200 240 280 320
06452-022
Figure 23. AD9779A Third-Order IMD vs. fOUT, over
50 Parts, 4× Interpolation, fDATA = 200 MSPS
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AD9776A/AD9778A/AD9779A
Rev. A | Page 17 of 60
100
50
55
60
65
70
75
80
85
90
95
0 400
f
OUT
(MHz)
IMD (dBc)
80 160 240 36032040 120 200 280
0dBFS
–3dBFS
–6dBFS
06452-117
Figure 24. AD9779A IMD Performance vs. Digital Full-Scale Input over
Output Frequency, 4× Interpolation, fDATA = 200 MSPS
100
50
55
60
65
70
75
80
85
90
95
0 400
f
OUT
(MHz)
IMD (dBc)
80 160 240 36032040 120 200 280
20mA
10mA
30mA
06452-118
Figure 25. AD9779A IMD Performance vs. Full-Scale Output Current over
Output Frequency, 4× Interpolation, fDATA = 200 MSPS
STOP 400.0MHz
SWEEP 1.203s (601 pts)
VBW 20kHz
START 1.0MHz
*RES BW 20kHz
REF 0dBm
*PEAK
Log
10dB
LGAV
51
W1
S3
£(f):
FTUN
SWP
S2
FC
AA
*ATTEN 20dB
EXT REF
DC-COUPLED
06452-023
Figure 26. AD9779A Single Tone, 4× Interpolation,
fDATA = 100 MSPS, fOUT = 30 MHz
STOP 400.0MHz
SWEEP 1.203s (601 pts)
VBW 20kHz
START 1.0MHz
*RES BW 20kHz
REF 0dBm
*PEAK
Log
10dB
LGAV
51
W1
S3
£(f):
FTUN
SWP
S2
FC
AA
*ATTEN 20dB
EXT REF
DC-COUPLED
06452-024
Figure 27. AD9779A Two-Tone Spectrum,
4× Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz
–142
–146
–150
–154
–158
–162
–166
–170
0
f
OUT
(MHz)
NSD (dBm/Hz)
20 40 60 80
0dBFS
–3dBFS
–6dBFS
06452-025
Figure 28. AD9779A Noise Spectral Density vs. Digital Full-Scale over Output
Frequency of Single Tone Input, fDATA = 200 MSPS,
2× Interpolation
–
150
–170
0100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
06452-026
Figure 29. AD9779A Noise Spectral Density vs. fDAC over Output Frequency for
Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS
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AD9776A/AD9778A/AD9779A
Rev. A | Page 18 of 60
–
150
–170
0100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
06452-027
Figure 30. AD9779A Noise Spectral Density vs. fDAC over Output Frequency
with a Single Tone Input at −6 dBFS
–
55
–90
–85
–80
–75
–70
–65
–60
026024022020018016014012010080604020
f
OUT
(MHz)
ACLR (dBc)
06452-300
0dBFS, PLL DISABLED
–3dBFS, PLL DISABLED
–6dBFS, PLL DISABLED
0dBFS, PLL ENABLED
Figure 31. AD9779A ACLR for First Adjacent Band W-CDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.49dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
dBc
–76.75
–80.94
–79.95
dBm
–89.23
–93.43
–92.44
LOWER
dBc
–77.42
–80.47
–78.96
dBm
–89.91
–92.96
–91.45
UPPER
REF –25.28dBm
*AVG
Log
10dB
PAVG
10
W1 S2
*ATTEN 4dB
EXT REF
06452-031
Figure 32. AD9779A W-CDMA Signal, 4× Interpolation,
fDATA = 122.88 MSPS, fDAC/4 Modulation
–
55
–90
–85
–80
–75
–70
–65
–60
026024022020018016014012010080604020
f
OUT
(MHz)
ACLR (dBc)
06452-301
–3dBFS, PLL DISABLED
–6dBFS, PLL DISABLED
0dBFS, PLL ENABLED
0dBFS, PLL DISABLED
Figure 33. AD9779A ACLR for Second Adjacent Band W-CDMA,
4× Interpolation, fDATA = 122.88 MSPS;
On-Chip Modulation Translates Baseband Signal to IF
–
55
–90
–85
–80
–75
–70
–65
–60
026024022020018016014012010080604020
f
OUT
(MHz)
ACLR (dBc)
06452-302
–3dBFS, PLL DISABLED
–6dBFS, PLL DISABLED
0dBFS, PLL ENABLED
0dBFS, PLL DISABLED
Figure 34. AD9779A ACLR for Third Adjacent Band W-CDMA, 4×
Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates
Baseband Signal to IF
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
CENTER 151.38MHz
*RES BW 30kHz
1 –17.87dBm
2 –20.65dBm
3 –18.26dBm
4 –18.23dBm
TOTAL CARRIER POWER –12.61dBm/15.3600MHz
REF CARRIER POWER –17.87dBm/3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
INTEG BW
3.840MHz
3.840MHz
3.840MHz
dBc
–67.70
–70.00
–71.65
dBm
–85.57
–97.87
–99.52
LOWER
dBc
–67.70
–69.32
–71.00
dBm
–85.57
–87.19
–88.88
UPPER
REF –30.28dBm
*AVG
Log
10dB
PAVG
10
W1 S2
*ATTEN 4dB
EXT REF
06452-032
Figure 35. AD9779A Multicarrier W-CDMA Signal,
4× Interpolation, fDAC = 122.88 MSPS, fDAC/4 Modulation
Downloaded from Elcodis.com electronic components distributor

AD9776A/AD9778A/AD9779A
Rev. A | Page 19 of 60
1.5
0
CODE
INL (14-BIT LSB)
10k
1.0
0.5
0
–0.5
–1.0
–1.5
2k 4k 6k 8k
0
6452-033
Figure 36. AD9778A Typical INL
0.6
0
CODE
DNL (14-BIT LSB)
–0.2
–1.0
16k14k12k10k8k6k4k2k
0.4
0.2
0
–0.4
–0.6
–0.8
06452-034
Figure 37. AD9778A Typical DNL
100
50
0400
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
40 80 120 160 200 240 280 320 360
4× 200MSPS
4× 150MSPS
4× 100MSPS
06452-035
Figure 38. AD9778A IMD vs. fOUT, 4× Interpolation
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 250MSPS
f
DATA
= 200MSPS
f
DATA
= 160MSPS
06452-036
Figure 39. AD9778A In-Band SFDR vs. fOUT, 2× Interpolation
–90
0250
f
OUT
(MHz)
ACLR (dBc)
–70
–80
–60
25 50 75 100 125 150 175 200 225
1ST ADJ CHAN
2ND ADJ CHAN
3RD ADJ CHAN
06452-037
Figure 40. AD9778A ACLR, Single Carrier W-CDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = −3 dBFS
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.74dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.884MHz
3.840MHz
3.840MHz
dBc
–76.49
–80.13
–80.90
dBm
–89.23
–92.87
–93.64
LOWER
dBc
–76.89
–80.02
–79.53
dBm
–89.63
–92.76
–92.27
UPPER
REF –25.39dBm
*AVG
Log
10dB
PAVG
10
W1 S2
*ATTEN 4dB
06452-038
Figure 41. AD9778A ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
Downloaded from Elcodis.com electronic components distributor

AD9776A/AD9778A/AD9779A
Rev. A | Page 20 of 60
–
150
–170
0100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
06452-039
Figure 42. AD9778A Noise Spectral Density vs. fOUT for Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
–
150
–170
0100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
06452-040
Figure 43. AD9778A Noise Spectral Density vs. fOUT with Single Tone Input
at −6 dBFS, fDATA = 200 MSPS
0.4
04096
CODE
INL (12-BIT LSB)
–0.4
512 1024 256020481536 3072 3584
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
06452-041
Figure 44. AD9776A Typical INL
0.20
04096
CODE
DNL (12-BIT LSB)
2048
–0.20
512 1024 1536 2560 3072 3584
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
06452-042
Figure 45. AD9776A Typical DNL
100
50
0400
f
OUT
(MHz)
IMD (dBc)
40 80 120 160 200 240 280 320 360
4× 200MSPS
4× 100MSPS
4× 150MSPS
95
90
85
80
75
70
65
60
55
06452-043
Figure 46. AD9776A IMD vs. fOUT, 4× Interpolation
100
50
0100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 250MSPS
f
DATA
= 200MSPS
f
DATA
= 160MSPS
06452-044
Figure 47. AD9776A In-Band SFDR vs. fOUT, 2× Interpolation
Downloaded from Elcodis.com electronic components distributor