Analog Devices EV-ADF4356SD1Z User manual

EV-ADF4356SD1Z User Guide
UG-1062
One Technology Way • P.O. Box 9106 • Norwood, MA02062-9106, U.S.A. • Tel: [phone] • Fax: [phone] • www.analog.com
Evaluating the ADF4356 Microwave Wideband Synthesizer with Integrated VCO
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 13
FEATURES
Self contained board, including ADF4356 frequency
synthesizer with integrated VCO, differential, 122.88 MHz,
temperature controlled crystal oscillator (TCXO), loop
filter (80 kHz), USB interface, and voltage regulators
Windows-based software allows control of synthesizer
functions from a PC
Externally powered by 5.5 V
EVALUATION KIT CONTENTS
EV-ADF4356SD1Z
EQUIPMENT NEEDED
Windows-based PC with USB port for evaluation software
System demonstration platform, serial only (SDP-S)
EVAL-SDP-CS1Z controller board
USB cable (included with the EVAL-SDP-CS1Z)
Power supply (5.5 V)
Spectrum analyzer
50 Ω terminators
ONLINE RESOURCES
Documents Needed
ADF4356 data sheet
EV-ADF4356SD1Z user guide
PLL Software Installation Guide
Required Software
Analog Devices, Inc., ADF4356 software, Version 1.0.10 or
higher
GENERAL DESCRIPTION
The EV-ADF4356SD1Z evaluates the performance of the ADF4356
frequency synthesizer with an integrated voltage control (VCO) for
phase-locked loops (PLLs). The evaluation board contains the
ADF4356 frequency synthesizer with an integrated VCO, a
differential 122.88 MHz reference (TCXO), a loop filter, a USB
interface, power supply connectors, and subminiature Version A
(SMA) connectors. A USB cable is included to connect the
board to a PC USB port.
This board requires an SDP-S (shown in Figure 1, but not supplied
with the kit). The SDP-S allows software programming of the
EV-ADF4356SD1Z.
When working with the evaluation board and for full
specifications of the device, consult the ADF4356 frequency
synthesizer data sheet. For easy programming of the
synthesizer, download the Windows®-based software from the
ADF4356 product page.
EVALUATION BOARD PHOTOGRAPH
15087-001
Figure 1.

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TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents................................................................... 1
Equipment Needed........................................................................... 1
Online Resources.............................................................................. 1
General Description ......................................................................... 1
Evaluation Board Photograph......................................................... 1
Revision History ............................................................................... 2
Getting Started .................................................................................. 3
Software Installation Procedures................................................ 3
Evaluation Board Setup Procedures........................................... 3
Evaluation Board Hardware ............................................................ 4
Power Supplies .............................................................................. 4
RF Output.......................................................................................4
Loop Filter ......................................................................................4
Reference Source ...........................................................................4
Default Configuration ..................................................................4
Evaluation Board Setup ................................................................5
Evaluation Board Software...............................................................6
Main Controls................................................................................6
Evaluation and Test ...........................................................................7
Evaluation Board Schematics and Artwork ...................................8
Ordering Information.................................................................... 12
Bill of Materials........................................................................... 12
REVISION HISTORY
04/2017—Rev. 0 to Rev. A
Changes to Features, Evaluation Kit Contents, Equipment
Needed, Online Resources Sections, and Figure 1....................... 1
Changes to Figure 2.......................................................................... 3
Changes to Evaluation Board Hardware Section and Deleted
Figure 3, Renumbered Sequentially ............................................... 4
Changes to Figure 3.......................................................................... 5
Changes to Evaluation Board Software, Step 5 and Figure 5...... 7
Changes to Figure 6.......................................................................... 8
Changes to Figure 7.......................................................................... 9
Deleted Figure 8, Renumbered Sequentially................................. 9
Changes to Figure 8, Figure 9, and Figure 10 ............................. 10
Deleted Figure 11, Renumbered Sequentially............................. 11
Changes to Figure 11 ...................................................................... 11
Changes to Figure 12...................................................................... 12
Changes to Table 1.......................................................................... 13
10/2016—Revision 0: Initial Version

EV-ADF4356SD1Z User Guide UG-1062
Rev. A | Page 3 of 13
GETTING STARTED
SOFTWARE INSTALLATION PROCEDURES
See the ADF4356 product page for the EV-ADF4356SD1Z
control software. For the software installation procedure, see
the PLL Software Installation Guide.
EVALUATION BOARD SETUP PROCEDURES
To run the software,
1. Click the ADF4356 file on the desktop or from the Start
menu.
2. On the Select Device and Connection tab, choose
ADF4356 and SDP board (black), and then click Connect
(see Figure 2).
3. When connecting the board, allow 5 sec to 10 sec for the
label on the status bar to change.
Under the File menu, the current settings can be saved to, and
loaded from, a text file.
15087-002
Figure 2. Software Front Panel Display—Select Device and Connection

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EVALUATION BOARD HARDWARE
The EV-ADF4356SD1Z requires the SDP-S platform that uses
the EVAL-SDP-CS1Z (SDP-B is not recommended).
The EV-ADF4356SD1Z schematics are shown in Figure 6, and
Figure 7. The evaluation board silkscreen is shown in Figure 8.
POWER SUPPLIES
The board is powered by a 5.5 V power supply connected to the
red and black banana connectors. Connect the red connector to
a 5.5 V power supply and the black connector to ground. Reversal
of the connections to the red and black banana connectors can
cause catastrophic failure of the HMC1060 low noise regulator.
The HMC1060 low noise regulator is configured to supply 5 V
for the charge pump and VCO supply pins, and 3.3 V for the
remaining supply pins.
RF OUTPUT
The EV-ADF4356SD1Z has two pairs of SMA output
connectors: RFOUTA+/RFOUTA− and RFOUTB+/RFOUTB−
(differential outputs). Because they are sensitive to impedance
mismatch, connect the RF outputs to equal load impedances.
If only one port of a differential pair is used, terminate the
complementary port with an equal load terminator (in general,
a 50 Ω terminator).
LOOP FILTER
The loop filter schematic is included in the board schematic in
Figure 6. For lowest rms phase noise, use the following
components (that are inserted on the evaluation board) with a
0.9 mA charge pump current:
•C22 = 120 pF, C29 = 2700 pF, C33 = 22 pF
•R33 = 2.7 kΩ, R34 = 10 kΩ
Narrower loop filter bandwidths have lower spurious signals.
REFERENCE SOURCE
The evaluation board contains a 122.88 MHz differential output
TCXO from Vectron International. If preferred, the user may
supply either a single-ended or differential reference input to
REFINA/REFINB SMA connectors. When using an external
reference, remove R7 to disconnect the power rail to the TCXO.
To use a single-ended REFINx, connect a low noise, 122.88 MHz
reference source to the REFINA SMA connector. Remove Resis-
tor R6 (100 Ω) and insert R10 (50 Ω) and R15 (50 Ω).
To use a differential REFINx, connect the differential signal to
the REFINA and the REFINB SMA connectors. The differential
REFINA/REFINB SMA connectors can operate to a 500 MHz
input frequency.
DEFAULT CONFIGURATION
All components necessary for local oscillator (LO) or clock
generation are inserted on the board. This board is shipped with
the ADF4356 synthesizer with an integrated VCO, a differential
122.88 MHz reference TCXO, and a 80 kHz loop filter (ICP =
0.9 mA).

EV-ADF4356SD1Z User Guide UG-1062
Rev. A | Page 5 of 13
EVALUATION BOARD SETUP
SPECTRUM
ANALYZER
PC
EXTERNAL DC
SUPPLY
TCXO
ADF4356
LOOP FILTER
LOCK
DETECT
LED
REFERENCE
IN/OUT
SDP-S BOARD
REFINA
REFINB
RFOUTB–
RFOUTA–
RFOUTA+
RFOUTB+
REFERENCE
(OPTIONAL)
SIGNAL GENERATOR
EXTERNAL DC
GND
USB
15087-004
Figure 3. Evaluation Setup Block Diagram

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EVALUATION BOARD SOFTWARE
MAIN CONTROLS
The Main Controls tab (see Figure 4) selects the RF and user
configurable register settings. Consult the register descriptions
of the ADF4356 data sheet for details. Default settings are
recommended for most registers.
In the RF Settings section, ensure that the VCOout (MHz) box
equals the VCO frequency. Set the Output divider dropdown
menu to give the required RFoutA± (MHz).
Ensure that the Reference freq. value equals the applied
reference signal. The PFD frequency is calculated from the
reference frequency, the R counter, the reference doubler, and
the reference divide by 2. Ensure that the value in PFD (MHz)
matches the value specified in the loop filter design.
In the Register 4 section, program the CP current dropdown
menu to match the value used for the loop filter design.
15087-005
Figure 4. Software Front Panel Display—Main Controls

EV-ADF4356SD1Z User Guide UG-1062
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EVALUATION AND TEST
To evaluate and test the performance of the ADF4356, use the
following procedure:
1. Install the ADF4356 software (see the PLL Software
Installation Guide).
2. Follow the hardware driver installation procedure
(Windows XP only).
3. Connect a 50 Ω terminator to RFOUTA−.
4. Connect the EV-ADF4356SD1Z board to the SDP-S board.
5. Connect the 5.5 V power supply to the banana connectors
and power on the board.
6. Connect the USB cable from the SDP-S board to the PC.
7. Run the ADF4356 software.
8. Select ADF4356 and SDP board (black) in the Select
Device and Connection tab of the software front panel
display window (see Figure 2).
9. Click the Main Controls tab, and set the VCOout (MHz)
to a frequency of 5000 MHz.
10. Click Write Init. Seq.
11. Connect the spectrum analyzer to SMA connector
RFOUTA+, see Figure 3 for a typical evaluation setup.
12. Measure the output spectrum and single-sideband phase
noise.
Figure 5 shows a phase noise plot of the SMA RFOUTA+ equal
to 5 GHz.
–80
–170
–160
–150
–140
–130
–120
–110
–100
–90
1k 10k 100k 1M 10M 30M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
15087-020
M1
M2
M3
M4
10kHz
–102.41dBc/Hz
400.39063kHz
–117.2dBc/Hz
1MHz
–131.71dBc/Hz
10MHz
–152.33dBc/Hz
Figure 5. Single-Sideband Phase Noise

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EVALUATION BOARD SCHEMATICS AND ARTWORK
15087-021
PLACE NEAR ADF4356
VREGVCO DECOUPLING
VVCODECOUPLING
CENTER TOCENTER ON PCB
MATCHED LINE WIDTH'S TRACE WIDTH = 380UM
RF CHOKE
0201
0302
0201
0201
0201
0402
ADF4356
SHIELD SIGNALS WITH VIAS
PLACE ON BOTTOM SIDE OF PCB SPITRACES
LOCK DETECT
0302
REFINA AND REFINB ARE SPACED 15MM
0402
NOSTUB.
PLACE R4,C4 CLOSE TO VTUNE INPU
DNI
122.88MEGHZ
32K243-40ML5
DNI
0.1UF
1000PF
22PF
0
1
0.1UF
DNI
0.1UF
0
0
100PF
0
0
0
0
DNI 10K
32K243-40ML5
0
0 DNI
120PF
0
1000PF
0.1UF
0
0
0
DNI
0
DNI
0
0
10UF
0.1UF
0.1UF
1UF
2700PF
0.1UF
DNI
DNI
10UF
ADF4356BCPZ
10UF 10UF
0.1
0.1
0.1UF 0.1UF
75K
HMC1060LP3E
50
571-0100 571-0500
4.7UF
DNI
120PF
120PF
120PF 120PF
100NH
100NH
1000PF
1000PF
7.4NH
0.1UF 0.1UF
1.8K
1.8K
1.8K
1UF
1UF
32K243-40ML5
32K243-40ML5
10PF 10PF
100PF
100PF
TBD0402
7.4NH
1.5K
50
1UF
100
500
1UF
0.1UF
DNI
1000PF
1000PF
0.1UF
0.1UF
10UF
0.1UF
1000PF
1
10UF
0.1UF
0
2.7K
10K
R27
R32
R25
R34
R33
C29
C33
C22
C9
C20
C18
C19
R24
C4
R23
R26
R36
R35
VRF
GND1
R6
C8
R5
R1
R2
C7
C3 C2
C1
U1
VSUPPLY_ALT
GND
CE
R22
GND2
U3
C39
R9
C30
C12
C13
C35
C36
R8
C17
C34
R15R10
C40
C41
C31
+5V VDD
C15 C16C14
VSUPPLY
C5
R3
VTUNE
REFINB
REFINA
C68
C67 C66
C65
C63
C64
L5
L8
RFOUTB-
R4
C26
C6
L1
C21
C24
C23
L2
C28
C25
C32
DATALE
CLK
RMUX
R20
RFOUTB+
RFOUTA-
RFOUTA+
R18
C27
R17
PDBRF
R11
Y1
R16
C10
C44
C45
C43
R12
R13
R14
C11
R7
MUXOUT
R19
DS1
R21
REFINB
REFINA
VRF
RFOUT_A-
VDD
VRF
+5V
CREG1
RFOUT_A+
VDD
DATA
VDD
CLK
RFOUT_B- RFOUT_B+
VRF
VRF
LE
VDD
VRF VRF
RFOUTA- RFOUTB-
CE
VRF
RFOUTA+
VRF
CREG2
+5V
VDD
MUXOUT
VRF
PDBRF
RFOUTB+
1
1
9 10 11 12
1
4
7 6
14 15
8
PAD
5
13 16
2
3
2 1 2 1
17 20 10 19 23
6
24
31
22
15 14 12 11
28 29
26
PAD
30
3
27
2
32
25 7
8
1 4
16
5
21
18
13
9
1
5 4 3 2
543 2
1
6
4
2
5
1 3
GND
GND
GND
GND
VDD
CFO
FO
GND
E/D
NC
GND
GND
GND
GND
GND GND GND
GND
GND
GND
GND
GND
PAD
HV1 RD1 RD2 HV2 VR1
VR2 VR3 VR4
PTATB RD4 RD3 HV3
REF
EN
GND
VDD
GND
GND
GND
PAD
AGNDVCO
AGNDVCO
AGNDRF
AVDD
AVDD
CREG2
SDGND
MUXOUT
REFINA REFINB
DVDD
PDBRF
CREG1
VBIAS
VREF
RSET
VTUNE
VREGVCO
VVCO
RFOUTB-
RFOUTB+
RFOUTA-
RFOUTA+
VRF
AGND
CPGND
CPOUT
VP
CE
LE DATA CLK
GND
GND
GND
GNDGND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IN
IN
IN IN IN IN
GND
GND
GNDGND
GND GND
GND
GND
GND
GND
GND
GND
Figure 6. Evaluation Board Schematic—Page 1

EV-ADF4356SD1Z User Guide UG-1062
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15087-022
1.5K
0
1.5K
TBD0603
0
0
DNI
0
24LC32A-I/MS
DNI
100K
DNI
1.5K
100K
DNI
0
R31
R30
R29
R28
SDA
SCL
RMUXOUT
RDATA
RLE
RCLK
RE3
RE2
RE1
UE1
CN1
CN1
CLK
MUXOUT
DATA
VIO_+3-3V
PDBRF
SCL_0
SDA_0
CE
LE
LE
7
4
8
5
6
3
2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
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98
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100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
IN
IN
IN
IN
IN
IN
IN
GND
GND GND GND
VSS
VCC
WP
A2
A1
A0
SCL SDA
GNDGND
Figure 7. Evaluation Board Schematic—Page 2

UG-1062 EV-ADF4356SD1Z User Guide
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15087-023
Figure 8. Evaluation Board Silk Screen
15087-024
Figure 9. Evaluation Board Layer 1—Primary
15087-025
Figure 10. Evaluation Board Layer 2—Ground